KR20060097303A - Hybrid ferromagnet/si semiconductor spin device using silicon on insulator (soi) and its fabrication method - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hybrid magnetic / semiconductor spin device using a SOI substrate and a method for manufacturing the same. Especially, the present invention is applicable to memory and logic devices from spin valve effect obtained by injecting electrons spin-polarized from ferromagnetic material into Si semiconductor at room temperature. A spin implantation device and a spin field effect transistor are disclosed.

According to the present invention, an SOI substrate is formed on an insulating film, a source region of a magnetic material is formed on the SOI substrate, and a spin channel region having a one-dimensional structure is formed on the SOI substrate through which spin injected into the source region passes. A hybrid magnetic / semiconductor spin device is provided, wherein a drain region of a magnetic material is formed on the SOI substrate on which the spin passing through the spin channel region is detected.

Accordingly, the present invention achieves a spin valve effect, which is not realized in the conventional magnetic / Si semiconductor device, and controls the electric charge of the carrier only by the electric field in the semiconductor transistor, whereas in the hybrid magnetic / semiconductor device, the magnetic material is used as the source and the drain. By injecting and detecting the spin into the SOI semiconductor, the spin can be applied to memory and logic devices using the spin of the carrier.

Spin injection element, SOI, magnetic / semiconductor heterojunction structure, magnetoresistance, spin valve

Description

Hybrid magnetic material / semiconductor spin device using SOI substrate and manufacturing method thereof HYBRID FERROMAGNET / SI SEMICONDUCTOR SPIN DEVICE USING SILICON ON INSULATOR (SOI) AND ITS FABRICATION METHOD}

1 is a plan view of a spin injection device according to the present invention.

2 is a cross-sectional view of the spin injection device according to the present invention.

3 is a plan view showing an actual spin device manufactured according to the present invention.

4 is a graph showing current-voltage characteristics between electrodes / silicon measured to confirm the junction characteristics between the ferromagnetic electrodes and the semiconductor.

5A and 5B are graphs showing anisotropic magnetoresistance curves of a NiFe magnetic body having an electrode size of 2 µm in width x 9 µm in length and a magnetic body having a width of 200 nm × 18 µm in length, respectively.

6 is a graph showing the resistance-magnetic force showing the spin valve effect measured from a spin device manufactured at 10K.

FIG. 7 is a plan view of the one-dimensional Si conduction channel immediately after electron beam photodetection and argon ion milling in an SOI mesa structure.

8 is a cross-sectional view illustrating a structure of a spin polarization field effect transistor (spin FET).

The present invention relates to a hybrid magnetic material / semiconductor spin device using an SOI substrate and a method of manufacturing the same. More particularly, the present invention relates to a hybrid magnetic material / semiconductor spin device using a thin Si semiconductor formed in a thickness of 50 to 300 nm on an insulator.

Up to now, semiconductor electronic devices control only two types of electrons, namely, charges of carriers (electrons with negative charges and holes with positive charges), ignoring spin, among electric charges and spins. In other words, the device is implemented using only the negative electric charge among the two inherent physical properties of the electron (charge, spin), but recently, spin-dependent electron transport has been developed. Efforts to develop electronic devices in consideration of charge and spin degrees of freedom at the same time are attracting much attention in the scientific world. Compared with the existing electronic devices, it has the characteristics such as non-volatility, which is inherent in spin electronic devices, and ultra-high speed and ultra low power, which will lead the revolutionary growth of next-generation electronic devices with the development of nanotechnology. It is expected to be.

A major concern in spintronics research is to implement transistors for memory and logic by considering charge and spin degrees of freedom at the same time. In order to implement a transistor using spin-polarized electrons, spin-polarized electrons are injected from a source magnetic material into a semiconductor, move while maintaining the direction of spin in a semiconductor, and control to change resistance by controlling a direction of spin by applying a gate voltage, Four mechanisms, such as detecting the moved spin polarized electrons in the drain magnetic material, must be fully operated.

Currently, research on spin injection that injects spin electrons from a magnetic metal into a paramagnetic metal or a semiconductor is actively being conducted. Effective spin injection has been reported to cause interesting phenomena such as spin accumulation. In 1993, a paramagnetic metal such as Au is sandwiched between two magnetic metals. A spin switch is used to inject spin into a paramagnetic metal using one magnetic metal as a spin source and to detect spins injected into the other magnetic metal. Bipolar spin transistors were fabricated as devices.

As described above, the spin transistor made of metal has been experimentally proved as a spin injection phenomenon. However, the spin transistor composed of metal has a limitation in being used as a memory device due to its low impedance. Spin injection and transfer from magnetic metals to semiconductors is a major area of interest in spintronics research, and this technology is recognized as the basis for the development of spin-enabled field effect transistors. Recently, a technique for injecting a spin from a magnetic metal into a thin film of InAs and GaAs based two-dimensional electron gas has been developed, and a gate for changing resistance by controlling precession of the injected spin using a gate voltage. Effects are also reported. However, very little research has been carried out on spin injection and spin devices in Si, which are currently the most widely used in complementary metal oxide semiconductors (CMOS). This is understood because the spin diffusion distance in Si is short and the mobility of charge is slow compared to the group 3-5 semiconductor having a two-dimensional electronic structure.

In 1996, Steven Chou et al. ( ₁₎ applied 10 nm thick SiO ₂ oxide on the surface by thermal oxidation method on a bulk n-type Si substrate, and then spin valve effect in a device in which two Ni electrodes with 75 and 150 nm width and 300 nm spacing, respectively, were deposited. However, firstly, the contact resistance is very high as several tens of M Ohm and the noise ratio is very large. Second, the switching field is unclear due to the magnetostatic interaction between the two Ni electrodes. Since the Si channel is planar between the electrodes, the local Hall effect due to the stray field of the two electrodes can dominate, and the magnetoresistance effect obtained from the above device is spin injection and transfer phenomenon to Si. It is difficult to see the signal observed from.

In 2004, Woo Young et al. Etched a Si substrate to reduce the contact resistance and then formed a magnetic electrode therein to increase the contact area between Si and the magnetic metal and reduce the contact resistance by shortening the charge path from the electrode to the electrode in a straight line. Has devised and reported. In this way, the contact resistance could be reduced, but the leakage current was large by using a bulk Si substrate as indicated by the above problem of S. Chou's device, and the anisotropic magnetoresistance of the two magnetic electrodes in spin valve measurement It is difficult to obtain a spin valve in which magneto-resistance is mainly observed, and the spin polarized in the magnetic electrode is injected into the Si, moved through the Si channel, and the spin moved in another magnetic electrode is observed. As a result, the spin valve device has not been realized using Si as a channel.

Therefore, in the present invention, firstly, by using an SOI substrate having a thin Si channel on the insulator, the leakage of the spin is prevented, and second, a spin valve signal is formed on the Si by forming a narrow, long one-dimensional channel of nanometer size instead of the planar channel. The spin balance device is realized by excluding local Hall effect and fringe field effect.

Implementing a spin device in Si, which is widely used in semiconductor devices, has a great advantage in terms of application and practical use of the spin device. The nanometer-sized process technology and equipment used in the conventional CMOS devices can be used as they are, so the process compatibility is excellent and the price is very low, which is expected to contribute to the development of spin devices.

Accordingly, the present invention is to solve the above problems, an object of the present invention is spin injection device and spin that can be applied to memory and logic devices from the spin valve effect obtained by injecting electrons spin-polarized from a ferromagnetic material into a Si semiconductor at room temperature The present invention provides a method for manufacturing a field effect transistor.

Existing patents and researches were conceptual patents that can produce spin field effect transistors in the same way for all semiconductor materials (including Si and Ge) from experimental results obtained from two-dimensional electronic structures of group 3-5 semiconductors (GaAs, InAs). In the present invention, the semiconductor used as the spin transfer channel is limited to Si, and the design and process of the device for implementing the spin valve effect, which has not been discovered by anyone in the spin device using Si, and the gate voltage applied therefrom to Si. A method of fabricating a Si-based spin field effect transistor is specified in detail by controlling the precession of the implanted spin.

As the technical idea for achieving the above object of the present invention

An SOI substrate is formed on the insulating film, a source region of a magnetic material is formed on the SOI substrate, a spin channel region having a one-dimensional structure is formed on the SOI substrate through which the spin injected into the source region passes, and the spin channel region is formed. A hybrid magnetic material / semiconductor spin element is formed on the SOI substrate on which the passed spin is detected.

At this time, the magnetic material is a magnetic metal having a large spin polarization (spin polarization) is selected from Fe, Co, Ni, FeCo, NiFe, or any one selected from magnetic semiconductors such as GaMnAs, InMnAs, GeMn, GaMnN, GaMnP, ZnMnO, etc. Can be. In addition, a half metal having a spin polarization of 100% may be used, such as La _(1-x) Sr _x MnO ₃ (LSMO), CrO _2, or the like.

The semiconductor is formed of a Si thin film substrate (SOI) having a thickness of 50 to 300 nm formed on a single crystal silicon (Si) substrate or an insulator (SiO ₂ ) having a thickness of 50 to 400 nm, and the spin channel region is formed of silicon (Si) or SOI (Si). on Insulator).

The source region and the drain region have a line width in the range of 20 nm to 50 μm according to the type of device to be applied, and the line widths are formed differently so that the spin switching is antiparallel in a certain magnetic range, but the line width is the same. Both of the source or the drain includes antiparallel switching magnetic field ranges by using a pinned layer / free layer stack by an antiferromagnetic exchange bias. In addition, even if the same line width includes the use of two ferromagnetic materials having different coercive force (Coercive force) to selectively anti-parallel switching magnetic field range. The interval between the source region and the drain region is suitably in the range of 10 nm to 5 μm.

In addition, according to the present invention, a channel region having a length of 0.1 to 5 µm and a width of 0.02 to 2 µm having a length of 1 to 100 carriers is formed on an SOI substrate, and the surface of the semiconductor substrate on the left and right sides of the channel is etched. The present invention provides a method of manufacturing a hybrid magnetic material / semiconductor spin device including filling an insulator in left and right etched regions of and electrically isolating adjacent channels and forming source and drain regions with magnetic materials in the channel region.

In this case, the contact resistance between the magnetic material and the semiconductor may be ohmic or schottky. Meanwhile, an interlayer such as Al ₂ O ₃ , SiO _2, or the like may be inserted between the magnetic metal and the semiconductor in a thickness range of 0.5 to 2 nm to generate spin injection by tunneling.

In particular, the present invention is a very sensitive device using a nano-sized ferromagnetic electrode should be made very high degree of cleanliness and step movement when manufactured.

Hereinafter, a method of manufacturing a magnetic body / semiconductor device according to the present invention and its physical characteristics will be described in detail with reference to the following examples.

As a substrate, an SOI wafer having a 51 nm thick N-type silicon thin film on a 360 nm thick SiO ₂ insulating layer was prepared. In order to prevent leakage current on the silicon surface, the silicon dioxide layer (SiO ₂ ) was grown to a thickness of about 1 to 10 nm using a thermal oxidation method. After the oxide film was grown, the specimen was cut into 10 × 10 mm using a cutting saw.

In order to remove the source of contamination with the external environment prior to the experiment progress of the prepared sample was performed a cleaning process as shown in [Table 1]. First, the surface organic matter remaining for 10 minutes in a high temperature acidic solution mixed with TCE, Acetone, Methanol, DI water, and then mixed at a ratio of H ₂ SO ₄ : H ₂ O ₂ (4: 1). After completely removing the residual metal and finally, washed with DI water for 10 minutes and dried using nitrogen gas.

Silicon Wafer Cleaning Process Solvent Removal One Immerse in boiling trichloroethylene (TCE) for 3 min. 2 Immerse in boiling acetone for 3 min. 3 Immerse in boiling methyl alcohol for 3 min. 4 Wash in DI water for 3 min. Heavy metal clean One Immerse in a solution of H ₂ SO ₄ : H ₂ O ₂ (4: 1) for 10min at a temperature of 120 ℃ 2 Quench the solution under running DI water for 1 min. 3 Wash in running DI water for 10 min. 4 N ₂ Blowing.

After washing, the Mesa structure having a width of 18 μm was patterned by using a photoexposure process, and the remaining portions except Mesa were argon (Ar) ion milled to completely remove the 51 nm Si film. At this time, if the TaO insulating film is deposited by sputtering and the photosensitive agent is removed, a mesa structure surrounded by an insulator can be obtained. After forming the carrier moving channel of the one-dimensional structure inside the mesa structure by patterning with an electron beam exposure apparatus, a trench was fabricated by ar ion milling an electron beam photosensitive agent (ZEP520A) with a mask.

After the milling process, the TaO insulating layer was filled in the etched portion and the photoresist was lifted off to form a channel having an accurate line width and depth. The electron beam exposure process uses an electron gun controlled by a computer without using an exposure mask, unlike a general photoexposure process (photoexposure process). In order to obtain the spin valve effect of the electrode by the direction of the magnetic field on the conductive channel of the one-dimensional structure, the size of the source and the detector are 200 nm in width, 18 μm in length (axis ratio 1:90), 1.5 μm in width, The electron beam exposure was carried out with a length of 9 mu m (axial ratio 1: 6). Since the width and spacing of the electrodes were smaller than microns, they were patterned with an electron beam exposure apparatus. The electron beam was exposed on the multilayer photoresist and then developed in a MIBK: IPA (3: 1) solution. In order to remove moisture from the silicon substrate, the multilayer electron beam photoresist was subjected to free baking at 160 ° C. for 2 minutes, and then applied PMMA 495K and PMMA 950K A4 at 6000 rpm using a spin coater, followed by soft baking at 180 ° C. Performed for a minute to form a thickness of 300nm.

At this time, the reason why the photoresist film is raised in a multi-layer rather than a single layer is to form a layer having different molecular weights so that the lower photoresist film having a lower molecular weight is developed more widely to facilitate a lift-off process after electrode deposition. It is for.

After the patterning process, a ferromagnetic electrode was deposited using a DC magnetron sputtering system. Prior to the deposition, it was necessarily immersed in BOE (buffered oxide etchant) solution for a while to remove the natural oxide film generated during the movement in the previous step, washed thoroughly and then mounted in a vacuum chamber. The reason for the thorough removal of the oxide film is to ensure proper injection and detection of spin electrons between silicon and the electrode. Electrode deposition is also presputtered with Fe ₁₆ Co ₈₄ (spin polarization: 52%) for about 10 minutes before the process, to maintain an initial vacuum of 1 × 10 ^-8 torr or less to remove contaminants from the chamber. After the sputtering, deposition of the electrode was carried out in earnest.

Fe ₂₀ Ni ₈₀ (spin polarization 48%) was used as another electrode. In order to form an easy magnetization axis of the ferromagnetic electrode, deposition was performed at 60 nm thickness by attaching a magnet in the direction of the major axis of the electrode. On the other hand, in order to prevent surface oxidation of the electrode in the air, tantalum (Ta) was stacked 5 nm directly thereon to form a protective film. Deposition of the ferromagnetic electrode may be used a variety of known deposition methods in addition to the applied sputtering.

After the deposition of the electrode is completed, the photoresist film used at the time of patterning is put in a container containing acetone by a lift-off process and soaked for about 24 hours until the photoresist film is completely removed. At this time, since the ferromagnetic electrode is very fine size, care must be taken not to short-circuit during the lift-off process.

1 and 2 are plan, cross-sectional schematic diagrams of a Si-based spin injection device manufactured by the above process. Referring to FIG. 1, several 200 nm wide spin conduction channels 14 are formed on an Si mesa structure 13 having a width of 18 μm, and insulating layers 15 such as TaO and SiO 2 are insulated between the channels. The periphery of the mesa structure was also planarized with the insulating film 15 to prevent the short circuit of the Ti / Au lead wire. It can be seen that two magnetic electrodes 11 and 12 having different widths are formed on the channel as the source and the drain 16.

2 shows the structure of an SOI substrate and the device fabricated on the substrate. In the SOI substrate, a SiO ₂ insulating film 25 having a thickness of 360 nm is formed on a bulk Si structure 26, and a Si on insulator 24 having a thickness of 50 nm is formed thereon. A mesa structure 28 is formed in the Si thin film, and the mesa periphery is planarized with a TaO insulating film 29. An Si channel 23 having a width of 200 nm is etched into the Si mesa structure, and the channel is filled with a TaO insulating film 27. The ferromagnetic electrode 21 is formed on the thus formed Si channel, and the electrode is in contact with the Ti / Au connecting line 22.

At this time, the contact portion of the connecting line and the ferromagnetic electrode must be on the TaO insulating film. If contact is made on Si, electrons that are not polarized from the Ti / Au line are directly injected into Si, which is a major cause of noise increase. The polarized spin through the ferromagnetic electrode flows through the lower one-dimensional Si channel, and the upper and lower Si channels are insulated with SiO ₂ and move only into the 50-nm-thick one-dimensional Si channel structure 23. Can be reduced.

3 is a view of an actual spin device manufactured by the above process. Identification numbers 31 and 32 represent sources and drains of magnetic materials having different widths, respectively, 33 is a Si mesa structure, 35 is a TaO insulating film formed to planarize after forming a mesa structure, and 34 is formed inside a Si mesa structure. Si channel, 37 is a TaO insulating film between channels, 36 is a Ti / Au connection line.

Since the device implemented as the above structure is very small in size, it is impossible to measure directly. Therefore, it can be measured by making a conductor with a very small resistance and bonding it to a nano-sized electrode. For this purpose, it is important to select a material that can transfer the applied voltage applied to the ferromagnetic electrode without dissipation, and to design the pad to achieve an optimal ohmic junction between the electrode and the pad.

The material chosen for this is gold (Au). However, the direct deposition of gold on a silicon substrate improves adhesion by depositing titanium (Ti) between the two materials because the adhesion between the two materials is not good. Since the contact pad should be formed using a photolithography process, a pad designed on a glass mask having a chromium (Cr) film was fabricated. Patterning is performed using a photoexposure apparatus under optimum conditions (AZ-5214 photoresist is applied onto the specimen, rotated at 4000 rpm in a spin coater, and baked for about 15 minutes in an oven at 75 ° C. After manufacturing by sensitizing for about 4.5 seconds, it was developed by immersing in a developing solution.

After thoroughly cleaning the patterned specimen, the above-mentioned two materials (Ti / Au) were sequentially e-beam evaporated (e-beam) with the initial vacuum of 2 × 10 ^-6 torr in a thickness of 10 nm and 80 nm. evaporator). After the pad was deposited in this way, the photoresist applied for patterning was removed using acetone to perform a lift-off process. In this way, a silicon nano spin device using the spin valve effect was fabricated.

Figure 4 shows the current-voltage characteristics between the electrode / silicon measured to confirm the junction characteristics between the ferromagnetic electrode and the semiconductor. As shown, the schottky junction was found to be perfectly bonded without any contaminant between the two junctions. In addition, the Schottky barrier height due to the Schottky barrier between electrodes / silicon was calculated through the following equation.

는 쇼트키 장벽의 높이이고,

는 리차드슨 상수이다. 이 식을 통하여 장벽의 높이를 구한 결과 0.49 eV를 얻을 수 있다.Where

Is the height of the Schottky barrier,

Is the Richardson constant. From this equation, 0.49 eV can be obtained from the height of the barrier.

5A and 5B show anisotropic magneto-resistance (AMR) behavior of two magnetic bodies having different widths and lengths used as source and drain regions of the magnetic body / Si spin device. FIG. 5A is an AMR observed in a NiFe magnetic body having a width of 2 μm × a length of 9 μm (axis ratio 1: 4.5), which is a magnetoresistance caused by spin-orbit coupling according to a difference between a current direction and a spin direction. In FIG. 5A a negative peak appears in the field of about 40 Oe, with a ratio of about 0.2%. It can be seen that the switching field of this electrode is about 40 Oe because the direction of spin rotates at the magnetic force at which this negative peak appears.

Meanwhile, another magnetic material of FIG. 5B is 200 nm in width x 18 μm in length (axial ratio 1:90), and in the AMR measurement, no negative peak was observed at a specific magnetic force as shown in FIG. 5B. This is because when the width of the magnetic material is very narrow compared to the length, the spin is difficult to rotate and does not rotate at the same time in a specific field.As a result, the coercivity due to the shape magnetic anisotropy of the electrode having a large line width is smaller than that of the smaller wire width electrode. You can see that the switch works well.

Figure 6 shows the spin valve effect observed at 10K. In the silicon nanospin device according to the present invention, the resistance change is caused by injecting electrons spin-polarized from the first ferromagnetic electrode into silicon when the magnetic field is changed in the longitudinal direction of the electrode (ie, the longitudinal direction). It means transporting through the silicon without losing that information, detecting it at the second drain, and measuring the electrical signal that changes accordingly. The source and drain regions are NiFe magnetic thin films each having a width of 1.5 m × 9 m (axial ratio 1: 6) and a width of 0.2 m × 18 m (axial ratio 1:90). In the field where the magnetization directions of the two electrodes are anti-parallel, the resistance is increased, a positive peak is generated, and the resistance-field curve is decreased in the arrangement in which the magnetization directions are parallel.

From this result, when thin and long conduction channels like 1D are formed on the thin 2D Si thin film formed on the insulating film, polarized spin is effectively injected into the Si semiconductor, and the magnetization directions of the two magnetic bodies are antiparallel. In this case, the spin direction injected from the source and the spin direction of the drain are different, so that the spin accumulates in the Si semiconductor and the resistance increases. In parallel, the injected spin moves easily to the drain, resulting in a typical spin valve phenomenon. I could check my luggage.

FIG. 7 illustrates electron beam lithography and argon milling of the channel to define a process technique for forming a plurality of one-dimensional Si conduction channels in the SOI mesa structure mentioned in the plan view of FIG. Fig. 1 shows the device immediately after the step.

One of the most important things in the present invention is to form a one-dimensional Si conduction channel through an etching process, unlike the previous studies. The width of the channel is in the order of tens to hundreds of nanometers and the length is several microns, so It is difficult to form a channel. Therefore, instead of the photolithography process, an electron beam photosensitive process with much more precise size and position control was used. As shown in FIG. 7, the electron beam photosensitive agent maintains its original shape after the etching process. The electron beam photosensitizers widely used in the electron beam photosensitive process are PMMA series such as PMMA 495K and PMMA 950K. These are easily damaged by dry etching processes such as ar ion milling, and it is difficult to proceed with the subsequent process using PMMA as a mask. Therefore, in the present invention, ZEP520A electron beam photosensitizer was used, which has an advantage that the etching rate for ion milling is 0.9 Å / sec lower than PMMA, so that the photoresist itself can be used as an etching mask in a later process.

However, in the electron beam photosensitive process, the control of process variables is very difficult and the control of process conditions is difficult. The parameters of the electron beam photosensitive process optimized in the present invention are area dose 45 μC / cm, dose factor 1.2, acceleration voltage 25 KV, step size, 9.2 nm. After Ar Ion milling using a ZEP520A photoresist as a mask, a plurality of Si spin channels as shown in FIG. 3 can be made by filling an insulating layer in an etching place and lifting the photoresist off.

A spin transistor is illustrated in FIG. 8 as an example of the hybrid magnetic material / semiconductor device manufactured in the present invention. A magnetic material was used as the source 81 and the drain 82 of the spin transistor. Spin-polarized carriers are injected from the source 81 into the channel region 85 and again detected at the drain 82. In the channel region, a spin-polarized carrier injected into the channel region was formed by forming an one-dimensional channel on the SOI by applying an oxide insulating film 86 on the channel, and then applying a voltage to the gate by installing a gate electrode 83 thereon. Precession can be controlled. In this way, a spin-polarized field effect transistor (spin FET) is realized.

As described above, according to the present invention, a spin valve effect, which is not realized in a conventional magnetic / Si semiconductor device, is achieved, so that only a charge of a carrier is controlled by an electric field in a semiconductor transistor. By injecting and detecting the spin into the SOI semiconductor using the magnetic material, it can be applied to memory and logic devices using the spin of the carrier.

Claims (15)

An SOI substrate is formed on the insulating film, a source region of a magnetic material is formed on the SOI substrate, a spin channel region having a one-dimensional structure is formed on the SOI substrate through which the spin injected into the source region passes, and the spin channel region is formed. A hybrid magnetic material / semiconductor spin element, wherein a drain region of a magnetic material is formed on the SOI substrate on which the passed spin is detected. The hybrid magnetic material / semiconductor spin device according to claim 1, wherein the magnetic material is a magnetic metal having a large spin polarization and is made of one selected from Fe, Co, Ni, FeCo, and NiFe. The hybrid magnetic material / semiconductor spin device according to claim 1, wherein the magnetic material is made of one selected from GaMnAs, InMnAs, GeMn, GaMnN, GaMnP, and ZnMnO. The hybrid magnetic material according to claim 1, wherein the magnetic material is composed of a half metal having a spin polarization of 100% including La _(1-x) Sr _x MnO ₃ (LSMO), CrO ₂ , and the like. Spin element. The hybrid magnetic / semiconductor spin device according to claim 1, wherein the SOI substrate is composed of a Si thin film layer having a thickness of 50 to 300 nm on a SiO ₂ insulating film having a thickness of 50 to 400 nm. 2. The one-dimensional channel of claim 1, wherein the surface of the SOI substrate on either side of the channel region is etched to the lower insulating layer to form a one-dimensional conduction channel region in which the spin moves on the SOI substrate. A hybrid magnetic material / semiconductor spin element, having a channel structure, and having a channel structure between the channels and insulating with insulating films such as TaO and SiO ₂ . The method of claim 6, wherein in order to form a large number of the one-dimensional conduction channel on the SOI substrate, patterning is performed by electron beam etching using an electron beam photosensitizer, and argon ion milling using the electron beam photosensitizer as a mask. A hybrid magnetic material / semiconductor spin element, wherein an insulating film is filled therein and a photosensitive agent is removed to form a channel. The hybrid magnetic / semiconductor spin device according to claim 1, wherein the source region and the drain region are made of a magnetic material having a width in a range of 20 nm to 50 μm and a length of 100 nm to 500 μm. The hybrid magnetic material / semiconductor spin device according to claim 8, wherein a distance between the source region and the drain region is in a range of 10 nm to 5 µm. The hybrid magnetic material / semiconductor spin device according to claim 8, wherein the source region and the drain region have different line widths so that spin switching is antiparallel in a certain magnetic range. 9. The method of claim 8, wherein the source region and the drain region are switched by a conversion bias of a semi-magnetic pinned layer / ferromagnetic free layer structure to one of the source or drain region for the purpose of spin-parallel antiparallel in a certain magnetic range when the line width and length are the same Hybrid magnetic material / semiconductor spin device, characterized in that the magnetic field range can be adjusted. The hybrid magnetic material of claim 8, wherein the source region and the drain region use one of magnetic materials having different coercive forces for the purpose of anti-parallel spin switching in a certain magnetic range when the line width and the length are the same. / Semiconductor spin device. The hybrid magnetic material / semiconductor spin device according to claim 1, wherein the contact resistance between the magnetic material and the SOI semiconductor is ohmic or schottky. The hybrid type of claim 1, wherein an insulating film, such as Al ₂ O ₃ or SiO ₂ , is inserted between the magnetic material and the SOI semiconductor to a thickness in a range of 0.5 to 2 nm to improve spin injection efficiency by tunneling. Magnetic / Semiconductor Spin Device. Forming a gate; Forming an insulating layer under the gate; Forming a source region and a drain region by using magnetic materials on left and right sides of the insulating layer; Forming a SOI layer under the insulating layer as a spin transfer channel layer; And controlling the precession of the spin-polarized carriers by the voltage applied to the gate.

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