KR101013791B1 - Non-volatile semiconductor memory device and method of manufacturing thereof - Google Patents

Abstract

The present invention relates to a nonvolatile semiconductor memory device and a method of manufacturing the same.

The nonvolatile semiconductor memory device according to the present invention includes a substrate, a semiconductor pillar formed on the substrate, a hard mask formed on the semiconductor pillar, a gate electrode formed on both sides of the semiconductor pillar, and a direction different from the direction in which the gate electrode is formed, In addition, on the resistance change material layer and the resistance change material layer, which are formed to surround the source electrode, the drain electrode, and the hard mask formed on both sides of the semiconductor pillar, and the resistance change material is changed according to an electrical signal. It includes a metal layer formed.

The nonvolatile semiconductor memory device according to the present invention can be operated at high speed when power is supplied, and data can be stored and continuously maintained using a resistance change material even when the power supply is stopped.

DRAM, Capacitorless DRAM, Resistance Random Access Memory (RRAM), Nonvolatile Memory

Description

Nonvolatile semiconductor memory device and manufacturing method thereof {NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THEREOF}

The present invention relates to a nonvolatile semiconductor memory device and a method of manufacturing the same.

Since the semiconductor memory device has a high number of memory cells per unit area, that is, a high degree of integration, a fast operation speed, and a low power operation, many studies have been conducted. Various types of memory devices have been developed.

A typical example of the memory devices is a DRAM (Dynamic Random Access Memory, DRAM) device. In general, a DRAM has a unit cell composed of one transistor and one capacitor. DRAM has the advantage of high integration and fast operation speed. However, after the power is turned off, all the stored data is lost. In addition, when the DRAM device for high integration is scaled down, the capacitor manufacturing process is complicated, resulting in process problems as the integration of the device increases. In addition, the capacitor manufacturing process is also an obstacle to forming embedded chips with other devices.

Accordingly, various types of devices for improving the integration of DRAM devices are being studied, and one of such memory devices is a capacitorless DRAM. Capacitorless DRAMs are semiconductor memory devices that operate by dividing holes in bits by accumulating holes in a floating body without a capacitor causing a complicated process of a general DRAM device.

Briefly describing the operation of the capacitorless DRAM, first, when the voltage is applied to the gate electrode and the drain electrode of the transistor formed on the silicon-on-insulator (SOI) substrate, impact ionization phenomenon As a result, excess electron holes are generated in the channel region adjacent to the drain electrode. The generated excess holes are not escaped by the insulating layer formed below the floating body, and are collected in the floating body region having the lowest potential. Accordingly, the capacitorless DRAM shows a difference between the threshold voltage and the current level of the transistor depending on the presence of holes gathered in the floating body region, and the bit such as '0' or '1' through the difference between the threshold voltage and the current level. It operates by dividing the unit data. However, the holes in the body are discontinued due to power supply interruption and recombination over time. Accordingly, the conventional capacitorless DRAM has a problem in that stored data cannot be maintained after the power supply is interrupted.

Meanwhile, unlike the DRAM device, a flash memory is a representative example of a nonvolatile memory device in which stored data may be preserved even after power is turned off. Unlike DRAM devices, which are volatile memory devices, flash memories have nonvolatile data retention. However, flash memories have higher operating voltages and slower operating speeds than DRAM devices. In addition, in the manufacture of flash memory devices, the physical limitations of scale-down due to high integration are encountered. RRAM (Resistance Random Access Memory) is a memory device that mainly uses resistance characteristics of resistance change material depending on voltage. It is possible to operate memory without using a transistor like DRAM. It is very advantageous in terms of the degree of integration, and has the advantage that the process is very simple due to the simple structure.

Accordingly, in order to solve the above problems, the present invention provides a non-volatile semiconductor memory device capable of high-speed operation at the time of supplying power, and retaining stored data even when the power supply is interrupted by using a resistance change material. Let it be technical problem.

Another object of the present invention is to provide a nonvolatile semiconductor memory device and a manufacturing method capable of selectively performing functions as a DRAM and a nonvolatile semiconductor memory device.

The nonvolatile semiconductor memory device according to claim 1 is formed in a direction different from a direction in which a substrate, a semiconductor pillar formed on the substrate, a hard mask formed on the semiconductor pillar, gate electrodes formed on both sides of the semiconductor pillar, and a gate electrode are formed, respectively. Also, the resistance change material layer and the resistance change material layer which are formed to surround the source electrode and the drain electrode formed on both sides of the semiconductor pillar and the hard mask, and the resistance change material is changed in accordance with the electrical signal. It includes a metal layer formed on.

A nonvolatile semiconductor memory device according to claim 2 is a nonvolatile semiconductor memory device according to claim 1, further comprising a gate insulating layer formed between the gate electrode and the semiconductor pillar, wherein a predetermined region of the gate insulating layer is hard. It is covered by a mask and a layer of resistance change material.

In the nonvolatile semiconductor memory device of the invention according to claim 3, in the nonvolatile semiconductor memory device according to the invention according to claim 1, the substrate is formed of an insulating layer embedded silicon (Silicon-On-Insulator, SOI).

The nonvolatile semiconductor memory device of the invention according to claim 4 is the nonvolatile semiconductor memory device according to the invention of claim 1, wherein the hard mask includes silicon nitride (Si ₃ N ₄ ).

A nonvolatile semiconductor memory device according to claim 5 is a nonvolatile semiconductor memory device according to claim 1 or 2, wherein the resistance change material layer is formed so as to cover predetermined regions of the source electrode and the drain electrode, and includes aluminum (Al). ) Oxide, copper (Cu) oxide, nickel (Ni) oxide, titanium (Ti) oxide, hafnium (Hf) oxide, zirconium (Zr) oxide, zinc (Zn) oxide, tungsten (W) oxide, cobalt (Co) oxide And vanadium (V) oxide.

In the nonvolatile semiconductor memory device of the invention according to claim 6, in the nonvolatile semiconductor memory device according to the first invention, the width of the semiconductor pillar is formed to be larger than the maximum width of the depletion region formed in the semiconductor pillar.

The nonvolatile semiconductor memory device of the invention according to claim 7 is the nonvolatile semiconductor memory device according to the invention of claim 1, wherein the metal layer is aluminum (Al), copper (Cu), nickel (Ni), titanium (Ti), or hafnium (Hf). ), Zirconium (Zr), zinc (Zn), tungsten (W), cobalt (Co), vanadium (V), erbium (Er), platinum (Pt).

In the method for manufacturing a nonvolatile semiconductor memory device according to claim 8, the first step of forming a semiconductor pillar on a substrate, the second step of depositing a hard mask on the semiconductor pillar, the gate electrode is formed on both sides of the semiconductor pillar, respectively A third step of forming a source electrode and a drain electrode on both sides of the semiconductor pillar; And a fifth step of forming a resistance change material layer including a resistance change material, and a sixth step of forming a metal layer on the resistance change material layer.

In the method for manufacturing a nonvolatile semiconductor memory device according to claim 9, in the method for manufacturing a nonvolatile semiconductor memory device according to claim 8, the semiconductor pillar is oxidized by a thermal oxidation method, and the semiconductor pillar and gate Forming a gate insulating layer between the electrodes, wherein a predetermined region of the gate insulating layer is covered by the hard mask and the resistance change material layer.

In the method for manufacturing a nonvolatile semiconductor memory device according to claim 10, the method for manufacturing a nonvolatile semiconductor memory device according to claim 8 or 9, wherein the first step is to etch the substrate to form the semiconductor pillar, The insulating layer is formed of silicon-on-insulator (SOI).

Production method of the inventions non-volatile semiconductor memory device according to claim 11, in the inventions method of manufacturing a nonvolatile semiconductor memory device according to claim 8, and a hard mask keuneun silicon nitride (Si ₃ N _4).

The method of manufacturing a nonvolatile semiconductor memory device according to claim 12 is the method of manufacturing a nonvolatile semiconductor memory device according to claim 8 or 9, wherein the third step includes depositing a gate electrode material on a substrate and a hard mask. A first process includes a second process of planarizing the gate electrode material using a chemical mechanical polishing method, and a third process of patterning the planarized gate electrode material to form respective gate electrodes.

The method for manufacturing a nonvolatile semiconductor memory device according to claim 13 is the method for manufacturing a nonvolatile semiconductor memory device according to claim 8 or 9, wherein the resistance change material layer covers a predetermined region of the source electrode and the drain electrode. Aluminum oxide, copper (Cu) oxide, nickel (Ni) oxide, titanium (Ti) oxide, hafnium (Hf) oxide, zirconium (Zr) oxide, zinc (Zn) oxide, tungsten (W) oxide , At least one of cobalt (Co) oxide and vanadium (V) oxide.

In the method for manufacturing a nonvolatile semiconductor memory device according to claim 14, in the method for manufacturing a nonvolatile semiconductor memory device according to claim 8, the width of the semiconductor pillar is formed to be larger than the maximum width of the depletion region formed in the semiconductor pillar. .

In the method for manufacturing a nonvolatile semiconductor memory device according to claim 15, the method for manufacturing a nonvolatile semiconductor memory device according to claim 8, wherein the metal layer is aluminum (Al), copper (Cu), nickel (Ni), titanium ( Ti, hafnium (Hf), zirconium (Zr), zinc (Zn), tungsten (W), cobalt (Co), vanadium (V), erbium (Er), platinum (Pt).

The nonvolatile semiconductor memory device according to claim 16 includes a substrate, a floating body formed on the substrate, a source electrode and a drain electrode formed on both sides of the floating body, a gate insulating layer sequentially formed on the floating body, and And a resistance change material layer formed on the gate electrode, the source electrode, and the drain electrode, and formed on the gate electrode and including a resistance change material whose resistance value changes according to an electrical signal, and a metal layer formed on the resistance change material layer.

A nonvolatile semiconductor memory device of the invention according to claim 17 is a nonvolatile semiconductor memory device according to the invention of claim 16, wherein the substrate is formed of an insulating layer buried silicon (SOI).

The nonvolatile semiconductor memory device of the invention according to claim 18 is the nonvolatile semiconductor memory device according to the invention according to claim 16, wherein the resistance change material layer includes aluminum (Al) oxide, copper (Cu) oxide, nickel (Ni) oxide, and titanium. (Ti) oxide, hafnium (Hf) oxide, zirconium (Zr) oxide, zinc (Zn) oxide, tungsten (W) oxide, cobalt (Co) oxide and vanadium (V) oxide.

A nonvolatile semiconductor memory device according to claim 19 is a nonvolatile semiconductor memory device according to claim 16, wherein the metal layer is aluminum (Al), copper (Cu), nickel (Ni), titanium (Ti), or hafnium (Hf). ), Zirconium (Zr), zinc (Zn), tungsten (W), cobalt (Co), vanadium (V), erbium (Er), platinum (Pt).

A method for manufacturing a nonvolatile semiconductor memory device according to claim 20 is a first step of forming a floating body on a substrate, a second step of forming a source electrode and a drain electrode on both sides of the floating body, and floating A third step of sequentially forming a gate insulating layer and a gate electrode on the body cell, a resistance change material including a resistance change material on the source electrode and the drain electrode, and the resistance value of the gate electrode being changed according to an electrical signal; A fourth step of forming a layer, and a fifth step of forming a metal layer on the resistance change material layer.

In the method for manufacturing a nonvolatile semiconductor memory device according to the present invention, in the method for manufacturing a nonvolatile semiconductor memory device according to the present invention according to claim 20, the substrate is formed of an insulating layer embedded silicon (Silicon-On-Insulator, SOI).

The method for manufacturing a nonvolatile semiconductor memory device according to claim 22 is the method for manufacturing a nonvolatile semiconductor memory device according to claim 20, wherein the fourth step includes a chemical vapor deposition method and a sputtering method. Alternatively, the resistive change material layer may be formed using any one of atomic layer deposition methods, and the resistive change material layer may include aluminum (Al) oxide, copper (Cu) oxide, nickel (Ni) oxide, and titanium ( Ti) oxide, hafnium (Hf) oxide, zirconium (Zr) oxide, zinc (Zn) oxide, tungsten (W) oxide, cobalt (Co) oxide and vanadium (V) oxide.

In the method for manufacturing a nonvolatile semiconductor memory device according to claim 23, the method for manufacturing a nonvolatile semiconductor memory device according to claim 20, wherein the metal layer includes aluminum (Al), copper (Cu), nickel (Ni), titanium ( Ti, hafnium (Hf), zirconium (Zr), zinc (Zn), tungsten (W), cobalt (Co), vanadium (V), erbium (Er), platinum (Pt).

As described above, according to the nonvolatile memory device according to the present invention, by using the resistance change material, high-speed operation is possible at the time of power supply, and the stored data can be continuously maintained even if the power supply is stopped.

In addition, functions as DRAMs and nonvolatile semiconductor memory devices can be selectively performed.

Specific matters other than the problem to be solved, the problem solving means, and the effects of the present invention as described above are included in the following embodiments and the drawings. Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. Like reference numerals refer to like elements throughout.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the accompanying drawings are only described in order to more easily disclose the contents of the present invention, but the scope of the present invention is not limited to the scope of the accompanying drawings that will be readily available to those of ordinary skill in the art. You will know.

1 is a view showing a nonvolatile semiconductor memory device according to an embodiment of the present invention, Figures 2a to 2g is a view showing the nonvolatile semiconductor memory device shown in Figure 1 in the AA 'direction in the process order, 3 is a diagram illustrating an operation of a nonvolatile semiconductor memory device according to an embodiment of the present invention when a DRAM operation is performed. FIG. 4 is a diagram illustrating a nonvolatile semiconductor memory device according to an embodiment of the present invention. It is a figure for explaining the operation in the case of performing a memory operation.

As shown in FIG. 1, a nonvolatile semiconductor memory device according to an embodiment of the present disclosure may include a substrate 100, a semiconductor pillar 110 formed on the substrate 100, and a hard mask formed on the semiconductor pillar 110. 120, the gate electrode 140 formed on both sides of the semiconductor pillar 110, and the source electrode 150 and the drain formed in directions different from the direction in which the gate electrode 140 is formed, and formed on both sides of the semiconductor pillar, respectively. On the resistance change material layer 170 and the resistance change material layer 170 which are formed to surround the electrode 160 and the hard mask 120 and include a resistance change material whose resistance value is changed according to an electrical signal. The formed metal layer 180 is included. Hereinafter, the substrate 100, the semiconductor pillar 110, the hard mask 120, the gate electrode 140, the source electrode 150, and the drain constituting the nonvolatile semiconductor memory device according to an embodiment of the present invention described above. The electrode 160, the resistance change material layer 170, and the metal layer 180 will be described in detail with reference to FIGS. 2 to 4.

2A through 2G are diagrams illustrating the nonvolatile semiconductor memory device illustrated in FIG. 1 in the direction A-A 'according to a process sequence.

As shown in FIG. 2A, first, a nonvolatile semiconductor memory device according to an embodiment of the present invention uses an insulating layer embedded silicon (SOI). Here, the insulating layer buried silicon is composed of a silicon layer (not shown), an insulating layer 100 (hereinafter, referred to as a substrate) formed on the silicon layer, and a silicon layer 110 formed on the insulating layer 100. . In addition, a hard mask 120 is deposited on the silicon layer 110. In this case, the hard mask 120 preferably uses silicon nitride (Si ₃ N ₄ ) to protect the semiconductor pillar formed during the chemical mechanical polishing (CMP) process.

As shown in FIG. 2B, when the hard mask 120 and the silicon layer 110 are etched, the semiconductor pillars 110 are formed on the substrate 100. In this case, the width W1 of the semiconductor pillar 110 may be larger than the maximum width of the depletion region formed in the semiconductor pillar 110 when the device is driven. That is, the semiconductor pillar 110 has a width thicker than the maximum thickness of the depletion region. Here, the depletion region is a region generated in the region adjacent to the gate electrode 140 shown in FIG. 2 (d). When the thickness of the semiconductor pillar 110 is thinner than the maximum thickness of the depletion region, the entire semiconductor pillar 110 is formed. Is depleted, and since newly formed holes are immediately recombined and disappeared in the depleted region, the semiconductor pillar 110 preferably has a sufficient thickness to form a partial depletion region. As a result, the semiconductor pillar 110 may be partially depleted when the device is driven to accumulate holes in the center region of the semiconductor pillar having the lowest potential difference.

As shown in FIG. 2C, when the semiconductor pillar 110 is oxidized by a thermal oxidation method, the gate insulating layer 130 is formed on the side of the semiconductor pillar 110.

Then, as shown in FIG. 2 (d), a material to be used as the gate electrode 140 is deposited on the entire device, and then planarized by chemical mechanical polishing (CMP). In this case, a gate material layer (not shown) having a planarized material to be used as the gate electrode 140 is formed, and when the gate material layer is patterned using a conventional lithography method, two separate gate electrodes 140 are formed. do.

In addition, as shown in FIG. 2E, the source electrode 150 and the drain electrode 160 are formed on both sides of the semiconductor pillar 110. Here, the semiconductor pillar 110 is formed in a direction different from the direction in which the gate electrode 140 is formed. The source electrode 150 and the drain electrode 160 are not limited to the direction perpendicular to the direction in which the gate electrode 140 is formed, as shown in FIG. 2E, but may be positioned in a different direction. The source electrode 150 and the drain electrode 160 formed on both sides of the semiconductor pillar 110 may be formed through a diffusion or ion implantation process and a subsequent heat treatment process. In other words, a desired impurity (for example, boron, indium, and n-type Phosphohorus, Arsenic, etc.) is implanted into the source electrode and drain electrode region through a diffusion or ion implantation process. When the impurity is activated through subsequent heat treatment, a desired n-type or p-type region is formed. In this case, the gate electrode 140, the source electrode 150, and the drain electrode 160 may be implanted with impurities at the same concentration.

Then, as shown in Figure 2 (f), to form a resistance change material layer 170 that changes the resistance value in accordance with the electrical signal. In this case, a portion of the resistance change material layer 170 must be present on the source electrode 150 and the drain electrode 160 for the nonvolatile memory operation. Here, the resistance change material layer 170 may include aluminum (Al) oxide, copper (Cu) oxide, nickel (Ni) oxide, titanium (Ti) oxide, hafnium (Hf) oxide, zirconium (Zr) oxide, and zinc (Zn). And at least one of oxide, tungsten (W) oxide, cobalt (Co) oxide, erbium (Er) oxide, and vanadium (V) oxide. As the method for depositing the resistive change material layer 170, a chemical vapor deposition method, a sputtering method or an atomic layer deposition method is used. The resistance change material layer 170 mostly has an insulator property as a metal oxide, and has a property of changing a resistance value of a material according to a specific voltage applied thereto. That is, the resistance change material has insulation as a metal oxide, but when a specific voltage is applied, the resistance change material loses insulation and has a property of low resistance. Here, the resistance change material may continuously maintain the changed resistance value even when a specific voltage applied thereto is removed. When a specific voltage is applied again, the lowered resistance value is changed to have original insulation.

As shown in FIG. 2 (g), the metal layer 180 is formed on the resistance change material layer 170. In this case, the region of the metal layer 180 is preferably the same as the resistance change material layer 170. The metal layer 180 may include aluminum (Al), copper (Cu), nickel (Ni), titanium (Ti), hafnium (Hf), zirconium (Zr), zinc (Zn), tungsten (W), and cobalt (Co). ), Vanadium (V), erbium (Er), and platinum (Pt).

Hereinafter, a driving method of a nonvolatile semiconductor memory device according to an embodiment of the present invention will be described with reference to FIGS. 3 and 4.

First, a driving voltage is applied to the gate electrode 140 and the drain electrode 160 when power is supplied to the nonvolatile semiconductor memory device. As shown in FIG. 3, the non-volatile semiconductor memory device has a collision ionization effect. The excess holes 190 are generated in the semiconductor pillar 110. The generated excess holes 190 are blocked by the insulating layer 100 and have no place to exit, and collect in the semiconductor pillar center region having the lowest potential difference in the semiconductor pillar 110. Accordingly, the memory device having the accumulated holes 190 may have a difference between the memory device when the hole 190 is not present in the semiconductor pillar 110 and a threshold voltage and a current level. Accordingly, the nonvolatile semiconductor memory device may operate by dividing the data in bit units such as '0' or '1' by using the difference between the threshold voltage and the current level depending on the presence of the hole 190 in the semiconductor pillar 110. Will be.

On the other hand, when the power supply is cut off, it operates as a nonvolatile semiconductor memory element. As shown in FIG. 4, when a voltage of a specific value or more is applied to the metal layer 180, the source electrode 150, and the drain electrode 160, the resistance value of the resistance change material constituting the resistance change material layer 170 is provided. Will change. Here, the resistance value of the changed resistance change material layer 170 may be continuously maintained even if a voltage higher than a specific value applied thereto is removed. In addition, when a voltage of a specific value or more is applied again, the changed resistance value may return to the original value before applying a voltage of a specific value or more. In addition, since the resistance change occurs only in the local region, only the resistance of the resistance change material layer 170 close to the source electrode 150 and the drain change layer 170 close to the source electrode 150 is changed. do. Accordingly, the memory device stores data of 2 bits in one device such as '00', '01', '10', and '11' by using the difference in resistance value of the resistance change material layer 170. You can keep it going.

Hereinafter, a nonvolatile semiconductor memory device according to another embodiment of the present invention will be described with reference to the accompanying drawings.

5A to 5B are views for explaining a method of manufacturing a nonvolatile semiconductor memory device according to another embodiment of the present invention, and FIG. 6 illustrates a nonvolatile memory device according to another embodiment of the present invention. Is a diagram for explaining the operation during the DRAM operation and the DRAM operation.

As shown in FIG. 5A, a nonvolatile semiconductor memory device according to another embodiment of the present invention may include a conventional insulating layer embedded silicon (SOI) substrate 100 and a transistor formed on the substrate 100. 110 and 130 to 160, and a resistance change material layer 170 deposited on the transistors 110 and 130 to 160. Here, the resistance change material layer 170 may include aluminum (Al) oxide, copper (Cu) oxide, nickel (Ni) oxide, titanium (Ti) oxide, hafnium (Hf) oxide, zirconium (Zr) oxide, and zinc (Zn). And at least one of oxide, tungsten (W) oxide, cobalt (Co) oxide, erbium (Er) oxide, and vanadium (V) oxide. As the method for depositing the resistive change material layer 170, a chemical vapor deposition method, a sputtering method or an atomic layer deposition method is used. The resistance change material layer 170 is mostly a metal oxide, not only has an insulator property, but also has a property of changing a resistance value of a material according to a specific voltage applied thereto. That is, although the resistance change material has insulation as a metal oxide, when a specific voltage is applied, the resistance change material loses insulation and has a property of low resistance. Here, the resistance change material may continuously maintain the changed resistance value even when a specific voltage applied thereto is removed. When a specific voltage is applied again, the lowered resistance value is changed to have original insulation.

Next, as shown in FIG. 5B, the metal layer 180 is formed on the resistance change material layer 170. The metal layer 180 includes aluminum (Al), copper (Cu), nickel (Ni), titanium (Ti), hafnium (Hf), zirconium (Zr), zinc (Zn), tungsten (W), cobalt (Co), It is preferable to form one of vanadium (V), erbium (Er) and platinum (Pt).

Hereinafter, a driving method of a nonvolatile semiconductor memory device according to another exemplary embodiment of the present invention will be described with reference to FIG. 6.

First, in the non-volatile semiconductor memory device, a driving voltage is applied to the gate and the drain when the power is supplied. As shown in FIG. 6, the non-volatile semiconductor memory device is exceeded in the floating body 110 toward the drain electrode 160 by the collision ionization effect. Holes 190 will be generated. Since the generated excess holes 190 are blocked by the insulating layer and are not escaped, they are collected in the center region of the semiconductor pillar having the lowest potential difference in the floating body 110. Accordingly, the memory device having the accumulated holes 190 has a difference between the memory device and the threshold voltage and the current level when there is no hole 190 in the floating body 110. Accordingly, the nonvolatile semiconductor memory device may operate by dividing the data in bit units such as '0' or '1' by using the difference between the threshold voltage and the current level depending on the presence of the hole 190 in the floating body 110. It becomes possible.

On the other hand, when the power supply is cut off, it operates as a nonvolatile semiconductor memory element. When a voltage of a specific value or more is applied to the metal layer 180, the source electrode 150, and the drain electrode 160, the resistance value of the resistance change material constituting the resistance change material layer 170 is changed. Here, the resistance value of the changed resistance change material layer 170 may be continuously maintained even if a voltage higher than a specific value applied thereto is removed. In addition, when a voltage of a specific value or more is applied again, the changed resistance value may return to the original value before applying a voltage of a specific value or more. In addition, since the resistance change is known to occur only in the local region, only the resistance of the resistance change material layer 170 close to the source electrode 150 and the resistance change material layer 170 close to the drain electrode 160 is known. Will change. Accordingly, the memory device stores data of 2 bits in one device such as '00', '01', '10', and '11' by using the difference in resistance value of the resistance change material layer 170. You can keep it going.

Therefore, when the driving voltage is applied, the nonvolatile semiconductor memory device according to the present invention not only enables high-speed operation like a DRAM but also stores or permanently stores data using the resistance change material even after the driving voltage is turned off. . In addition, it is possible to selectively perform functions as DRAM and nonvolatile memory devices.

As described above, those skilled in the art to which the present invention pertains will understand that the present invention may be implemented in other specific forms without changing the technical spirit or essential features. Therefore, the embodiments described above are to be understood in all respects as illustrative and not restrictive, and the scope of the present invention is indicated by the following claims rather than the above description, and the meaning and scope of the claims And all changes or modifications derived from the equivalent concept should be interpreted as being included in the scope of the present invention.

1 illustrates a nonvolatile semiconductor memory device according to an embodiment of the present invention.

2A to 2G are diagrams illustrating the nonvolatile semiconductor memory device shown in FIG. 1 in the A-A 'direction according to a process sequence;

3 is a diagram for describing an operation of a nonvolatile semiconductor memory device according to an embodiment of the present invention when a DRAM operation is performed.

4 is a diagram for describing an operation of a nonvolatile semiconductor memory device according to an embodiment of the present invention when the nonvolatile memory device operates.

5A to 5B are views for explaining a method of manufacturing a nonvolatile semiconductor memory device according to another embodiment of the present invention.

FIG. 6 is a diagram illustrating an operation of a nonvolatile semiconductor memory device according to another embodiment of the present invention when performing a nonvolatile memory operation and a DRAM operation. FIG.

******** Explanation of symbols for the main parts of the drawing ********

100: insulation layer

110: semiconductor pillar

120: hardmask

130: gate insulating layer

140: gate electrode

150: source electrode

160: drain electrode

170: resistance change material layer

180: metal layer

190: hole

Claims (23)

Board; A semiconductor pillar formed on the substrate; A hard mask formed on the semiconductor pillar; Gate electrodes formed on both sides of the semiconductor pillar; A source electrode and a drain electrode formed in a direction different from the direction in which the gate electrode is formed, and formed on both sides of the semiconductor pillar, respectively; A resistance change material layer formed to surround the hard mask and including a resistance change material whose resistance value changes according to an electrical signal; And A metal layer formed on the resistance change material layer; Non-volatile semiconductor memory device comprising a. The method of claim 1, And a gate insulating layer formed between the gate electrode and the semiconductor pillar, respectively. And a predetermined region of the gate insulating layer is covered by the hard mask and the resistance change material layer. The method of claim 1, The substrate is formed of an insulating layer buried silicon (Silicon-On-Insulator, SOI), non-volatile semiconductor memory device. The method of claim 1, And the hard mask comprises silicon nitride (Si ₃ N ₄ ). The method according to claim 1 or 2, The resistance change material layer, It is formed to cover a predetermined region of the source electrode and the drain electrode, Aluminum (Al) oxide, copper (Cu) oxide, nickel (Ni) oxide, titanium (Ti) oxide, hafnium (Hf) oxide, zirconium (Zr) oxide, zinc (Zn) oxide, tungsten (W) oxide, cobalt ( A nonvolatile semiconductor memory device comprising at least one of Co) oxide and vanadium (V) oxide. The method of claim 1, The width of the semiconductor pillar is formed larger than the maximum width of the depletion region formed in the semiconductor pillar. The method of claim 1, The metal layer may be aluminum (Al), copper (Cu), nickel (Ni), titanium (Ti), hafnium (Hf), zirconium (Zr), zinc (Zn), tungsten (W), cobalt (Co), vanadium ( A nonvolatile semiconductor memory device comprising any one of V), erbium (Er) and platinum (Pt). Forming a semiconductor pillar on the substrate; Depositing a hard mask on the semiconductor pillar; A third step of forming gate electrodes on both sides of the semiconductor pillar; A fourth step of forming a source electrode and a drain electrode in directions different from the direction in which the gate electrode is formed, and on both sides of the semiconductor pillar; A fifth step of forming a resistance change material layer surrounding the hard mask and including a resistance change material whose resistance value changes according to an electrical signal; And A sixth step of forming a metal layer on the resistance change material layer; A manufacturing method of a nonvolatile semiconductor memory device comprising a. The method of claim 8, Oxidizing the semiconductor pillars by a thermal oxidation method to form gate insulating layers between the semiconductor pillars and the gate electrodes, respectively. And a predetermined region of the gate insulating layer is covered by the hard mask and the resistance change material layer. 10. The method according to claim 8 or 9, The first step is to form the semiconductor pillar by etching the substrate, The substrate is formed of an insulating layer buried silicon (Silicon-On-Insulator, SOI), manufacturing method of a nonvolatile semiconductor memory device. The method of claim 8, The hard mask includes silicon nitride (Si ₃ N ₄ ), a method of manufacturing a nonvolatile semiconductor memory device. 10. The method according to claim 8 or 9, The third step, Depositing a gate electrode material on the substrate and the hard mask; A second process of planarizing the gate electrode material using a chemical mechanical polishing method; And A third process of patterning the planarized gate electrode material to form respective gate electrodes; A manufacturing method of a nonvolatile semiconductor memory device comprising a. 10. The method according to claim 8 or 9, The resistance change material layer, It is formed to cover a predetermined region of the source electrode and the drain electrode, Aluminum (Al) oxide, copper (Cu) oxide, nickel (Ni) oxide, titanium (Ti) oxide, hafnium (Hf) oxide, zirconium (Zr) oxide, zinc (Zn) oxide, tungsten (W) oxide, cobalt ( A method for manufacturing a nonvolatile semiconductor memory device, comprising at least one of Co) oxide and vanadium (V) oxide. The method of claim 8, The width of the semiconductor pillar is formed larger than the maximum width of the depletion region formed in the semiconductor pillar, manufacturing method of a nonvolatile semiconductor memory device. The method of claim 8, The metal layer may be aluminum (Al), copper (Cu), nickel (Ni), titanium (Ti), hafnium (Hf), zirconium (Zr), zinc (Zn), tungsten (W), cobalt (Co), vanadium ( V), erbium (Er) and platinum (Pt), any one of the manufacturing method of a nonvolatile semiconductor memory device. Board; A floating body cell formed on the substrate; A source electrode and a drain electrode on the substrate and formed on both sides of the floating body cell; A gate insulating layer and a gate electrode sequentially formed on the floating body cell; A resistance change material layer on the source electrode and the drain electrode and formed on the gate electrode, the resistance change material layer including a resistance change material whose resistance value changes according to an electrical signal; And A metal layer formed on the resistance change material layer; Non-volatile semiconductor memory device comprising a. The method of claim 16, The substrate is formed of an insulating layer buried silicon (Silicon-On-Insulator, SOI), non-volatile semiconductor memory device. The method of claim 16, The resistance change material layer may include aluminum (Al) oxide, copper (Cu) oxide, nickel (Ni) oxide, titanium (Ti) oxide, hafnium (Hf) oxide, zirconium (Zr) oxide, zinc (Zn) oxide, and tungsten. (W) A nonvolatile semiconductor memory device comprising at least one of oxide, cobalt (Co) oxide, and vanadium (V) oxide. The method of claim 16, The metal layer may be aluminum (Al), copper (Cu), nickel (Ni), titanium (Ti), hafnium (Hf), zirconium (Zr), zinc (Zn), tungsten (W), cobalt (Co), vanadium ( A nonvolatile semiconductor memory device comprising any one of V), erbium (Er) and platinum (Pt). Forming a floating body on the substrate; Forming a source electrode and a drain electrode on the substrate and on both sides of the floating body; A third step of sequentially forming a gate insulating layer and a gate electrode on the floating body cell; Forming a resistance change material layer on the source electrode and the drain electrode and including a resistance change material on the gate electrode, the resistance change material having a resistance value changed according to an electrical signal; And Forming a metal layer on the resistance change material layer; A manufacturing method of a nonvolatile semiconductor memory device comprising a. 21. The method of claim 20, The substrate is formed of an insulating layer buried silicon (Silicon-On-Insulator, SOI), manufacturing method of a nonvolatile semiconductor memory device. 21. The method of claim 20, In the fourth step, the resistive change material layer is formed using any one of chemical vapor deposition, sputtering, and atomic layer deposition. The resistance change material layer may include aluminum (Al) oxide, copper (Cu) oxide, nickel (Ni) oxide, titanium (Ti) oxide, hafnium (Hf) oxide, zirconium (Zr) oxide, zinc (Zn) oxide, and tungsten. (W) A method for manufacturing a nonvolatile semiconductor memory device comprising at least one of oxide, cobalt (Co) oxide, and vanadium (V) oxide. 21. The method of claim 20, The metal layer may be aluminum (Al), copper (Cu), nickel (Ni), titanium (Ti), hafnium (Hf), zirconium (Zr), zinc (Zn), tungsten (W), cobalt (Co), vanadium ( V), erbium (Er) and platinum (Pt), any one of the manufacturing method of a nonvolatile semiconductor memory device.

Images