KR20060105360A - Nonvolatile memory device using resistive material whose resistance changes depending on applied voltage as memory node and methods of manufacturing and operating the same - Google Patents

Abstract

Disclosed are a nonvolatile memory device using a memory node having a resistor whose resistance varies according to an applied voltage, and a method of manufacturing and operating the same. Non-volatile memory device of the present invention is provided with a substrate having a buffer layer on the surface, the source and drain formed on the buffer layer spaced apart, the pin channel provided between the source and drain, between the pin channel and the buffer layer And a memory node connected to the source and drain, a gate insulating layer covering the pin channel and the memory node, and a gate electrode spaced apart from the source and drain and covering the gate insulating layer. The memory node may be a transition metal oxide layer, and a spacer may be provided between the gate electrode and the source and drain.

Description

Nonvolatile memory device using resistive material whose resistance changes depending on applied voltage as memory node and methods of manufacturing and operating the same}

1 is a perspective view of a nonvolatile memory device including a fin transistor according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of FIG. 1 taken in a 2-2 'direction.

FIG. 3 is a cross-sectional view of FIG. 1 taken in the 3-3 'direction.

4 to 15 are cross-sectional views sequentially illustrating a method of manufacturing the nonvolatile memory device of FIG. 1 according to the first embodiment of the present invention.

16 to 25 are cross-sectional views sequentially illustrating a manufacturing method of a nonvolatile memory device of FIG. 1 according to a second embodiment of the present invention.

FIG. 26 is an equivalent circuit diagram of the nonvolatile memory device of FIG. 1.

FIG. 27 is an equivalent circuit diagram of a logic device NAND including the nonvolatile memory device of FIG. 1.

* Description of the symbols for the main parts of the drawings *

10: semiconductor substrate 12: buffer layer

14a and 14b: first and second conductive layer patterns

16a, 16b: first and second spacers

18a, 18b: first and second interlayer insulating layer patterns

20: gate electrodes 22a and 24a: first and second channel layers

26a: gate insulating films 12a and 12b: exposed regions of the buffer layer 12

14: conductive layer 18: interlayer insulating layer

16a, 16b: first and second spacers

18a, 18b: first and second interlayer insulating layer patterns

GS: Gate laminate PR, PR1, PR2, PR3: Photoresist pattern

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device of a semiconductor device, and more particularly, to a nonvolatile memory device including a pin transistor, and a method of manufacturing and operating the same.

Semiconductor memory devices can be classified into volatile memory devices and nonvolatile memory devices. A volatile memory device refers to a memory device in which all of the recorded data is erased when the power supply is cut off. Nonvolatile refers to a memory device in which the recorded data is not erased even when the power supply is cut off. Flash memory devices are typical of nonvolatile memory devices.

With the recent development of internet technology and manufacturing technology of portable communication devices, users can use more various information more easily than in the past. Accordingly, the amount of information that a user wants to store also increases naturally, and as the necessity of moving information spatially increases, the demand and interest for nonvolatile memory devices naturally increase.

Recently, various nonvolatile memory devices, such as MRAM and PRAM RRAM, have been introduced.

MRAM uses a magnetic tunnel junction (MTJ) layer as a memory node to which data is written, and PRAM uses a phase change material layer as a memory node. The RRAM uses a resistor whose resistance varies depending on the voltage applied to the memory node.

The RRAM includes the above resistor and one field effect transistor (FET).

However, as the RRAM density increases, the scale of the transistor decreases, which causes serious problems. In other words, as the scale of the transistor decreases, the source-drain current of the transistor decreases rapidly. When the source-drain current of the transistor is small, switching of the resistor can be difficult, and as a result, data writing or erasing becomes difficult.

Accordingly, an aspect of the present invention is to provide a nonvolatile memory device using a pin transistor, which is capable of increasing the degree of integration and enabling low voltage driving.

Another object of the present invention is to provide a method of manufacturing such a nonvolatile memory device.

Another object of the present invention is to provide a method of operating the nonvolatile memory device.

Another object of the present invention is to provide a logic device including the nonvolatile memory device.

In order to achieve the above technical problem, the present invention provides a substrate having a buffer layer, a source and a drain formed on the buffer layer, a fin channel provided between the source and drain, provided between the fin channel and the buffer layer and A nonvolatile memory device includes a memory node connected to a source and a drain, a gate insulating layer covering the pin channel and the memory node, and a gate electrode spaced apart from the source and drain and covering the gate insulating layer.

The memory node may be a resistor whose resistance changes according to an applied voltage, and the resistor may be a transition metal oxide layer.

A spacer may be provided between the gate electrode and the source and drain.

An interlayer insulating layer may be provided between the source and drain and the gate electrode.

In order to achieve the above technical problem, the present invention provides a first step of forming a buffer layer on a substrate, a second step of sequentially stacking a memory node layer and a channel layer on the buffer layer, the channel layer and the memory node layer Patterning sequentially to form a pin-shaped channel and a memory node, and sequentially forming a source and an interlayer insulating layer connected to one end of the pin-shaped channel and a memory node on the buffer layer, A fourth step of sequentially forming a drain and an interlayer insulating layer connected to the other end of the channel and the memory node of the first step; a fifth step of forming a gate insulating film on the exposed entire surface of the pin-shaped channel and the memory node; A first spacer is formed on a side surface of the interlayer insulating layer and connected to one end of the pin-shaped channel and a memory node, and the drain A sixth step of forming a second spacer on a side of the pin-shaped channel of the interlayer insulating layer and the other end of the memory node; and forming a gate electrode on the buffer layer to cover the gate insulating layer between the first and second spacers It provides a method of manufacturing a nonvolatile memory device comprising a seventh step.

The present invention also provides a first step of forming a buffer layer on a substrate, a second step of sequentially stacking a conductive layer and an interlayer insulating layer on the buffer layer, the interlayer insulating layer and the conductive layer in order to achieve the above another technical problem. Patterning to form a source stack comprising the conductive layer and the interlayer insulating layer on a given region of the buffer layer, and draining the conductive layer and the interlayer insulating layer on a region spaced from the stack of the buffer layer. A third step of forming a stack, a fourth step of sequentially forming a pin-shaped memory node and a channel connecting the two stacks on the buffer layer between the source stack and the drain stack, the pin shape A fifth step of forming a gate insulating film on the exposed entire surface of the memory node and the channel of the fin stack of the source stack Forming a first spacer on a side to which a second node is connected, and forming a second spacer on a side of the pin-shaped channel and a memory node of the drain stack, and forming the first spacer on the buffer layer. A seventh step of forming a gate electrode covering a gate insulating film between two spacers is provided.

In the manufacturing methods, the memory node may be a resistor whose resistance changes according to an applied voltage, and the resistor may be formed of a transition metal oxide film.

In order to achieve the above another technical problem, the present invention is a substrate having a buffer layer on the surface; A fin transistor comprising a source and a drain formed on the buffer layer, a fin channel connecting the source and drain, a gate insulating film covering the fin channel, and a gate electrode spaced apart from the source and drain and covering the gate insulating film; And a memory node provided under the pin channel and connected to the source and drain and covered with the gate insulating layer. The method of operating a nonvolatile memory device comprising: maintaining the pin transistor in an OFF state and The present invention provides a method of operating a nonvolatile memory device, wherein data is written to the memory node by applying a write voltage Vw between a source and a drain.

The present invention also provides a buffer layer on the surface in order to achieve another technical problem; A fin transistor comprising a source and a drain formed on the buffer layer, a fin channel connecting the source and drain, a gate insulating film covering the fin channel, and a gate electrode spaced apart from the source and drain and covering the gate insulating film; And a memory node disposed under the pin channel and connected to the source and drain and covered with the gate insulating layer, the method comprising: an erase voltage for erasing data written to the memory node; Is Ve, the data is read from the memory node by holding the pin transistor in an OFF state and applying a read voltage Vr lower than the erase voltage Ve between the source and drain. A method of operating a nonvolatile memory device is provided.

The present invention also provides a buffer layer on the surface in order to achieve another technical problem; A fin transistor comprising a source and a drain formed on the buffer layer, a fin channel connecting the source and drain, a gate insulating film covering the fin channel, and a gate electrode spaced apart from the source and drain and covering the gate insulating film; And a memory node disposed under the pin channel and connected to the source and drain and covered with the gate insulating layer, wherein the write voltage for writing data to the memory node is Vw. In this case, the pin transistor is maintained in an OFF state, and an erase voltage Vr higher than the write voltage Vw is applied between the source and drain to erase data written to the memory node. A method of operating a nonvolatile memory device is also provided.

In the above operating methods, a spacer may be provided between the source and drain and the gate electrode, and an interlayer insulating layer may be provided between the source and drain and the gate electrode.

The memory node may be a resistor whose resistance changes according to an applied voltage, and the resistor may be a transition metal oxide layer.

In accordance with another aspect of the present invention, there is provided a NAND logic device including at least two nonvolatile memory devices, wherein the nonvolatile memory device includes a source and a drain, and a pin channel connecting the source and drain, A fin transistor comprising a gate insulating film covering the fin channel and a gate electrode formed on the gate insulating film spaced apart from the source and the drain; And a memory node disposed under the fin channel and covered with the gate insulating layer and connected to a source and a drain.

In addition, the present invention includes at least two nonvolatile memory devices, and includes a word line and a bit line connected to an array of a plurality of these memory devices, wherein the nonvolatile memory device includes a source and a drain, and the source and drain. A pin transistor including a pin channel connecting the gate channel, a gate insulating layer covering the pin channel, and a gate electrode formed on the gate insulating layer spaced apart from the source and the drain; And a memory node provided under the pin channel and covered with the gate insulating layer and connected to a source and a drain, the method of operating a NAND logic device, the selected memory device being selected from at least two nonvolatile memory devices. The connected word line is turned off and the other word line is turned on, and a write voltage Vw is applied to a bit line connected to the selected nonvolatile memory device and 0 V is applied to the remaining bit lines. A method of operating a NAND logic device characterized in that data is written to a volatile memory device.

According to the present invention, a read voltage is applied to a bit line connected to the selected nonvolatile memory device while a word line connected to a selected memory device of the at least two nonvolatile memory devices is turned off and the other word line is turned on. The present invention also provides a method of operating a NAND logic device, characterized in that data is read from the selected nonvolatile memory device by applying (Vr) and 0V to the remaining bit lines, and the read voltage is lower than an erase voltage.

In the logic device and its operating methods, the memory node may be a resistor, and the resistor may be a transition metal oxide layer.

The nonvolatile memory device of the present invention includes a memory node under the pin channel of the pin transistor. Since the cross-sectional area of the memory node is very small, the nonvolatile memory device can increase the integration degree and lower the driving voltage compared to a memory device including a capacitor. Can be.

Hereinafter, a nonvolatile memory device (hereinafter, the memory device of the present invention) using a pin transistor according to an embodiment of the present invention and a method of manufacturing and operating the same will be described in detail with reference to the accompanying drawings. In this process, the thicknesses of layers or regions illustrated in the drawings are exaggerated for clarity.

First, the memory device of the present invention will be described.

Referring to FIG. 1, a memory device of the present invention includes a buffer layer 12 on a semiconductor substrate 10. The semiconductor substrate 10 may be a silicon substrate. The buffer layer 12 may be a silicon oxide film of a given thickness. First and second conductive layer patterns 14a and 14b exist on a given region of the buffer layer 12. The first and second conductive layer patterns 14a and 14b are spaced apart. The first and second conductive layer patterns 14a and 14b are formed at the same time in the formation process and are made of the same material. One of the first and second conductive layer patterns 14a and 14b may be used as a source and the other may be used as a drain. In the present invention, for convenience, the first conductive layer pattern 14a is regarded as a source, and the second conductive layer pattern 14b is regarded as a drain. First and second interlayer insulating layer patterns 18a and 18b exist on the first and second conductive layer patterns 14a and 14b, respectively. The first and second interlayer insulating layer patterns 18a and 18b are formed at the same time and are the same material. The gate electrode 20 is positioned between the first and second conductive layer patterns 14a and 14b. The gate electrode 20 may extend by a given width onto the first and second interlayer insulating layer patterns 18a and 18b. The gate electrode 20 is an interconnection extending in a direction perpendicular to the first and second conductive layer patterns 14a and 14b, but an extension portion is omitted for convenience of illustration. First and second spacers are provided between the gate electrode 20 and the first and second conductive layer patterns 14a and 14b, respectively. The first and second spacers 16a and 16b are made of an insulating material, for example, silicon oxide film.

Referring to FIG. 2 in which FIG. 1 is cut in the 2-2 'direction together with FIG. 1,

It can be seen that the first and second channel layers 22a and 24a are sequentially stacked on the buffer layer 12 between the first and second conductive layer patterns 14a and 14b. The surfaces exposed to the outside of the first and second channel layers 22a and 24a may be covered by the gate insulating layer 26a. The gate insulating film 26a is covered with the gate electrode 20. The first and second channel layers 22a and 24a are both fin shaped.

Referring to FIG. 3, which shows a cross-sectional view of FIG. 1 in the 3-3 'direction, one portion of the first and second channel layers 22a and 24a is covered with the first conductive layer pattern 14a and the other side. A part is covered with the second conductive layer pattern 14b. The first and second channel layers 22a and 24a serve as passages of current flowing between the first and second conductive layer patterns 14a and 14b. The first and second conductive layer patterns 14a and 14b, the second channel layer 24a, the gate insulating layer 26a, and the gate electrode constitute a fin field effect transistor (hereinafter, referred to as a fin transistor). Therefore, the second channel layer 24a serves as a channel of the pin transistor. The second channel layer 24a may be a doped silicon layer. The first channel layer 22a has a different resistance according to the magnitude of the voltage applied from the outside. When an external voltage is applied to the first channel layer 22a so that the first channel layer 22a has a specific resistance, the specific resistance is maintained until a voltage greater than the external voltage is applied to the first channel layer 22a. do. For example, a predetermined voltage is applied to the first channel layer 22a, for example, the threshold voltage Vth or higher of the pin transistor, so that the first channel layer 22a is different from that before the predetermined voltage is applied. In the case of having a resistance, the first channel layer 22a may have a different resistance than before the predetermined voltage is applied, regardless of whether power is supplied, unless a voltage greater than the predetermined voltage is applied to the first channel layer 22a. Has Therefore, after the predetermined voltage is applied to the first channel layer 22a, when the current flows by applying a voltage lower than the predetermined voltage to the first channel layer 22a, the first channel layer 22a is made to flow. The amount of current passing through is different from that before applying the predetermined voltage to the first channel layer 22a. The first channel layer 22a may be used as a memory node in which bit data is stored because of this characteristic. The first channel layer 22a may be a transition metal oxide layer, for example, a nickel oxide (NiO) layer.

Considering that FIG. 3 is a cross-sectional view of FIG. 1 taken in the 3-3 'direction, the first spacer 16a may include first and second channel layers between the gate electrode 20 and the first conductive layer pattern 14a. 22a and 22b and the gate insulating layer 26a, and the second spacer 16b is provided between the first and second channel layers 22a between the gate electrode 20 and the second conductive layer pattern 14b. And 22b and the gate insulating film 26a. The first and second spacers 16a and 16b are preferably provided at the same height as the first and second interlayer insulating layers 18a and 18b.

Next, a method of manufacturing the memory device of the present invention will be described.

First, the manufacturing method by a 1st Example is demonstrated.

Referring to FIG. 4, a buffer layer 12 is formed on a semiconductor substrate 10. The semiconductor substrate 10 may be a silicon substrate, and the buffer layer 12 may be formed of a silicon oxide film. The first channel layer 22 and the second channel layer 24 are sequentially stacked on the buffer layer 12. The first channel layer 22 is used as a data storage layer. The first channel layer 22 may be formed of a transition metal material layer whose resistance varies depending on the applied voltage, for example, a nickel oxide layer (NiO). The second channel layer 24 may be formed of a doped silicon layer. The first and second channel layers 22 and 24 are formed in fins in a subsequent process. After sequentially stacking the first and second channel layers 22 and 24, a photosensitive film pattern PR is formed on the second channel layer 24 to define a region in which the channel is to be formed. The exposed portion of the second channel layer 24 is etched using the photoresist pattern PR as an etch mask, and the exposed portion of the first channel layer 22 that is subsequently exposed is etched. The etching is performed until the buffer layer 12 is exposed. As a result of the etching, as illustrated in FIG. 5, the first and second channel layers 22 and 24 are removed around the photoresist pattern PR, and the first and second channel layers 22 and 24 are formed on the photoresist pattern. (PR) will remain only below.

After the etching, the photoresist pattern PR is removed. FIG. 6 is a plan view of the result of removing the photoresist pattern PR from FIG. 5. Referring to FIG. 6, the second channel layer pattern 24a on the buffer layer 12 can be seen.

After the first and second channel layer patterns 22a and 24a are formed, the photoresist pattern PR1 defining the regions 12a and 12b on which the source and drain are to be formed, as shown in FIG. 7, on the buffer layer 12. ). At this time, one part of the second channel layer pattern 24a is exposed to the region 12a where the source is to be formed, and the other part facing the one side is the region 12b where the drain is to be formed. It is preferable to form so as to expose). That is, the center region of the second channel layer pattern 24a is covered with the photoresist pattern PR1, and both ends thereof are exposed together with the regions 12a and 12b where the source and drain are to be formed. Since the first channel layer pattern 24a is formed under the second channel layer pattern 24a, side surfaces of both ends of the first channel layer pattern 24a are naturally exposed. This fact can be seen more clearly in FIG. 8 showing a cross section taken in the 8-8 'direction.

Referring to FIG. 8, the photoresist pattern PR1 is not formed on the entire upper surface of the second channel layer pattern 24a but is formed only on a portion of the upper surface.

Subsequently, referring to FIG. 9, the conductive layer 14 is formed on the exposed regions 12a and 12b limited to the regions where the source and drain of the photoresist pattern PR1 and the buffer layer 12 are to be formed. In this case, the conductive layer 14 is also formed on the photoresist pattern PR1, and exposed regions of the first and second channel layer patterns 22a and 24a are covered with the conductive layer 14. After the conductive layer 14 is formed, an interlayer insulating layer 18 is formed on the upper surface of the conductive layer 14.

Subsequently, the photoresist pattern PR1 is removed. In this process, the conductive layer 14 and the interlayer insulating layer 18 formed on the photoresist pattern PR1 are also removed. 10 shows the result after the photoresist pattern PR1 is removed.

Referring to FIG. 10, the first conductive layer pattern 14a remains on the exposed region 12a defined as the region where the source of the buffer layer 12 is to be formed. The second conductive layer pattern 14b remains on the exposed region 12b defined as the region where the drain of the buffer layer 12 is to be formed. In addition, one of the first and second channel layer patterns 22a and 24a is covered with the first conductive layer pattern 14a, and the other is covered with the second conductive layer pattern 14b. After the photoresist pattern PR1 is removed, the interlayer insulating layer 18a remaining on the first conductive layer pattern 14a is hereinafter referred to as a first interlayer insulating layer pattern and is left on the second conductive layer pattern 14b. The interlayer insulating layer 18b is hereinafter referred to as a second interlayer insulating layer pattern 18b.

Referring to FIG. 11 and a cross-section taken along the 11-11 ′ direction, the gate insulating layer 26a is formed on the entire exposed surface of the first and second channel layer patterns 22a and 24a in the resultant of FIG. 10. Is optionally formed. Accordingly, the entire exposed surface of the first and second channel layer patterns 22a and 24a is covered with the gate insulating layer 26a.

Next, referring to FIG. 13, a first spacer 16a covering a portion of the gate insulating layer 26a is formed on side surfaces of the first conductive layer pattern 14a and the first interlayer insulating layer pattern 18a, and the second A second spacer 16b covering a portion of the gate insulating film 26a is formed on the side surfaces of the conductive layer pattern 14b and the second interlayer insulating layer pattern 18b. The first and second spacers 16a and 16b may be formed by forming a material film constituting them to a predetermined thickness on the entire surface of the resultant of FIG. 11 and then anisotropically etching the entire surface. The first and second spacers 16a and 16b prevent contact between the gate electrode 20 and the first and second conductive layer patterns 14a and 14b formed in a subsequent process.

FIG. 14 is a cross-sectional view of FIG. 13 taken along the 14-14 ′ direction. 13 and 14, it can be seen that side surfaces of the first conductive layer pattern 14a and the first interlayer insulating layer pattern 18a are covered with the first spacers 16a.

Next, referring to FIG. 15, a gate electrode 20 covering the gate insulating layer 26a between the first and second spacers 16a and 16b is formed. The gate electrode 20 has a shape as shown in FIG. 1, which is formed in a line shape in a direction perpendicular to the second channel layer pattern 24a. In this case, the gate electrode 20 may extend onto the first and second interlayer insulating layer patterns 18a and 18b to have a given width.

Next, a manufacturing method according to a second embodiment of the present invention will be described.

Referring to FIG. 16, a buffer layer 12, for example a silicon oxide film SiO 2, is formed on a semiconductor substrate 10. The conductive layer 14 is formed on the buffer layer 12, and the interlayer insulating layer 18 is formed on the conductive layer 14. The conductive layer 14 may be formed of, for example, a doped polysilicon layer. The interlayer insulating layer 18 can be formed of, for example, a silicon oxide film having a predetermined thickness. The photoresist pattern PR2 exposing a predetermined region of the interlayer insulating layer 18 is formed on the interlayer insulating layer 18. Subsequently, the exposed region of the interlayer insulating layer 18 is etched using the photoresist pattern PR2 as an etch mask. The exposed region of the interlayer insulating layer 18 is removed by the etching, and the conductive layer 14 is exposed. In this case, the etching conditions are adjusted to the etching of the conductive layer 14, and then the buffer layer 12 is exposed. The etching is continued until As a result of this etching, a predetermined region of the buffer layer 12 is exposed as shown in FIG. 17. In addition, the etching forms a first conductive layer pattern 14a and a second conductive layer pattern 14b facing each other with the exposed region of the buffer layer 12 interposed therebetween, and the first and second interlayer insulation layers. Layer patterns 18a and 18b are formed. One of the first conductive layer pattern 14a and the second conductive layer pattern 14b is used as a source and the other is used as a drain. For convenience, the first conductive layer pattern 14a is referred to as a source and the second conductive layer pattern 14b is referred to as a drain for convenience. After the etching, a post-etching process such as a cleaning and drying process is performed to keep the surface of the exposed area of the buffer layer 12 clean. Thereafter, the photoresist pattern PR2 is removed.

18 is a plan view of the resultant from which the photosensitive film pattern PR2 is removed. Referring to FIG. 18, it can be seen that the first and second conductive layer patterns 18a and 18b are rectangular and spaced apart by a given interval. In a subsequent process, a channel layer is formed on the buffer layer 12 between the first and second conductive layer patterns 18a and 18b.

To form the channel layer, as illustrated in FIG. 19, a photoresist pattern PR3 covering the first and second conductive layer patterns 14a and 14b is formed on the buffer layer 12. In this case, the photoresist pattern PR3 includes a hole h in a line shape exposing a portion of the buffer layer 12 between the first and second conductive layer patterns 14a and 14b. The hole h in a line shape defines a region in which the channel layer is to be formed in the buffer layer 12 between the first and second conductive layer patterns 14a and 14b. 20 is a cross-sectional view of FIG. 19 taken in a 20-20 'direction.

Next, using the photoresist pattern PR3 as an etch mask, the first and second channel layers are exposed on the region exposed through the hole h formed in the photoresist pattern PR3 of the buffer layer 12 as shown in FIG. 13. The patterns 22a and 22b are sequentially stacked. The first and second channel layer patterns 22a and 24a may be formed of the same material layer as in the first embodiment. Then, the photoresist pattern PR3 is ashed and stripped. The first and second channel layer patterns 22a and 24a are also formed on the photoresist pattern PR3, which is removed together with the photoresist pattern PR3 in the process of removing the photoresist pattern PR3. As a result, as illustrated in FIG. 22, first and second channel layer patterns sequentially stacked are connected to one of the first conductive layer patterns 14a and the other to the second conductive layer patterns 14b. 22a and 24a are formed on the buffer layer 12 between the first and second conductive layer patterns 14a and 14b. FIG. 23 is a cross-sectional view of FIG. 22 taken in a 23-23 'direction. Referring to FIG. 23, it can be seen that the first and second channel layer patterns 22a and 24a are formed in a fin shape.

Next, after the first and second channel layer patterns 22a and 24a are formed, as shown in FIG. 24, the gate insulation layer may be completely wrapped around the first and second channel layer patterns 22a and 24a. 26a).

Thus, as shown in FIG. 25, the first and second channel layer patterns 22a and 24a and the gate insulating layer 26a are disposed on the buffer layer 12 between the first and second conductive layer patterns 14a and 14b. A gate stack GS is formed. Referring to FIG. 25, a first spacer 16a is formed on side surfaces of the first conductive layer pattern 14a and the first interlayer insulating layer pattern 18a that are in contact with one end of the gate stack GS. The portion close to the first conductive layer pattern 14a of the gate stack GS is covered by the first spacer 16a. A second spacer 16b is formed on side surfaces of the second conductive layer pattern 14b and the second interlayer insulating layer pattern 18b which are in contact with the other end of the gate stack GS together with the first spacer 16a. The portion close to the second conductive layer pattern 14b of the gate stack GS is covered by the second spacer 16b. Subsequent processes follow the manufacturing method according to the first embodiment described above.

Next, a method of operating a memory device according to an exemplary embodiment of the present invention will be described with reference to FIG. 26.

FIG. 26 shows an equivalent circuit of the memory device of the present invention shown in FIG. In FIG. 26, reference numeral 50 denotes a variable resistor and indicates the first channel layer 22a formed of the transition metal oxide film of FIG. 1. In addition, reference numeral 60 denotes a switching element, the pin transistor including a second channel layer 24a of FIG. 1, a first conductive layer pattern 14a used as a source, and a second conductive layer pattern 14b used as a drain. Indicates.

<Write>

The switching element 60 is turned off. In this state, a write voltage Vw is applied between the source and the drain. The write voltage Vw may be higher than the operation start voltage of the switching element 60, that is, the threshold voltage Vth. Since the switching device 60 is in the off state, the source-drain current Id according to the application of the write voltage Vw does not flow through the switching device 60. Instead, the source-drain current Id flows through the variable resistor 50. The resistance of the predetermined portion of the variable resistor 50 is changed by the source-drain current Id. As a result, after the write voltage Vw is applied, the resistance of the variable resistor 50 is different from that before the write voltage Vw is applied. Therefore, when the same potential difference is maintained across the variable resistor 50 before and after the write voltage Vw is applied, the amount of current passing through the variable resistor 50 is different.

As such, when the write voltage Vw is applied and the resistance of the variable resistor 50 is different from that before the write voltage Vw is applied, it is assumed that bit data, for example, 1 is written in the memory device of the present invention. In other cases, other bit data, for example, zero, may be regarded as recorded.

<Read>

The switching element 60 is kept OFF. In this state, a read voltage Vr is applied between the source and the drain. In order to maintain the nonvolatile characteristics of the memory device of the present invention, it is preferable that the read voltage Vr is lower than the erase voltage at which the bit data written to the variable resistor 50 can be erased. Since the switching element 60 is in an off state, the read voltage Vr applied between the source and the drain is applied to the variable resistor 50. Therefore, a current due to the read voltage Vr flows through the variable resistor 50. Since the magnitude of this current will vary depending on the bit data written in the variable resistor 50, that is, the resistance of the variable resistor 50, the current is measured, and then the bit written in the memory element of the present invention in comparison with the reference current. Determine what the data is.

<Erase>

The switching element 60 is kept off. In this state, an erase voltage (not shown) is applied between the source and the drain. The erase voltage may be greater than the write voltage Vw. Due to the application of the erase voltage, the resistance state of the variable resistor 50 is in the same state as before the write voltage Vw is applied. Soon, the bit data recorded in the variable resistor 50 is erased.

Next, an operation of a logic device NAND including a plurality of memory devices of the present invention will be described with reference to FIG. 27.

In FIG. 27, reference numerals W1 to W3 denote first to third word lines, and B1 and B2 denote first and second bit lines. 27 illustrates only two rows and three columns of memory device arrays, three word lines, and two bit lines, but there may be more memory device arrays, word lines, and bit lines.

The operation of the logic device of FIG. 27 includes writing data to the selected memory device M1, reading data written to the selected memory device M1, or erasing data written to the selected memory device M1. do. Therefore, the description of the operation of the logic device of FIG. 27 replaces the above three processes.

<Process of Writing Data to Selected Memory Element M1>

Voltages greater than or equal to the threshold voltage Vth of the switching element 60 are applied to the first and third word lines W1 and W3, and the second word line W2 is turned off. The first bit line B1 is turned off, and a predetermined write voltage Vw is applied to the second bit line B2. Accordingly, although the switching elements included in the memory element arrays of the first and third columns are all on, the first bit line B1 is off, so that no current flows in the memory element arrays of the first row. However, since a predetermined write voltage Vw is applied to the second bit line B2, current due to the write voltage Vw flows through the memory element array of the second row. At this time, since the selected memory element M1 is included in the memory array of two columns, the switching element 60 of the selected memory element M1 is turned off. Therefore, the current due to the write voltage Vw flows through the switching element except for the memory element M1 selected from the memory elements forming the two-row memory element array, but the selected memory element M1 Flows through the variable resistor 50 because the switching element 60 is in an off state. The resistance of the variable resistor 50 of the selected memory element M1 is changed by this current. The changed resistance value of the variable resistor 50 according to the passage of the current is maintained until the erase voltage is applied to the second bit line B2 regardless of whether the power to the logic device of FIG. 18 is cut off.

As described above, when the resistance value of the variable resistor 50 of the selected memory element M1 is changed by the current resulting from the write voltage Vw applied to the second bit line B2, the selected memory element ( A date, e.g., 1, is recorded in M1).

<Process of Reading the Data Written to the Selected Memory Element M1>

When predetermined data, for example, 1, is written in the memory element M1 selected by the writing process, data written in the selected memory element M1 is read in a manner similar to that of the memory element of FIG. 17. Can be.

Specifically, applying a voltage equal to or greater than the threshold voltage Vth of the switching device 60 to the first and third word lines W1 and W3, and configuring a two-column memory device array including the selected memory device M1. The second word line W2 commonly connected to the switching elements of the memory devices is turned off. The first bit line B1 is turned off and a predetermined read voltage Vr lower than the write voltage Vw is applied to the second bit line B2. Since the switching device 60 of the selected memory device M1 is connected to the second word line W2 in the off state, the switching device 60 is also in the off state. Therefore, the current resulting from the predetermined read voltage Vr flows along the same path as the write current Iw. However, since the predetermined read voltage Vr is lower than the write voltage Vw, even if a current due to the read voltage Vr flows along the same path as the write current Iw, the selected memory element M1 is not affected. The recorded data is not changed or lost. The resistance of the variable resistor 50 of the selected memory element M1 before the write current Iw passes and the variable resistor 50 after the write current Iw passes, that is, the variable resistor 50 on which data is written. ) Resistance is different. Therefore, the amount of the read current passing through the variable resistor 50 varies depending on the state of the variable resistor 50. Therefore, by measuring the read current after passing through the variable resistor 50 and comparing the measurement result with the reference current through the comparator, it is possible to determine what data is written in the selected memory element M1.

<Erasing Data Written in the Selected Memory Element M1>

The states of the first to third word lines W1-W3 and the states of the first bit line B1 are maintained the same as the process of writing data in the selected memory device M1. In addition, an erase voltage Ve that is greater than the write voltage Vw is applied to the second bit line B2. Accordingly, data written to the selected memory element M1 is erased, and the variable resistor 50 is in the same state as before the write voltage Vw was applied.

While many details are set forth in the foregoing description, they should be construed as illustrative of preferred embodiments, rather than to limit the scope of the invention. For example, one of ordinary skill in the art may include a memory node made of a transition metal oxide layer under a fin channel of a fin transistor having another structure. In addition, the technical idea of the present invention may also be applied to a bottom fin transistor having a gate electrode disposed below. In other words, the gate electrode may be below the second channel layer, and the first channel layer of the transition metal oxide layer may be positioned above the second channel layer. Therefore, the scope of the present invention should not be defined by the described embodiments, but should be determined by the technical spirit described in the claims.

As described above, the memory device of the present invention has a resistor under the pin channel as a memory node, the resistance of which changes depending on the voltage, thereby lowering the operating voltage. In addition, since the resistor is provided below the fin channel layer in the same size as the fin channel of the fin transistor, the area occupied by the resistor in the memory device of the present invention is very small. Therefore, by using the present invention, it is possible to increase the degree of integration of a memory device than when using a capacitor as a memory node.

Claims (32)

A substrate having a buffer layer on its surface; Sources and drains spaced apart from each other on the buffer layer; A fin channel provided between the source and the drain; A memory node provided between the pin channel and the buffer layer and connected to the source and drain; A gate insulating layer covering the fin channel and the memory node; And And a gate electrode spaced apart from the source and drain and covering the gate insulating layer. The nonvolatile memory device of claim 1, wherein the memory node is a resistor whose resistance changes according to an applied voltage. 3. The nonvolatile memory device of claim 2, wherein the resistor is a transition metal oxide film. The nonvolatile memory device of claim 1, wherein a spacer is disposed between the gate electrode and the source and the drain. The nonvolatile memory device of claim 4, wherein an interlayer insulating layer is disposed between the source and drain and the gate electrode. Forming a buffer layer on the substrate; Sequentially stacking a memory node layer and a channel layer on the buffer layer; A third step of sequentially patterning the channel layer and the memory node layer to form a pin-shaped channel and a memory node; Source and interlayer insulating layers connected to one end of the pin-shaped channel and memory node are sequentially formed on the buffer layer, and drain and interlayer insulating layers sequentially connected to the other ends of the pin-shaped channel and memory node are sequentially formed. A fourth step of making; A fifth step of forming a gate insulating layer on the exposed entire surface of the fin-shaped channel and the memory node; A first spacer is formed on a side surface of the source and interlayer insulating layers connected to one end of the pin-shaped channel and a memory node, and a side surface connected to the other end of the pin-shaped channel and memory nodes of the drain and interlayer insulating layer Forming a second spacer in the sixth step; And And forming a gate electrode on the buffer layer to cover the gate insulating layer between the first and second spacers. The method of claim 6, wherein the memory node layer is a resistor whose resistance changes according to an applied voltage. 10. The method of claim 7, wherein the resistor is formed of a transition metal oxide film. Forming a buffer layer on the substrate; A second step of sequentially laminating a conductive layer and an interlayer insulating layer on the buffer layer; Patterning the interlayer insulating layer and the conductive layer to form a source stack comprising the conductive layer and the interlayer insulating layer on a given region of the buffer layer, and forming the source layer on a region spaced from the stack of the buffer layer. A third step of forming a drain stack including an interlayer insulating layer; A fourth step of sequentially forming a pin-shaped memory node and a channel connecting the two stacks on the buffer layer between the source stack and the drain stack; Forming a gate insulating layer on the entire exposed surface of the fin-type memory node and channel; A sixth spacer forming a first spacer on a side where the fin-shaped channel and a memory node are connected to the source stack and a second spacer on a side where the pin-shaped channel and a memory node of the drain stack are connected; step; And And forming a gate electrode on the buffer layer to cover the gate insulating layer between the first and second spacers. 10. The method of claim 9, wherein the memory node is a resistor whose resistance changes according to an applied voltage. 11. The method of claim 10, wherein the resistor is formed of a transition metal oxide film. A substrate having a buffer layer on its surface; A fin transistor comprising a source and a drain formed on the buffer layer, a fin channel connecting the source and drain, a gate insulating film covering the fin channel, and a gate electrode spaced apart from the source and drain and covering the gate insulating film; And A memory node provided under the pin channel and connected to the source and drain and covered with the gate insulating layer, the method of operating a nonvolatile memory device comprising:  And holding the pin transistor in an off state and applying a write voltage (Vw) between the source and the drain to write data to the memory node. 13. The method of claim 12, wherein a spacer is provided between the source and drain and the gate electrode, and an interlayer insulating layer is provided between the source and drain and the gate electrode. The method of claim 12, wherein the memory node is a resistor whose resistance changes according to an applied voltage. 15. The method of claim 14, wherein the resistor is a transition metal oxide film. A substrate having a buffer layer on its surface; A fin transistor comprising a source and a drain formed on the buffer layer, a fin channel connecting the source and drain, a gate insulating film covering the fin channel, and a gate electrode spaced apart from the source and drain and covering the gate insulating film; And A memory node provided under the pin channel and connected to the source and drain and covered with the gate insulating layer, the method of operating a nonvolatile memory device comprising:  When the erase voltage for erasing data written to the memory node is Ve, the pin transistor is kept OFF and a read voltage Vr lower than the erase voltage Ve between the source and drain. And applying data to read data from the memory node. 17. The method of claim 16, wherein a spacer is provided between the source and drain and the gate electrode, and an interlayer insulating layer is provided between the source and drain and the gate electrode. 17. The method of claim 16, wherein the memory node is a resistor whose resistance changes according to an applied voltage. 19. The method of claim 18, wherein the resistor is a transition metal oxide film. A substrate having a buffer layer on its surface; A fin transistor comprising a source and a drain formed on the buffer layer, a fin channel connecting the source and drain, a gate insulating film covering the fin channel, and a gate electrode spaced apart from the source and drain and covering the gate insulating film; And In the method of operating a nonvolatile memory device comprising a; memory node provided below the pin channel and connected to the source and drain and covered with the gate insulating film,  When the write voltage for writing data to the memory node is referred to as Vw, the pin transistor is kept OFF and an erase voltage Vr higher than the write voltage Vw is applied between the source and drain. And erasing data written to the memory node. 21. The method of claim 20, wherein a spacer is provided between the source and drain and the gate electrode, and an interlayer insulating layer is provided between the source and drain and the gate electrode. 21. The method of claim 20, wherein the memory node is a resistor whose resistance changes according to an applied voltage. 23. The method of claim 22, wherein the resistor is a transition metal oxide film. A NAND logic device comprising at least two nonvolatile memory devices, The nonvolatile memory device, A fin transistor comprising a source and a drain, a fin channel connecting the source and a drain, a gate insulating film covering the fin channel, and a gate electrode formed on the gate insulating film spaced apart from the source and drain; And And a memory node disposed under the fin channel and covered with the gate insulating layer and connected to a source and a drain. 25. The NAND logic element of claim 24 wherein the memory node is a resistor. 27. The NAND logic device of claim 25, wherein the resistor is a transition metal oxide film. A word line and a bit line comprising at least two nonvolatile memory elements and connected to an array of a plurality of these memory elements, The nonvolatile memory device may include one fin transistor including a source and a drain, a fin channel connecting the source and a drain, a gate insulating layer covering the fin channel, and a gate electrode formed on the gate insulating layer spaced apart from the source and drain. ; And 1. A method of operating a NAND logic device comprising: a memory node provided under the fin channel and covered with the gate insulating layer and connected to a source and a drain. The write voltage Vw is applied to the bit line connected to the selected nonvolatile memory device while the word line connected to the selected memory device of the at least two nonvolatile memory devices is turned off and the other word line is turned on. And applying 0V to the remaining bit lines to write data to the selected nonvolatile memory device. 28. The method of claim 27 wherein the memory node is a resistor. 29. The method of claim 28, wherein said resistor is a transition metal oxide film. A word line and a bit line comprising at least two nonvolatile memory elements and connected to an array of a plurality of these memory elements, The nonvolatile memory device may include one fin transistor including a source and a drain, a fin channel connecting the source and a drain, a gate insulating layer covering the fin channel, and a gate electrode formed on the gate insulating layer spaced apart from the source and drain. ; And 1. A method of operating a NAND logic device comprising: a memory node provided under the fin channel and covered with the gate insulating layer and connected to a source and a drain. Among the at least two nonvolatile memory devices, a read voltage Vr is applied to a bit line connected to the selected nonvolatile memory device while the word line connected to the selected memory device is turned off and the other word line is turned on. And applying 0V to the remaining bit lines to read data from the selected nonvolatile memory device, wherein the read voltage is lower than the erase voltage. 31. The method of claim 30 wherein the memory node is a resistor. 32. The method of claim 31 wherein the resistor is a transition metal oxide film.

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