KR100997906B1 - Unified random access memory device, manufacturing method and operating method of unified random access memory device - Google Patents

Abstract

The present invention relates to a fusion memory device, a manufacturing method and an operation method of the fusion memory device.

According to the present invention, a fusion memory device includes a semiconductor substrate, a hole encapsulation layer formed on a semiconductor substrate, a floating body layer formed on a predetermined region of a hole encapsulation layer, a gate insulating layer formed on a floating body layer, and a gate insulating layer. The first gate is formed, the resistance change material layer formed on the first gate, the second gate formed on the resistance change material layer, and the hole encapsulation layer are disposed on both sides of the floating body and include a source and a drain formed on each side.

Non-Volatile Memory, Capacitorless DRAM, Resistance Random Access Memory (RRAM), Unified Random Access Memory (URAM)

Description

METHOD AND MANUFACTURING METHOD AND MANUFACTURING METHOD OF FUSIONED MEMORY DEVICE AND FUSIONED METHOD {UNIFIED RANDOM ACCESS MEMORY DEVICE, MANUFACTURING METHOD AND OPERATING METHOD OF UNIFIED RANDOM ACCESS MEMORY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fusion memory device, a method of manufacturing and operating the fusion memory device. More specifically, a unit cell has a characteristic of a capacitorless DRAM and a randomness random access memory. A device and a method of manufacturing and operating the fused memory device.

The semiconductor memory device preferably has a high number of memory cells per unit area, that is, a high degree of integration, a high operating speed, a long charge storage duration, and a low power drive. To satisfy these conditions, various types of memory devices are developed. have.

In the case of DRAM (Dynamic Random Access Memory), a typical semiconductor memory device, a unit memory cell is generally composed of one transistor and one capacitor. DRAM has the advantage of high integration and fast operation speed. However, after the power is turned off, all the stored data is lost. In addition, the capacitor formation process is complicated when the device is scaled down for high integration, resulting in process problems as the integration of the device increases, and the capacitor formation process is also difficult to form embedded chips with other devices. Acts as.

Therefore, one of the things that are being studied as a device to overcome the disadvantages of DRAM is capacitorless DRAM (Z-RAM (ZRAM) or Zero-capacitor RAM (ZRAM) or 1T-DRAM (also called 1 Transistor DRAM). Capacitorless DRAM is a DRAM that can store data without a capacitor that causes complicated processes in the DRAM. It stores data by storing electric charges in a body.

FIG. 1A is a cross-sectional view illustrating an operation of a capacitorless DRAM according to the prior art, and FIG. 1B is a cross-sectional view schematically showing an RRAM according to the prior art.

As shown in FIG. 1A, a capacitorless DRAM according to the prior art may apply a large voltage to the gate 13 and the drain 12 in a transistor formed on an insulating layer embedded silicon (SOI) substrate. Impact ionization produces excess holes 1 in the channel on the drain 12 side. These excess holes are gathered in the body 14 with the lowest potential because there is no exit to exit because of the insulating layer 10 below the body 14. In this case, the transistors having the collected holes have a difference in the threshold voltage and the current level when there is no hole in the previous body, which distinguishes 0 and 1 by this difference.

Meanwhile, a flash memory is a representative example of a nonvolatile memory device in which stored data may be preserved even after the power is turned off. Unlike volatile memory, flash memory has nonvolatile characteristics, but has a disadvantage of high operating voltage and slow operation speed. In addition, high integration is facing the physical limitations of scale-down. Non-volatile memory devices that are currently being researched include magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase-change random access memory (PRAM), and resistance random access memory (RRAM). RRAM is a memory device whose resistance change material varies depending on the voltage. Since RRAM can operate without a transistor like a DRAM, it is very advantageous in terms of integration and its structure is simple and the process is very simple. have.

As shown in FIG. 1B, in the RRAM according to the related art, a resistance change material layer 21 is formed between the lower electrode 20 and the upper electrode 22. The lower electrode 20 and the upper electrode 22 are formed of a general conductive material, and the resistance change material layer 21 is formed of a material having resistance change characteristics. When an appropriate voltage is applied between the upper electrode 22 and the lower electrode 20, the resistance value of the resistance change material layer 21 is changed, and the difference between the resistance values of the resistance change material layer 21, that is, the resistance value is changed. 0 and 1 are distinguished by the difference between the low state (LRS-Low Resistance State) and the high resistance state (HRS-High Resistance State).

On the other hand, in recent years, most computer systems have various levels of memory that are controlled by a central processing unit (CPU) and can be used by the CPU to perform various programmed functions. Traditionally, the memory of a computer system is classified as main memory (main memory or main storage) or auxiliary memory (auxiliary storage).

Programs and data must be in main memory to be executed or referenced by the currently executing program, while programs or data that are not needed right now are held in auxiliary memory until needed and then moved to main memory for execution or reference. . This traditional memory storage hierarchy has been dramatically improved in performance and utilization since the 1960s with additional levels of expansion. This extra level, or cache, is high speed memory much faster than main memory. Because cache storage is relatively expensive compared to main memory, only a relatively small amount of cache memory is used in conventional computer systems. Cache memory typically runs 5 to 10 times faster than main memory, in some circumstances it can be close to the CPU itself. By placing the most frequently accessed instructions and / or data in fast cache memory, the average total memory access time for the system will be close to the cache's access time. Also, if a particular program instruction to be executed is preloaded into the cache, the CPU can execute program instructions without having to return to main or auxiliary memory, significantly increasing the operating speed of the system.

Cache memory may be subdivided into different categories depending on where in the computer system it is located or associated. Level 1 cache memory is typically located in the semiconductor die area where the processor is located.

Originally, additional cache memory that is not located on the same chip as the microprocessor is commonly referred to as level 2 cache memory. However, many processor designers now place Level 2 caches on the same semiconductor chip as the processor. Level 3 memory is often referred to as main memory, but some computers have level 3 memory, which is cache memory, and level 4 memory, which is main memory. In the past, caches were made mostly of static random access memory (RAM) and were mostly exclusive. These static RAMs (SRAMs) are made so that individual cells containing data bits do not have to be refreshed and have nonvolatile characteristics during power up. However, SRAM has a disadvantage of occupying a very large semiconductor substrate area. Comparable RAM is dynamic RAM (DRAM). DRAM is RAM in which data cells must be refreshed. Each cell will slowly lose its information if not refreshed. Therefore, since each cell of the DRAM array needs to be refreshed periodically, there is a disadvantage in that there is a time during which refresh cannot occur to be written or read in a specific cell or group of cells, but the semiconductor substrate area is smaller than that of SRAM. It can store more data than SRAM in the same area. Thus, some designers have been using DRAM for L2 cache recently because a large number of data bits can be located in a small DRAM area.

For example, "Method and Structure for Implementing a Cache Memory Using a DRAM Array," US Patent No. 5,829,026 by Leung et al., Has a DRAM cache that can turn a chip containing a processor on and off. Has been disclosed. In addition, U.S. Patent No. 5,895,487 to Boyd, et al., "Integrated Processing and L2 DRAM cache," discloses an L2 DRAM cache located on the same semiconductor chip as the processor. However, since the process required to manufacture DRAM is not compatible with the process of processor and SRAM, it is very difficult to implement the current DRAM in the CPU as it is. Therefore, research on the development of new embedded DRAM (EDRAM) is underway, and one of them is a capacitorless DRAM. In order to improve the performance of the current CPU, the capacity of the cache memory is increasing. Therefore, most of the CPU area is occupied by SRAM rather than the processor.

In order to solve this problem, DRAM may be used instead of SRAM, but as described above, there is a process difficulty due to the structural difference due to the presence of a capacitor. In addition, since DRAM is volatile memory, a periodic refresh process is required.

According to the present invention, by designing a fusion memory device in which a unit cell has both characteristics of a capacitorless DRAM and a resistance random access memory (RRAM), the same or similar fine line density technology may be used. It is an object of the present invention to provide a fusion memory device capable of two operations in a unit cell, a manufacturing method and an operation method of the fusion memory device.

The present invention also provides a method of manufacturing a fused memory device and a fused memory device that can maintain data stored as an RRAM device for a long time even when the power supply is interrupted, and that can operate at a high speed such as a DRAM or a capacitorless DRAM at the time of power supply. And to provide a method of operation.

In addition, an object of the present invention is to provide a fusion memory device, a manufacturing method and an operation method of the fusion memory device which can realize a high degree of integration because they do not include a capacitor.

The fusion memory device according to claim 1 includes a semiconductor substrate, a hole encapsulation layer formed on the semiconductor substrate, a floating body layer formed on a predetermined region of the hole encapsulation layer, a gate insulating layer formed on the floating body layer, and a gate insulating layer. And a source and a drain formed on the first gate, the resistance change material layer formed on the first gate, the second gate formed on the resistance change material layer, and the hole encapsulation layer, and spaced apart from each other on both sides of the floating body.

The fusion memory device of the invention according to claim 2 is the fusion memory device of the invention according to claim 1, wherein the hole surrounding layer comprises an insulating material.

The fusion memory device of the invention according to claim 3 is the fusion memory device of the invention according to claim 1, wherein the hole surrounding layer forms a hole barrier or a hole well to surround the holes.

The fusion memory device of the invention according to claim 4 is the fusion memory device according to any one of claims 1 to 3, wherein the hole surrounding layer is an impurity mixed layer in which P-type or N-type impurities are injected into a semiconductor substrate.

The fusion memory device of the invention according to claim 5 is the fusion memory device according to the invention according to claim 4, wherein the impurity mixed layer is a layer in which germanium (Ge) or carbon (C) is injected into a semiconductor substrate.

In the fusion memory device of the invention according to claim 6, in the fusion memory device according to the invention according to claim 1, the thickness of the floating body layer is formed thicker than the maximum depletion width of the channel of the fusion memory device.

The fusion memory device of the invention according to claim 7 is the fusion memory device according to the invention according to claim 1, wherein the resistive change material layer includes nickel (Ni) oxide, titanium (Ti) oxide, hafnium (Hf) oxide, and zirconium (Zr) oxide. And at least one of zinc (Zn) oxide, tungsten (W) oxide, cobalt (Co) oxide, vanadium (V) oxide, copper (Cu) oxide, and aluminum (Al) oxide.

The fusion memory element of the invention according to claim 8 is the fusion memory element of the invention according to claim 1 or 7, wherein the resistance change material layer has electrical conductivity when a voltage equal to or higher than a threshold voltage is applied.

A fused memory device according to claim 9 is a fused memory device according to claim 1, wherein the fused memory device is connected to a plurality of word lines and a plurality of bit lines to form a memory cell array, and a first gate. Is connected to any one of the plurality of word lines, and the second gate and the drain are connected to any one of the plurality of bit lines.

A method for manufacturing a fused memory device according to claim 10, comprising: a first step of sequentially forming a hole encapsulation layer, a floating body layer, a gate insulating layer, and a first gate on a semiconductor substrate, both sides of the gate insulating layer and the first gate; A second step of etching a predetermined region of the third step of forming a source and a drain on the hole encapsulation layer and spaced apart from each other on both sides of the floating body, and then the resistive change material layer and the second gate on the first gate Forming a fourth step.

The fusion memory device of the present invention according to claim 11 constitutes a memory cell array in which unit cells are arranged in a matrix of a plurality of rows and a plurality of columns, and an excess carrier is applied by a first voltage applied to any one of the unit cells. A carrier having a variable resistance characteristic by a second voltage applied to one unit cell and a first memory unit for generating and storing a carrier and storing data using a change in a predetermined threshold voltage and current. And a second memory unit for storing data using the resistance change characteristic of the memory device. The write and erase operations of the first memory unit include a resistance change characteristic of the second memory unit due to the first voltage smaller than the magnitude of the second voltage. It does not occur and generates and adjusts the excess holes in the first memory unit.

A method of operating a fusion memory device according to claim 12 is a method of operating a fusion memory device operating the fusion memory device according to claim 11, wherein any one of a plurality of word lines and one of a plurality of bit lines Selecting the unit cell of the control unit, controlling the excess hole generation operation of the first memory unit by adjusting a first voltage applied between the word line and the bit line connected to the selected unit cell, and the word line and bit connected to the selected unit cell Controlling a resistance change characteristic of the resistance change material layer of the second memory unit by adjusting a second voltage applied between the lines, wherein writing and erasing operations of the first memory unit are smaller than the magnitude of the second voltage. The resistance change characteristic of the second memory unit does not occur due to the first voltage, and excess holes are generated and adjusted in the first memory unit.

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A fusion memory device, a method of manufacturing and operating the fusion memory device according to the present invention is to design a fusion memory device such that the unit cell has both characteristics of a capacitorless DRAM (Resistance Random Access Memory) and a capacitorless DRAM (RRAM) Thus, two operations are possible in one unit cell while using the same or similar fine line density technology.

In addition, according to the present invention, even if the power supply is interrupted, the data stored together with the RRAM device can be maintained for a long time, and the power supply can operate at a high speed such as a DRAM or a capacitorless DRAM.

Further, according to the present invention, since no capacitor is included, high integration can be realized.

Specific matters other than the problem to be solved, the problem solving means, and the effects of the present invention as described above are included in the following embodiments and the drawings. Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. Like reference numerals refer to like elements throughout.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the accompanying drawings are only described in order to more easily disclose the contents of the present invention, but the scope of the present invention is not limited to the scope of the accompanying drawings that will be readily available to those of ordinary skill in the art. You will know.

2 is a cross-sectional view illustrating a structure of a fusion memory device according to an embodiment of the present invention, and FIGS. 3A and 3D are diagrams for explaining an energy band diagram of a fusion memory device according to an embodiment of the present invention.

As shown in FIG. 2, a fusion memory (URAM) device according to an embodiment of the present invention may include a substrate 100, a hole encapsulation layer 110, a floating body layer 120, a source 130, and a drain ( 140, a gate insulating layer 150, a first gate 160, a resistance change material layer 170, and a second gate 180.

In an embodiment of the present invention, the semiconductor substrate 100 will be described with reference to the P-type silicon substrate. However, the semiconductor substrate 100 may be made of a general material used for the semiconductor substrate, and may be made of, for example, silicon, silicon germanium, tensile silicon or tensile silicon germanium, or silicon carbide.

The hole encapsulation layer 110 and the floating body layer 120 are sequentially formed on the substrate 100. Here, the hole enveloping layer 110 is a layer for preventing holes from escaping from the floating body layer 120 so that holes can accumulate in the floating body layer 120 as described below. The hole surrounding layer 110 may be formed of an insulator such as a general oxide. In addition, the hole encapsulation layer 110 may be an impurity mixed layer. Here, the impurity mixed layer means germanium or a high concentration (1 × 10 ¹⁸ / cm ^{3 in the} semiconductor substrate 100). Or the layer into which the N-type impurity ions are implanted or the P-type impurity ions are implanted. Meanwhile, the description of the impurity mixed layer will be described in detail with reference to FIG. 3.

The floating body layer 120 is formed of a material constituting the body of a conventional field effect transistor. The floating body layer 120 is formed so that its thickness is thicker than the maximum depletion width of the channel of the fusion memory device according to the present invention. That is, a partially depleted layer is formed.

The resistance change material layer 170 refers to a layer made of any known material having a property that the resistance of the material varies depending on the applied voltage. The resistance change material layer 170 may include nickel (Ni) oxide, titanium (Ti) oxide, hafnium (Hf) oxide, zirconium (Zr) oxide, zinc (Zn) oxide, tungsten (W) oxide, cobalt (Co) oxide, At least one of vanadium (V) oxide, copper (Cu) oxide, and aluminum (Al) oxide.

In addition, the source body 130 and the drain 140 are formed on the hole surrounding layer 110 with the floating body 120 interposed therebetween.

The gate insulating layer 150 is formed on the floating body 120, and the first gate 160, the resistance change material layer 170, and the second gate 180 are sequentially formed on the gate insulating layer 150. . Meanwhile, the formation of the gate insulating layer 150, the first gate 160, the resistance change material layer 170, and the second gate 180 will be described in detail with reference to FIG. 4.

As shown in FIGS. 3A to 3D, an energy band diagram of the floating body 120, the hole encapsulation layer 110, and the substrate 100 of the fused memory device according to an embodiment of the present invention will be described. do.

FIG. 3A illustrates a case where the hole encapsulation layer 110 is an ion implantation layer in which germanium ions are implanted, and the electron affinity (X) of silicon and germanium is almost equal to the energy level of the conduction band (Ec). Becomes almost equal, and no barrier to electrons is formed. However, the difference in the valence band (Ev) energy level occurs due to the difference in the energy bandgap (Eg) according to the material difference, and due to this difference, a hole barrier is formed so that holes are localized in the barrier. Enemies are trapped and can collect holes.

FIG. 3B illustrates a case where the hole encapsulation layer 110 is an ion implantation layer implanted with P-type impurity ions, and an energy band diagram when a high concentration of N-type impurity is implanted. As shown in FIG. 3A, a barrier is formed. As a result, holes are blocked in the barrier and trapped within the hole envelope.

3C relates to the case where an N-type silicon substrate is used as the semiconductor substrate 100. As shown in FIG. 3C, holes are surrounded by the same principle as an energy band diagram when a high concentration of P-type impurities are injected.

FIG. 3D is an energy band diagram when silicon carbide (SiC) material is used as the hole encapsulation layer. Holes are surrounded by the same principle, and a method of forming silicon carbide includes an epitaxial growth method or carbon (C). Injection is preferred.

In summary, a method of forming the hole encapsulation layer 110 may include a silicon on insulator (SOI) substrate having a semiconductor substrate 100, a hole encapsulation layer 110, and a floating body layer 120 formed together. Can be used. In addition, as an alternative method, a hole encapsulation layer may be formed by growing a crystal film such as SiGe or SiC on a general silicon wafer, and depositing silicon again thereon. In addition, another method is to form the hole encapsulation layer 110 as an impurity mixture layer, which can be made relatively easily by implanting impurities into the semiconductor substrate 100 using a conventional semiconductor process as it is.

Hereinafter, a method of manufacturing a fused memory (URAM) device according to an embodiment of the present invention as described above will be described.

4A and 4D are cross-sectional views illustrating a method of manufacturing a fused memory device according to an embodiment of the present invention in the order of manufacturing processes.

As shown in FIG. 4A, the hole encapsulation layer 110, the floating body layer 120, the gate insulating layer 150, and the first gate 160 are sequentially formed on the semiconductor substrate 100. The floating body layer 120 is formed so that its thickness becomes a partially depleted (PD) substrate thicker than the maximum depletion width of the channel. If the thickness of the floating body is thinner than the maximum depletion width, the entire floating body is depleted, and in that depleted region, the newly formed holes are immediately recombined and disappeared, so that they become a partially depleted substrate. Sufficient body thickness should be provided. In addition, an insulating layer embedded silicon (SOI) substrate in which an insulating layer as the hole encapsulation layer 110 is formed inside the substrate 100 may be used. The insulating layer buried silicon substrate is divided into PD SOI (Partially Depleted Silicon On Insulator) and FD SOI (Fully Depleted Silicon On Insulator) substrate. Similarly, a PD SOI substrate using a thickness of the floating body layer 120 is thicker than the maximum depletion width of the channel. The floating body layer 120 may collect holes in an area adjacent to the hole surrounding layer 110 and may also be used as a channel between the source 130 and the drain 140.

Next, as shown in FIG. 4B, the gate insulating layer 150 and the first gate 160 are etched.

Next, as shown in FIG. 4C, the source 130 and the drain 140 spaced apart by the channel length in the floating body layer 120 may be diffused or ion implanted, a subsequent heat treatment, or the like. To form.

Finally, as shown in FIG. 4D, the resistance change material layer 170 and the second gate 180 are formed on the first gate 160. Herein, the method of forming the resistance change material layer 170 may include chemical vapor deposition, sputtering, atomic layer deposition, and metal organic chemical vapor deposition (MOCVD). Deposition, sol-gel, thermal oxidation or plasma oxidation methods can be used. In addition, the resistance change material layer 170 is not only an insulator characteristic as most metal oxides, but also has a property of changing a resistance value of a material according to a specific voltage applied thereto. That is, the resistance change material layer 170 has insulation as a metal oxide, but when a specific voltage is applied, the resistance change material layer 170 loses insulation and has a low resistance value. Here, the resistance change material layer 170 may maintain the changed resistance value even when a specific voltage applied thereto is removed. In addition, when a specific voltage is applied again, the lowered resistance value is changed to have original insulation. In addition, materials constituting the second gate 180 include aluminum (Al), copper (Cu), nickel (Ni), titanium (Ti), hafnium (Hf), zirconium (Zr), zinc (Zn), and tungsten. Metal materials such as (W), cobalt (Co), vanadium (V), erbium (Er) and platinum (Pt) are preferred.

Hereinafter, operation characteristics of the fusion memory (URAM) device according to an embodiment of the present invention as described above will be described.

5 is a view for explaining a method of operating a fusion memory device according to an embodiment of the present invention.

As illustrated in FIG. 5, the second gate 180 and the drain 140 are connected to each other to be connected to a bit line for the operation of the fusion memory device according to the exemplary embodiment. The gate 160 is connected to a word line, and the source 130 is grounded. When a voltage is applied to the first gate 160 and the drain 140, that is, when a first voltage that is a voltage difference enough to cause collision ionization between a word line and a bit line is applied, the drain 140 side is caused by collision ionization. Excess holes are created in the channel of. Since the excess holes are the hole encapsulation layer 110 below the floating body layer 120, there is no place to exit and are collected in the floating body 120 having the lowest potential. In this way, the transistors with the collected holes have a difference in the threshold voltage and the current level when there are no holes in the floating body, which distinguishes 0 and 1 by the difference. Accordingly, the fusion memory device may be used as a DRAM without a capacitor. However, when operating as a DRAM, if the resistance value of the resistive change material layer is changed due to the voltage applied between the word line and the bit line, that is, the insulation is lost and the resistance becomes low, the word line and the bit line are directly Since it is connected, it cannot operate as a DRAM. Therefore, when operating as a DRAM, the magnitude of the voltage applied to the word line and the bit line should be applied within a range in which collision ionization occurs but resistance change of the resistance change material layer does not occur.

In addition, the fusion memory device according to the present invention has the characteristics of a nonvolatile memory device. When a voltage equal to or greater than a specific value is applied between the first gate 160 and the second gate 180, that is, when a second voltage equal to or greater than a specific value is applied between the word line and the bit line, the resistance change material layer 170 may be formed. The resistance changes. In this case, since the resistance change is maintained even when the voltage applied to the gate is removed, the resistance change can operate as a nonvolatile memory device that can distinguish 0 and 1 according to the difference in the resistance value. Therefore, whether to operate the fused memory device according to the embodiment of the present invention using a DRAM or a nonvolatile memory device may be determined according to the magnitude of the voltage applied between the word line and the bit line. For example, since a voltage for operating with a DRAM is generally lower than a voltage for operating with a nonvolatile memory device, a specific voltage between the gate voltages is defined as a reference voltage. The operation of the fusion memory device according to the present invention is performed by operating the device at a voltage lower than the reference voltage when operating with a DRAM and operating the device at a voltage higher than the reference voltage when operating with a nonvolatile memory device. Can be determined.

FIG. 6 illustrates a structure of a cell array having a NOR structure of a fused memory device according to another exemplary embodiment of the present invention.

As shown in FIG. 6, the NOR cell array structure according to another embodiment of the present invention includes a plurality of unit cells arranged in a matrix of rows and columns. Here, in FIG. 6, the 2 × 3 unit cell structure has been described as an example. However, the present invention is not limited thereto, and embodiments of the present invention may be applied to unit cells having different sizes.

Hereinafter, although not shown, an example in which the fusion memory device according to the embodiment of the present invention configured as described above may be applied to other fusion memory devices will be described.

When the fusion memory device according to the embodiment of the present invention is applied to the cache memory of the current CPU, the fusion memory device according to the present invention is very small as 10F ² compared to the size of the SRAM (60 to 120F ² ), and thus, in terms of integration degree, Very advantageous. Given that the current cache memory size is several megabytes, the size of the cache memory can be increased up to several tens of megabytes. If you store programs and BIOS in advance and read them quickly at boot time, they are noticeably faster than reading from the hard disk. In addition, since the non-volatile operation when the power is turned off or the volatile high-speed operation when the power is supplied can be performed in one cell, its use can be variously changed according to the operation mode of the CPU.

As such, the technical configuration of the present invention described above can be understood by those skilled in the art that the present invention can be implemented in other specific forms without changing the technical spirit or essential features of the present invention.

Therefore, the exemplary embodiments described above are to be understood as illustrative and not restrictive in all respects, and the scope of the present invention is indicated by the following claims rather than the detailed description, and the meaning and scope of the claims and All changes or modifications derived from the equivalent concept should be interpreted as being included in the scope of the present invention.

1A is a cross-sectional view showing the operation of a capacitorless DRAM according to the prior art.

1B is a sectional view schematically showing a conventional RRAM.

2 is a cross-sectional view illustrating a structure of a fusion memory device according to an embodiment of the present invention.

3A and 3D are diagrams for explaining an energy band diagram of a fused memory device according to an embodiment of the present invention.

4A and 4D are cross-sectional views illustrating a method of manufacturing a fused memory device according to an embodiment of the present invention in the order of manufacturing processes.

5 is a view for explaining a method of operating a fusion memory device according to an embodiment of the present invention;

FIG. 6 is a view for explaining the structure of a cell array of NOR structure of a fused memory device according to another embodiment of the present invention; FIG.

<Explanation of symbols for the main parts of the drawings>

100: substrate 110: hole envelope layer

120: floating body layer 130: source

140: drain 150: gate insulating layer

160: first gate 170: resistance change material layer

180: second gate

Claims (15)

Semiconductor substrates; A hole encapsulation layer formed on the semiconductor substrate; A floating body layer formed on a predetermined region of the hole surrounding layer; A gate insulating layer formed on the floating body layer; A first gate formed on the gate insulating layer; A resistance change material layer formed on the first gate; A second gate formed on the resistance change material layer; And And a source and a drain formed on the hole encapsulation layer and spaced apart from each other on both sides of the floating body. The method of claim 1, The hole envelope layer, comprising an insulating material, Fusion memory device. The method of claim 1, The hole encapsulation layer forms a hole barrier or hole well to surround the holes, Fusion memory device. The method according to any one of claims 1 to 3, The hole envelope layer is an impurity mixed layer in which P-type or N-type impurities are injected into the semiconductor substrate, Fusion memory device. The method of claim 4, wherein The impurity mixed layer is a layer in which germanium (Ge) or carbon (C) is injected into the semiconductor substrate, Fusion memory device. The method of claim 1, The thickness of the floating body layer is formed thicker than the maximum depletion width of the channel of the fusion memory device, Fusion memory device. The method of claim 1, The resistance change material layer is nickel (Ni) oxide, titanium (Ti) oxide, hafnium (Hf) oxide, zirconium (Zr) oxide, zinc (Zn) oxide, tungsten (W) oxide, cobalt (Co) oxide, vanadium Containing at least one of (V) oxide, copper (Cu) oxide, and aluminum (Al) oxide, Fusion memory device. The method according to claim 1 or 7, The resistance change material layer has electrical conductivity when a voltage above a threshold voltage is applied. Fused memory devices. The method of claim 1, The fusion memory device may be connected to a plurality of word lines and a plurality of bit lines to form a memory cell array. The first gate is connected to any one of the plurality of word lines, and the second gate and the drain are connected to any one of the plurality of bit lines. Fused memory devices. A first step of sequentially forming a hole encapsulation layer, a floating body layer, a gate insulating layer, and a first gate on the semiconductor substrate; Etching a predetermined region on both sides of the gate insulating layer and the first gate; A third step of forming a source and a drain on the hole encapsulation layer and spaced apart from each other on both sides of the floating body; And A fourth step of sequentially forming a resistance change material layer and a second gate on the first gate A manufacturing method of a fused memory device comprising a. Constitutes a memory cell array in which unit cells are arranged in a matrix of a plurality of rows and a plurality of columns, A first memory unit generating and storing an excess carrier by a first voltage applied to any one of the unit cells, and storing data by using a change in a predetermined threshold voltage and current ; And And a second memory unit configured to store data by using a resistance change characteristic of a material having a variable resistance characteristic by a second voltage applied to the unit cell, wherein the write and erase operations of the first memory unit are performed. And generating and adjusting excess holes in the first memory unit such that the resistance change characteristic of the second memory unit does not occur by the first voltage smaller than the size of the second voltage. A method of operating a fused memory device for operating the fused memory device according to claim 11, Selecting one of a plurality of word lines and one of a plurality of bit lines as one unit cell; Controlling an excess hole generation operation of the first memory unit by adjusting a first voltage applied between a word line and a bit line connected to the selected unit cell; And And controlling a resistance change characteristic of the resistance change material layer of the second memory unit by adjusting a second voltage applied between the word line and the bit line connected to the selected unit cell. In the write and erase operations, the fusion memory device generates and adjusts excess holes in the first memory unit without causing the resistance change characteristic of the second memory unit to occur due to the first voltage smaller than the magnitude of the second voltage. How to operate. delete delete delete

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