WO2018009175A1

WO2018009175A1 - High speed single transistor non-volatile memory cell

Info

Publication number: WO2018009175A1
Application number: PCT/US2016/041059
Authority: WO
Inventors: Prashant Majhi; Elijah Karpov
Original assignee: Intel Corporation
Priority date: 2016-07-06
Filing date: 2016-07-06
Publication date: 2018-01-11

Abstract

A high speed single transistor suitable for a non-volatile memory cell is described. In one example, the memory cell has a source, a drain coupled to the source through a gate channel, a gate coupled to the gate channel, a floating gate between the gate and the gate channel, and a threshold switch between the floating gate and the gate channel.

Description

HIGH SPEED SINGLE TRANSISTOR NON- VOLATILE MEMORY CELL

FIELD

The present description relates to non-volatile memory and, in particular, to such a device with fast write times using a single device with a threshold switch.

BACKGROUND

NVRAM (Nonvolatile Random Access Memory) is a memory that retains its data without requiring any additional external power. Power is consumed only for reading and writing the memory. Solid state NVRAM is finding greater use in a wide variety of electronics and microelectronics devices and is moving into server and data provider systems. Solid state types of NVRAM are growing in use by offering smaller size and lower power consumption as compared to other types of memory. Currently, the dominant form of NVRAM is flash memory. However, flash requires a high voltage for programming by block to erase the memory and is limited in speed. There are other disadvantages in the configuration and lifetime of flash memory arrays.

Alternative solid state NVRAM technologies are under development to provide faster memory access at lower power and higher density. For embedded applications, the memory is built on the same die as the processor and so compatibility with CMOS (Complementary Metal Oxide Semiconductor) logic circuitry allows costs to be reduced.

A simple NAND cell may be structured using a thin film memory stack built as a one transistor (IT) NAND cell. This memory cell has a floating gate and a charge trap over a gate channel. The memory is written by changing the charge state on the floating gate. A tunnel oxide is used between the charge trap and the gate channel to prevent charge from migrating in and out of the charge trap unless a sufficiently high voltage is applied.

The sufficiently high voltage for writing to a flash NAND cell is on the order of 12V to 18 V, depending on the structure of the tunnel oxide and the charge trap. On the other hand logic circuits are operated at voltages of 1.5V to 3.2V. The power supply on a die with both types of circuits must be able to supply the full range of voltages which may vary by as much as an order of magnitude. The incompatibility of the tunnel oxide with logic circuitry increases as logic devices become smaller and lower power. BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements.

Figure 1 is a cross-sectional side view diagram of a IT memory cell according to an embodiment.

Figure 2 is a diagram of a program process for the IT memory cell of Figure 1 according to an embodiment.

Figure 3 is a graph of a response of a NAND memory cell to an applied gate voltage according to an embodiment.

Figure 4 to 7 are side cross-sectional side view diagrams of fabrication stages of a IT memory cell according to an embodiment.

Figure 8 is a cross-sectional side view diagram of a IT memory cell in a finFET structure according to an embodiment.

Figure 9 is a diagram of a portion of a NOR flash memory array incorporating a IT memory cell according to an embodiment.

Figure 10 is a diagram of a portion of a NAND flash memory array incorporating a IT memory cell according to an embodiment.

Figure 11 is a schematic diagram of a memory array and supporting circuits according to an embodiment.

Figure 12 is a block diagram of a computing device suitable for use with embodiments.

DETAILED DESCRIPTION

The present description relates to a one transistor (IT) NAND-like cell using a threshold selector instead of a tunneling oxide. The threshold selector allows for fast programing because it turns on under any programing bias that is above the threshold. It is an excellent conductor when biased beyond its threshold. The threshold selector also remains off during read operations. It is an excellent insulator when low or no bias is applied. This compact IT cell allows for a scaled IT memory in a 4F2 size and can be applied to embedded non- volatile memory (e-NVM) while being operated at a lower operating voltage.

The described approach to a high performance RRAM cell allows for improvements with scaled RRAM/NAND cells for larger, low power e-NVM arrays. It is also more suitable for integrating e-NVM into SoCs (System on a Chip). The performance is improved compared to a traditional IT NAND or NOR cell. In addition e-NVM arrays may be constructed with low operating voltages. Figure 1 is a side cross-sectional side view diagram of a IT memory cell suitable for nonvolatile memory both for embedded and discrete memory arrays. The memory cell is formed on a silicon substrate. There is a source 102 coupled to a doped well on one side of the transistor and a drain 104 coupled to a doped well on the other side of the transistor. The transistor may be n-type or p-type and accordingly the wells may be n-type or p-type, depending on the particular configuration of the memory array. A gate channel 101 is between the source and drain below the gate of the transistor. The gate is formed of a stack over the gate channel. A threshold switch 106 is formed over the gate channel in the substrate. A floating gate 108 is formed over the threshold switch and a blocking oxide 110 is formed over the floating gate 108. A control gate is formed over the blocking oxide 110. While a floating gate is described herein, a charge trap may alternatively be used in some configurations, depending on the particular component design.

In operation, to program or write to the cell a voltage V greater than the threshold voltage V_TH of the threshold switch 106 is applied to the control gate 112. This has two effects. In other words a bias difference greater than the VTH is applied between the control gate and the channel. First the voltage at the control gate draws charge from between the silicon channel 101 in the substrate and below the threshold switch through the threshold switch into the floating gate 108. Second, it overcomes the threshold voltage of the threshold switch so that there is little resistance to the flow of charge. The charge is trapped in the floating gate and affects the resistance through the gate channel between the source and the drain.

When sufficient charge has passed through the threshold switch, then the write voltage is disconnected from the control gate or the voltage is lowered to a voltage that is below the threshold voltage VTH- The lower voltage inhibits charge from moving in either direction between the channel and the floating gate because it is lower than the threshold of the switch Figure 2 shows a program or write process in which a voltage V is applied to the control gate 112. Charge 122 propagates from the channel 101 through the threshold switch 106 to the floating gate 108. Because of the applied voltage, charge 124 does not travel in the opposite direction.

The application of a voltage of one polarity will cause charge to be pulled into the floating gate as shown. The application of an equal voltage of opposite polarity will cause charge to be repulsed from the floating gate through the threshold switch and into the channel under the gate. Viewed another way, one polarity will draw electrons into the floating gate and the other polarity will draw holes into the floating gate. The result is that the trapped charge will either be positive or negative either enhancing current flow from source to drain or impeding current flow from source to drain. In this way either a 1 or 0 or either an ON or OFF may be stored in the cell.

In some embodiments, the voltage that is applied to the control gate is pulsed. Each pulse is higher than VTH at its peak and is also lower than VTH at its minimum. This allows charge to collect in the channel between pulses so that the response to each pulse is more rapid than for a sustained voltage. The pulses have a lower total duty cycle than a sustained voltage so that the total power is lower and less heat is generated.

In order to read the cell, the control gate voltage is set to some value below the threshold voltage of the threshold switch, VTH- The transistor' s resistance from source to drain is then measured. The lower control gate voltage eliminates or reduces the effect of any charge flow between the channel and floating gate. The transistor's resistance from source to drain depends primarily on the amount of charge trapped in the floating gate, because this charge effectively modulates the transistor's threshold voltage. The more electrons that are trapped in the floating gate the higher the transistor resistance. Multiple states per cell may be measured by storing different amounts of charge in the floating gate to represent different states. The difference in charge can be measured as discrete transistor resistance states

The threshold selector turns on during programing to allow for fast charging of the floating gate. The reaction of the threshold switch is significantly faster than a tunnel oxide used in other NAND cells. The tunnel oxide operates by allowing tunneling currents to pass through the oxide. The tunnel oxide requires a far higher voltage to cause the tunneling than VTH and there is still significant resistance for charge to tunnel through the oxide. The result of using the threshold switch is a faster response with more charge traveling faster at a lower input gate voltage. The precise value of VTH for the threshold selector may be controlled during fabrication by choosing geometry and materials for the device.

Figure 3 is a graph of a response of a NAND memory cell to an applied gate voltage.

The voltage applied to the control gate is shown on the horizontal axis and the resulting current into or out of the floating gate is shown on the vertical axis. The long gentle curve 140 corresponds to a response through a tunnel oxide. As shown, as more voltage is applied to the control gate, more charge is accumulated in the floating gate. The rate of charge accumulation is directly related to the applied voltage.

A steep abrupt curve 142 corresponds to a response through a threshold switch. A first section 144 is for all voltages below VTH- In this area there is almost no flow into or out of the floating gate. This is shown as an almost horizontal line in which a change in applied voltage has almost no effect on the charge flow. When the V_TH is exceeded at the control gate, there is an abrupt transition 146. After the transition, the flow becomes very high shown as a virtually vertical line. In this section, a very small increase in voltage at the control gate has a dramatic effect on charge flow but the effect runs out very quickly so that charge flow has reached a maximum very close to the threshold voltage. Notice that this flow is greater than for the tunnel oxide at all but the lowest voltages. The result is a faster cell that operates at a much lower voltage. The voltage may be as low as one tenth of the normal tunnel oxide voltage with a much faster response.

The lower voltage and faster response allows provides for a much lower energy to program and read the bits. At a bit cell level, the illustrated structure can operate more than ten times faster in speed than a tunnel oxide device. This allows for read and write times in the tens of nanosecond as compared to microseconds for a tunneling oxide-based cell. In addition, the control gate voltage may be a tenth the energy to surpass the threshold and change the stored state of the cell. While a tunnel oxide may require over 10 volts, the threshold selector may respond at 1-4V with a current as low as 10μΑ to 1mA. The particular characteristics of the threshold selector may be adapted to different applications based on the structure, dimensions, and materials that are used.

Figures 4-7 shows cross-sectional side view diagrams of stages of fabrication to produce a memory cell as described herein. At a first fabrication stage, threshold switch material 204 is deposited over a silicon substrate 202. The threshold switch material has a composition and a layer thickness selected to provide the desired threshold voltage and current flow characteristics. Chemical vapor deposition (CVD) may be used to apply the selected material.

Any of a variety of different or combined materials may be used. In some cases a metal mixed with an oxide may be used including Cu doped SiOx, Ag doped SiOx, Vanadium oxide (V0₂), Niobium Oxide (Nb0₂), SrV0₂, CrV0₂, CuxV₂0₅, SmNi0₃, etc. Alternatively, a chalcogenide-based material may be used mixed with one or more Group VI elements, e.g. Se, Te, S, etc. In other embodiments, a multicomponent chaclogenide alloy, such as ACh, ABCh, etc. may be used where Ch is group VI element such as S, Se, Te while A and B are group IV (Si, GE) and Group V (As, Sb ), respectively.

Figure 5 is a cross-sectional side view diagram of a second stage of fabrication of further building up the gate electrode by applying a floating gate 206 over the completed threshold switch 204 and a blocking oxide 208 over the floating gate. The floating gate may be formed by applying any of a variety of materials that are able to hold a charge. Any of a variety of different metal nitrides may be used. As examples a layer of TiN, polysilicon, WN, SiN, TaN, TaAIN, TiSiN, etc. may be applied by CVD to form the floating gate. The blocking oxide may then be applied by depositing a layer of AI2O₃, S1O2, HfAlO, ZrAlO, etc.

Figure 6 is a cross-sectional side view diagram of a third stage of fabrication after applying a control gate 210 over the blocking oxide. The control gate may be formed of a suitable conductive material. A variety of metals or other materials may be used such as TiN, W, WN, polysilicon, or other gate materials.

Figure 7 shows a final stage of the memory cell as a cross-sectional side view diagram. In order to form the multilayer structure into an array of memory cells, a patterned layer of photoresist may be formed over the control gate layer. The layers may then be removed by plasma etching to form discrete columns of the layers with exposed silicon substrate exposed in between. The exposed silicon may then be doped to form sources 212 and drains 214 on either side of the each gate column. Electrodes (not shown) may then be formed to complete the memory cell. And the remaining photoresist may be removed to expose the control gates.

As an alternative, the switch material 204 may be deposited by first applying a patterned mask over the silicon to expose only the areas that are to become gates. The patterned mask for the threshold switch may remain in place until after the charge gate is deposited. After the gate is formed then the mask may be removed to expose the silicon base and allow the silicon to be doped to form the sources and drains.

While the examples provided above are directed to planar MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structures, a similar approach may be used to form

FinFET (Fin Field Effect Transistor) structures as well. Figure 8 is a side cross-sectional view of a FinFET using a similar threshold switch structure. A silicon fin 304 is formed on a substrate 302. A threshold switch 306 is formed over the fin. A floating gate 308, blocking oxide 310, and control gate 312 are then formed over and around the threshold switch 306 on the fin 304 in the same order as for the planar structure. The source and drain are then formed but are not visible in this view because they are on either side of the plane of the page.

The described high speed threshold switch device may be used in a NOR flash cell type of architecture as shown in Figure 9. Figure 9 is a circuit diagram of a NOR circuit flash memory array for storing a byte (6 bits) of data. A set of switch devices 404, 406, 408, 410, 412, 414, such as the threshold switch devices of Figure 1 are coupled in pairs with the drains of each pair coupled together and to a ground. The sources are coupled to a bit line and the gates are each coupled to a distinct word line, labeled word line 0 to word line 5. While six devices are shown there may be more. Due to the high current flow and fast response of the threshold switch, such a NOR array has both fast write and read times. This makes a NOR array suitable for many high speed applications including those currently being served by DRAM (Dynamic Random Access Memory). However, in contrast to DRAM, a NOR array as described does not require refreshes to maintain the stored memory state. This reduces power consumption, circuit complexity, and heat generation as compared to current DRAM systems.

Figure 10 is a circuit diagram of a NAND circuit flash memory array for storing a byte (8 bits) of data using a set of switch devices 460, 461, 462, 463, 464, 465, 466, 467 such as the switch device of Figure 1. The threshold switch devices are coupled in series the drain of each one being coupled to the source of the next one. While eight devices are shown there may be more. The row of switches has a bit line select transistor 456 coupled between the bit line and one of the transistors in the row. A ground select transistor is coupled between the transistor at the opposite end of the row and ground. The select transistors are coupled to externally controlled select lines (not shown) and each other transistor in the row has a gate coupled to a respective word line 0, 1, 2, 3, 4, 5, 6, 7.

The examples described above pertain to realizing the NAND or NOR arrays in a two dimensional layout, such as one in which the transistor channel is parallel to the wafer surface. The proposed cell with threshold selector may also be implemented in 3D structures in which the transistor channel is vertical or perpendicular to the wafer surface. The NAND design, for example, may be implemented as 3D NAND suitable for large scale commercial applications.

The threshold switch structure of Figure 9 offers faster write or program cycles than tunnel oxide devices. The read speed is not significantly faster because of the limitations of the NAND flash architecture. Even though the threshold switch devices have faster read times, these are faster than can be used by current NAND flash architecture so that the total system speed may not be improved until enhancements to the architecture allow.

Figure 11 is a schematic of a nonvolatile NAND array 701 including a plurality of NAND cells with threshold switches 702, similar to that of Figure 1. A similar array may be modified to be a NOR array. The array 705 in this example is a bidirectional cross point array including any number of independent memory stacks 702, each stack is coupled through a contact gate electrode and a source electrode. Each column is associated with a word line driven by a column select circuit in column select circuitry 725 coupled to the source electrode of each NAND element. Each row is associated with a bit line driven by a row select circuit in row select circuitry 730 coupled to the contact gate of each NAND memory cell. In an operation, R/W control circuitry 720 receives memory access requests (e.g., from a local processor or communication chip in which the memory is embedded), generates the requisite control signals based on the requests (e.g., read, write 0, or write 1), and controls the row and column select circuitry 725, 730. Voltage supplies 710, 715 are controlled to provide the voltage necessary to bias the contact gates to facilitate the requested action on one or more bit lines 702. Row and column select circuitry 725, 730 applies the supplied voltage across array 705 to access a selected word line for reads. Row select circuitry 725, column select circuitry 730, and R/W control circuitry 720 may be implemented with any known technology. In one exemplary embodiment, the maximum supply voltage that is available from voltage supplies 710, 715 for a write operation is less than 1.5 volt.

Figure 12 illustrates a computing device 100 in accordance with one implementation. The computing device 100 houses a board 2. The board 2 may include a number of components, including but not limited to a processor 4 and at least one communication chip 6. The processor 4 is physically and electrically coupled to the board 2. In some implementations the at least one communication chip 6 is also physically and electrically coupled to the board 2. In further implementations, the communication chip 6 is part of the processor 4.

Depending on its applications, computing device 100 may include other components that may or may not be physically and electrically coupled to the board 2. These other components include, but are not limited to, volatile memory (e.g., DRAM) 8, non-volatile memory (e.g., ROM) 9, flash memory (not shown), a graphics processor 12, a digital signal processor (not shown), a crypto processor (not shown), a chipset 14, an antenna 16, a display 18 such as a touchscreen display, a touchscreen controller 20, a haptic actuator array 21, a battery 22, an audio codec (not shown), a video codec (not shown), a power amplifier 24, a global positioning system (GPS) device 26, a compass 28, an accelerometer (not shown), a gyroscope (not shown), a speaker 30, a camera 32, and a mass storage device (such as hard disk drive) 10, compact disk (CD) (not shown), digital versatile disk (DVD) (not shown), and so forth). These components may be connected to the system board 2, mounted to the system board, or combined with any of the other components.

The communication chip 6 enables wireless and/or wired communications for the transfer of data to and from the computing device 100. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 6 may implement any of a number of wireless or wired standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, Ethernet derivatives thereof, as well as any other wireless and wired protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 100 may include a plurality of communication chips 6. For instance, a first communication chip 6 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second

communication chip 6 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

Many of the components of the computing device may include memory on a die with logic devices or may have memory or logic devices on different dies in the same package. The memory device may be packaged together with a die that includes memory. The processor, memory devices, communication devices, or other components may all include or be packaged with memory or logic transistors fabricated or configured as described herein. The term

"processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

In various implementations, the computing device 100 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set- top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, wearables, and drones. In further implementations, the computing device 100 may be any other electronic device that processes data.

Embodiments may be adapted to be used with a variety of different types of packages for different implementations. References to "one embodiment", "an embodiment", "example embodiment", "various embodiments", etc., indicate that the embodiment(s) so described may include particular features, structures, or characteristics, but not every embodiment necessarily includes the particular features, structures, or characteristics. Further, some embodiments may have some, all, or none of the features described for other embodiments.

In the following description and claims, the term "coupled" along with its derivatives, may be used. "Coupled" is used to indicate that two or more elements co-operate or interact with each other, but they may or may not have intervening physical or electrical components between them. As used in the claims, unless otherwise specified, the use of the ordinal adjectives "first", "second", "third", etc., to describe a common element, merely indicate that different instances of like elements are being referred to, and are not intended to imply that the elements so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner.

The drawings and the forgoing description give examples of embodiments. Those skilled in the art will appreciate that one or more of the described elements may well be combined into a single functional element. Alternatively, certain elements may be split into multiple functional elements. Elements from one embodiment may be added to another embodiment. For example, the specific location of elements as shown and described herein may be changed and are not limited to what is shown. Moreover, the actions of any flow diagram need not be implemented in the order shown; nor do all of the acts necessarily need to be performed. Also, those acts that are not dependent on other acts may be performed in parallel with the other acts. The scope of embodiments is by no means limited by these specific examples. Numerous variations, whether explicitly given in the specification or not, such as differences in structure, dimension, and use of material, are possible. The scope of embodiments is at least as broad as given by the following claims.

The following examples pertain to further embodiments. The various features of the different embodiments may be variously combined with some features included and others excluded to suit a variety of different applications. Some embodiments pertain to a memory cell that includes a source, a drain coupled to the source through a gate channel, a gate coupled to the gate channel, a floating gate between the gate and the gate channel, and a threshold switch between the floating gate and the gate channel.

In further embodiments the threshold switch provides a high resistance to charge flow between the gate channel and the floating gate when the voltage applied to the gate is below a threshold and a low resistance to charge flow between the gate channel and the floating gate when the voltage applied to the gate is above the threshold.

In further embodiments the threshold switch comprises a metal mixed with an oxide.

In further embodiments the metal is copper, chromium, samarium, or silver and the oxide is a silicon, vanadium or niobium oxide.

In further embodiments the floating gate comprises a metal or a polysilicon, or a metal nitride.

In further embodiments the gate channel is formed in a fin of a FinFET (Field Effect Transistor). In further embodiments the threshold switch is configured to allow the state of the floating gate to be changed when a voltage higher than a threshold voltage is applied to the gate and configured to maintain the state of the floating gate when a voltage lower than the threshold voltage is applied to the gate.

Some embodiments pertain to a memory array a bit line, a plurality of word lines, and a plurality of bit storage transistors, each having a source coupled to the bit line and a control gate coupled to a respective word line, the storage transistors further having a gate channel coupled to the control gate, a floating gate between the gate and the gate channel, and a threshold switch between the floating gate and the gate channel.

In further embodiments the storage transistors are coupled to the bit line directly and wherein the storage transistors each have a drain coupled to a ground to form a NOR array.

In further embodiments each storage transistor except for one is coupled to the bit line each through a connection from the source to a drain of another storage transistor, the one transistor being coupled directly to the bit line transistor to form a NAND array.

In further embodiments the threshold switch comprises a multicomponent chalcogenide alloy having a Group IV element, a Group V element, and a Group VI element.

In further embodiments the threshold switch provides high current flow from the channel to the floating gate if a voltage above a threshold is applied to the control gate has and a low current flow from the channel to the floating gate if a voltage below the threshold is applied to the control gate.

In further embodiments the array is embedded in a processor die.

Some embodiments pertain to a method of operating a memory cell that includes applying a voltage higher than a threshold voltage to a gate of a memory cell, the gate being coupled to a gate channel; the gate channel being coupled between a source and a drain wherein the voltage overcomes a threshold switch between a floating gate and the gate channel to allow charge to flow between the floating gate and the gate channel to set a state in the floating gate, applying a voltage lower than the threshold voltage to maintain the state of the floating gate, and reading the memory cell by applying a voltage to the source to measure the state of the floating gate.

In further embodiments applying a voltage comprises applying a sequence of voltage pulses having a high above the threshold voltage and a low below the threshold voltage. Further embodiments include setting an opposite state in the floating gate by applying a voltage higher than the threshold voltage with an opposite polarity to the gate of the memory cell.

Some embodiments pertain to a method of fabricating a memory cell that includes depositing a threshold switch over a silicon substrate, depositing a floating gate over the threshold switch, depositing a blocking oxide over the floating gate, depositing a control gate over the blocking oxide, and forming a source and a drain in the silicon substrate beside the threshold switch.

In further embodiments depositing a threshold switch comprises depositing a metal mixed with an oxide by chemical vapor deposition.

In further embodiments depositing a floating gate comprises depositing a metal nitride by chemical vapor deposition.

Claims

CLAIMS:

1. A memory cell comprising:

a source;

a drain coupled to the source through a gate channel;

a gate coupled to the gate channel;

a floating gate between the gate and the gate channel; and

a threshold switch between the floating gate and the gate channel.

2. The memory cell of Claim 1, wherein the threshold switch provides a high resistance to charge flow between the gate channel and the floating gate when the voltage applied to the gate is below a threshold and a low resistance to charge flow between the gate channel and the floating gate when the voltage applied to the gate is above the threshold.

3. The memory cell of Claim 1 or 2, wherein the threshold switch comprises a metal mixed with an oxide.

4. The memory cell of Claim 3, wherein the metal is copper, chromium, samarium, or silver and the oxide is a silicon, vanadium or niobium oxide.

5. The memory cell of Claim 3 or 4, wherein the floating gate comprises a metal or a polysilicon, or a metal nitride.

6. The memory cell of any one or more of the above claims, wherein the gate channel is formed in a fin of a FinFET (Field Effect Transistor).

7. The memory cell of any one or more of the above claims, wherein the threshold switch is configured to allow the state of the floating gate to be changed when a voltage higher than a threshold voltage is applied to the gate and configured to maintain the state of the floating gate when a voltage lower than the threshold voltage is applied to the gate.

8. A memory array comprising:

a bit line;

a plurality of word lines; and

a plurality of bit storage transistors, each having a source coupled to the bit line and a control gate coupled to a respective word line, the storage transistors further having a gate channel coupled to the control gate, a floating gate between the gate and the gate channel, and a threshold switch between the floating gate and the gate channel.

9. The memory array of Claim 8, wherein the storage transistors are coupled to the bit line directly and wherein the storage transistors each have a drain coupled to a ground to form a NOR array.

10. The memory array of Claim 8 or 9, wherein each storage transistor except for one is coupled to the bit line each through a connection from the source to a drain of another storage transistor, the one transistor being coupled directly to the bit line transistor to form a NAND array.

11. The memory array of any one or more of claims 8 - 10, wherein the threshold switch comprises a metal mixed with an oxide.

12. The memory array of Claim 11, wherein the threshold switch comprises a multicomponent chalcogenide alloy having a Group IV element, a Group V element, and a Group VI element.

13. The memory array of any one or more of claims 8 - 12, wherein the threshold switch provides high current flow from the channel to the floating gate if a voltage above a threshold is applied to the control gate has and a low current flow from the channel to the floating gate if a voltage below the threshold is applied to the control gate.

14. The memory array of any one or more of claims 8 - 13, wherein the array is embedded in a processor die.

15. A method of operating a memory cell comprising:

applying a voltage higher than a threshold voltage to a gate of a memory cell, the gate being coupled to a gate channel; the gate channel being coupled between a source and a drain wherein the voltage overcomes a threshold switch between a floating gate and the gate channel to allow charge to flow between the floating gate and the gate channel to set a state in the floating gate;

applying a voltage lower than the threshold voltage to maintain the state of the floating gate; and

reading the memory cell by applying a voltage to the source to measure the state of the floating gate.

16. The method of Claim 15, wherein applying a voltage comprises applying a sequence of voltage pulses having a high above the threshold voltage and a low below the threshold voltage.

17. The method of Claim 15 or 16, further comprising setting an opposite state in the floating gate by applying a voltage higher than the threshold voltage with an opposite polarity to the gate of the memory cell.

18. A method of fabricating a memory cell comprising:

depositing a threshold switch over a silicon substrate;

depositing a floating gate over the threshold switch; depositing a blocking oxide over the floating gate;

depositing a control gate over the blocking oxide; and

forming a source and a drain in the silicon substrate beside the threshold switch.

19. The method of Claim 18, wherein depositing a threshold switch comprises depositing a metal mixed with an oxide by chemical vapor deposition.

20. The method of Claim 18 or 19, wherein depositing a floating gate comprises depositing a metal nitride by chemical vapor deposition.