CN116936618A - Semiconductor device, preparation method and application method thereof - Google Patents
Semiconductor device, preparation method and application method thereof Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 148
- 238000000034 method Methods 0.000 title claims abstract description 35
- 238000002360 preparation method Methods 0.000 title abstract description 7
- 238000003860 storage Methods 0.000 claims abstract description 58
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 230000005641 tunneling Effects 0.000 claims abstract description 33
- 230000000903 blocking effect Effects 0.000 claims abstract description 28
- 229910052751 metal Inorganic materials 0.000 claims description 82
- 239000002184 metal Substances 0.000 claims description 82
- 238000002161 passivation Methods 0.000 claims description 47
- 238000004519 manufacturing process Methods 0.000 claims description 15
- 238000005192 partition Methods 0.000 claims description 14
- 230000005684 electric field Effects 0.000 claims description 12
- 230000008569 process Effects 0.000 claims description 10
- 230000000149 penetrating effect Effects 0.000 claims description 8
- 230000009471 action Effects 0.000 claims description 7
- 238000005468 ion implantation Methods 0.000 claims description 6
- 238000002955 isolation Methods 0.000 claims description 6
- 230000000694 effects Effects 0.000 abstract description 13
- 230000009286 beneficial effect Effects 0.000 abstract description 4
- 150000002500 ions Chemical class 0.000 description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
- 229910052814 silicon oxide Inorganic materials 0.000 description 11
- 229910052581 Si3N4 Inorganic materials 0.000 description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 230000015556 catabolic process Effects 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- -1 for example Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910015900 BF3 Inorganic materials 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical compound FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- HTXDPTMKBJXEOW-UHFFFAOYSA-N dioxoiridium Chemical compound O=[Ir]=O HTXDPTMKBJXEOW-UHFFFAOYSA-N 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 1
- 229910000457 iridium oxide Inorganic materials 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 229910001925 ruthenium oxide Inorganic materials 0.000 description 1
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- UONOETXJSWQNOL-UHFFFAOYSA-N tungsten carbide Chemical compound [W+]#[C-] UONOETXJSWQNOL-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The application discloses a semiconductor device and a preparation method and an application method thereof, and the semiconductor device comprises a semiconductor substrate, an epitaxial layer is formed on the semiconductor substrate, a first groove is formed in the epitaxial layer, a grid structure is formed in the first groove, a well region and a source region are formed in the epitaxial layer outside the first groove, wherein the grid structure comprises a functional medium region and a grid region, the functional medium region is formed on the inner wall surface of the first groove, and sequentially comprises a charge tunneling layer, a charge storage layer and a charge blocking layer from the inner wall of the first groove to the central direction, and the grid region is formed on the charge blocking layer and fills the first groove completely. By forming the grid structure in the first groove, induced charges are generated in the channel by utilizing the charge storage capacity of the functional medium region, the reverse bias effect between the source region and the drain region is enhanced, the drain-source leakage of the channel is reduced, and meanwhile, the charge storage capacity of the functional medium region is beneficial to expanding the threshold voltage range of the semiconductor device and improving the performance of the semiconductor device.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a semiconductor device, a preparation method and an application method thereof.
Background
Since the application of Power metal oxide semiconductor field effect transistors (Power MOS), new device structures and fabrication processes have been emerging in an effort to achieve the goals of maximum Power handling and minimum Power dissipation. Thus, it is typical practice to combine a large number of power MOS transistor cells into a single power MOS transistor, with each power MOS transistor cell outputting a relatively small amount of current. However, the power MOS transistor made by this method is very large and does not meet the current size requirements.
The grooves of the vertical MOS transistor are vertical, so that the density of the grooves can be improved, the chip size can be reduced, the current processing capacity of the device can be improved, and the vertical MOS transistor is one of main ways for achieving high-power processing and minimum power loss of the MOS transistor. As the size of the MOS device is reduced, the channel length is gradually shortened, resulting in a decrease in the distance between the source and the drain, which results in a deterioration of the control capability of the gate to the channel, and the drain-source leakage phenomenon also becomes easier to occur.
Therefore, how to provide a semiconductor device, a method for manufacturing the same, and a method for applying the same, so as to reduce the drain-source leakage of the channel on the basis of having smaller feature size, is a problem to be solved in the art.
Disclosure of Invention
The application aims to provide a semiconductor device, a preparation method and an application method thereof, which utilize the charge storage capacity of a functional medium region to generate induced charges in a channel, enhance the reverse bias effect between a source region and a drain region and reduce drain-source leakage. Meanwhile, the stored charges in the functional medium area can be used for changing the threshold voltage of the semiconductor device, so that the application range of the semiconductor device is widened.
In a first aspect, an embodiment of the present application provides a method for manufacturing a semiconductor device, including the steps of:
providing a semiconductor substrate with a first conductivity type;
forming an epitaxial layer on the upper surface of the semiconductor substrate, wherein the epitaxial layer comprises a well region and a source region;
a first groove is formed in the epitaxial layer, and penetrates through the source region and the well region;
the gate structure comprises a functional medium region and a gate region, the functional medium region is formed on the inner wall surface of the first trench, and the gate structure comprises a charge tunneling layer, a charge storage layer and a charge blocking layer, wherein the charge tunneling layer, the charge storage layer and the charge blocking layer are sequentially formed from the inner wall of the first trench to the center direction, and the gate region is formed on the charge blocking layer and completely fills the first trench.
In one possible embodiment, the well region and the source region are formed after the gate structure is formed, comprising the steps of:
forming an epitaxial layer on the periphery of the side wall of the first groove into a well region with a second conductivity type;
forming a source region having a first conductivity type on an upper surface of the well region;
the well region and the source region are formed by an ion implantation process.
In one possible embodiment, the epitaxial layer further comprises a drift region of the first conductivity type, the drift region being located between the semiconductor substrate and the well region, the first trench extending through the source region and the well region and into the drift region.
In one possible embodiment, the first groove is a U-shaped groove.
In one possible embodiment, after the step of forming the well region and the source region, the method further comprises the steps of:
forming an insulating layer on the epitaxial layer;
forming a first contact hole in the insulating layer, wherein the first contact hole penetrates through the insulating layer and exposes the well layer, and the first contact hole is filled with a first metal layer to be connected with the source layer;
forming a second contact hole in the insulating layer, wherein the second contact hole penetrates through the insulating layer and exposes the gate region, and the second metal layer is filled in the second contact hole to be connected with the gate region;
and forming a third metal layer on the insulating layer, wherein the third metal layer is respectively connected with the first metal layer and the second metal layer.
In one possible embodiment, further comprising forming a passivation structure on the third metal layer;
the passivation structure comprises a first passivation layer and a second passivation layer, the first passivation layer further comprises a partition area penetrating through the third metal layer, and the partition area separates the third metal layer above the first metal layer and the third metal layer above the second metal layer from each other; the second passivation layer further includes a filled passivation layer extending into the isolation region.
In one possible embodiment, the method further comprises:
and forming a fourth metal layer on the lower surface of the semiconductor substrate, wherein the fourth metal layer is electrically connected with the semiconductor substrate to form a drain electrode layer.
In a second aspect, there is also provided a semiconductor device characterized by comprising:
a semiconductor substrate having a first conductivity type;
an epitaxial layer on the semiconductor substrate, the epitaxial layer including a well region and a source region
The first groove is positioned in the epitaxial layer and penetrates through the source region and the well region;
the gate structure is positioned in the first groove, the gate structure comprises a functional medium region and a gate region, the functional medium region is positioned on the surface of the inner wall of the first groove, and the gate structure sequentially comprises a charge tunneling layer, a charge storage layer and a charge blocking layer from the inner wall of the first groove to the center direction, and the gate region is positioned on the charge blocking layer and fills the first groove.
In one possible embodiment, the epitaxial layer further comprises a drift region having a first conductivity type, the drift region being located between the semiconductor substrate and the well region, the source region being located on the well region, the first trench extending through the source region and the well region and into the drift region, the well region having the second conductivity type, the source region having the first conductivity type.
In one possible embodiment, the first groove is a U-shaped groove.
In one possible embodiment, the semiconductor device further includes an insulating layer on the well region, and first and second contact holes spaced apart within the insulating layer; the first contact hole penetrates through the insulating layer and exposes the well region, the first metal layer is filled in the first contact hole to connect with the source region, the second contact hole penetrates through the insulating layer and exposes the gate region, and the second metal layer is filled in the second contact hole to connect with the gate region; the third metal layer is positioned on the insulating layer and is respectively connected with the first metal layer and the second metal layer.
In one possible embodiment, the semiconductor device further comprises a passivation structure on the third metal layer, the passivation structure comprising a first passivation layer and a second passivation layer, the first passivation layer further comprising a partition region extending through the third metal layer, the partition region separating the third metal layer over the first metal layer and the third metal layer over the second metal layer from each other; the second passivation layer further includes a filled passivation layer extending into the isolation region.
In one possible embodiment, the semiconductor device further comprises a fourth metal layer located on the lower surface of the semiconductor substrate, and electrically connected with the semiconductor substrate to form a drain electrode layer.
In a third aspect, there is also provided a method for applying a semiconductor device, including:
after the semiconductor device is turned off and standby, programming voltage is applied to the gate region, so that electrons or holes tunnel into the charge storage layer under the action of an electric field, and channel leakage between the source electrode and the drain electrode is blocked;
before the semiconductor device is started to operate, an erasing voltage is applied to the grid electrode area, and electrons or holes in the charge storage layer are released;
the polarity of the erasing voltage is the same as the first conductive type, and the polarity of the erasing voltage is opposite to the polarity of the programming voltage.
Compared with the prior art, the application has the following beneficial effects:
the application provides a semiconductor device, a preparation method and an application method thereof. The gate structure comprises a functional medium region and a gate region, the functional medium region is formed on the surface of the inner wall of the first groove, and sequentially comprises a charge tunneling layer, a charge storage layer and a charge blocking layer from the inner wall of the first groove to the center direction, the gate region is formed on the charge blocking layer and fills the first groove, and the gate structure is formed in the first groove, so that the reverse bias effect between the source region and the drain region is enhanced by utilizing the charge storage capacity of the functional medium region, and the channel drain-source leakage is reduced. Meanwhile, the charge storage capacity of the functional medium region is beneficial to changing the threshold voltage of the semiconductor device, so that the application range of the semiconductor device is widened, and the performance of the semiconductor device is improved.
And forming a U-shaped first groove in the well region, forming a grid structure in the first groove, and adjusting the depth of the U-shaped groove and the vertical width of the well region, so that the effective channel length between the source region and the drain region can be adjusted, and the possibility of breakdown of the source and the drain is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1-7 are schematic structural views of a semiconductor device according to an embodiment of the present application at various stages of fabrication;
fig. 8A-8C are energy band diagrams illustrating one principle of operation of a semiconductor device according to an embodiment of the present application;
fig. 9A-9B are diagrams illustrating an operational embodiment of a semiconductor device, according to an embodiment of the present application;
fig. 10A-10B are simplified model diagrams illustrating one embodiment of the operation of a semiconductor device, in accordance with embodiments of the present application.
Illustration of:
a 100 semiconductor substrate; 110 drain regions; a 120 epitaxial layer; 130 well regions; 140 source regions; 150 drift region; 200 first trenches; 300 gate structure; 310 a functional media area; 311 charge tunneling layer; 312 charge storage layers; 313 charge blocking layer; 320 gate regions; 400 insulating layers; 500 a first metal layer; 510 a second metal layer; 520 a third metal layer; 530 a fourth metal layer; 600 passivation structures; 610 a first passivation layer; 611 partition; 620 a second passivation layer; 621 is filled with a passivation layer.
Detailed Description
The following specific examples are presented to illustrate the present application, and those skilled in the art will readily appreciate the additional advantages and capabilities of the present application as disclosed herein. The application may be practiced or carried out in other embodiments that depart from the spirit and scope of the present application, and details of the present application may be modified or changed from various points of view and applications.
In the description of the present application, it should be noted that, unless explicitly stated and limited otherwise, the term "connected" should be interpreted broadly, and for example, it may be a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art according to the specific circumstances. Furthermore, the terms "first" and "second," etc. are used merely to distinguish between descriptions and should not be construed as indicating or implying relative importance.
According to one aspect of the present application, a method of manufacturing a semiconductor device is provided. However, the present embodiment is merely an example, and the method for manufacturing the semiconductor device should not be limited thereto. The preparation method of the semiconductor device comprises the following steps:
providing a semiconductor substrate 100 having a first conductivity type;
forming an epitaxial layer 120 on the upper surface of the semiconductor substrate 100, the epitaxial layer 120 including a well region 130 and a source region 140;
a first groove 200 is formed in the epitaxial layer 120, and the first groove 200 penetrates through the source region 130 and the well region 140;
the gate structure 300 is formed in the first trench 200, the gate structure 300 includes a functional dielectric region 310 and a gate region 320, the functional dielectric region 310 is formed on an inner wall surface of the first trench 200, and sequentially includes a charge tunneling layer 311, a charge storage layer 312 and a charge blocking layer 313 from an inner wall of the first trench 200 to a central direction, and the gate region 320 is formed on the charge blocking layer 313 and completely fills the first trench 200.
The following describes in further detail the method for manufacturing a semiconductor device according to an embodiment of the present application with reference to fig. 1 to 7 and specific examples. By way of example, the semiconductor device may be any semiconductor device that incorporates a semiconductor substrate 100, a gate region 320, and a source region 140, including but not limited to a metal-oxide semiconductor field effect transistor (MOS-FET), an Insulated Gate Bipolar Transistor (IGBT), a memory transistor, or a microelectromechanical system. In this embodiment, the semiconductor device may be a PMOS transistor, an NMOS transistor, or a CMOS integrated circuit. The first conductivity type may be N-type or P-type, the second conductivity type may be P-type or N-type, the N-type dopant ion may be, for example, phosphorus (P) ion, arsenic (As) ion, or antimony (Sb) ion, and the P-type dopant ion may be, for example, boron (B) ion, boron fluoride (bf2+) ion, gallium (Ga) ion, or indium (In) ion.
Referring to fig. 1, a semiconductor substrate 100 is provided, in which a first conductivity type dopant ion is implanted from an upper surface of the semiconductor substrate 100 by ion implantation to form a first conductivity type semiconductor substrate 100, i.e., a drain region 110, and an epitaxial material having the first conductivity type is epitaxially grown on the drain region 110 by an epitaxial growth technique to form an epitaxial layer 120. The semiconductor substrate 100 may be monocrystalline silicon, polycrystalline silicon, or silicon on insulator, and the upper surface of the semiconductor substrate 100 is a surface on which the epitaxial layer 120 is prepared. In this example, the drain region 110 is heavily doped, and the epitaxial layer 120 is lightly doped.
Referring to fig. 2, an isolation region of the first trench 200 is defined by a photolithography technique, and the first trench 200 is etched in the epitaxial layer 120 by a combination of dry etching and wet etching. It should be noted that, for convenience of describing the present structure, only a part of the first trench 200 is shown in the drawings, and those skilled in the art can easily understand that, in a specific application, a plurality of first trenches 200 are formed according to actual needs.
Referring to fig. 3, a gate structure 300 is formed by filling a trench with an epitaxial growth or deposition technique. The gate structure 300 includes a functional dielectric region 310 and a gate region 320, the functional dielectric region 310 includes a charge tunneling layer 311, a charge storage layer 312 and a charge blocking layer 313 sequentially from an inner wall of the first trench 200 toward a center direction, and the gate region 320 is formed on the charge blocking layer 313 and fills the first trench 200. For example, a polysilicon layer (Poly) is deposited within the first trench 200 using low pressure chemical vapor deposition to form the gate region 320. The functional dielectric region 310 is disposed between the epitaxial layer 120 and the gate region 320 within the first trench 200 to be electrically isolated from each other to block charge from entering the gate region 320.
The specific process of forming the functional dielectric region 310 in the first trench 200 includes: first, a charge tunneling layer 311 is formed in the first trench 200, then a charge storage layer 312 is formed on the charge tunneling layer 311, and finally a charge blocking layer 313 is formed on the charge storage layer 312. As an example, the charge tunneling layer 311 may include silicon oxide, silicon oxynitride, or a combination of both, the charge storage layer 312 may include nitride or oxynitride, and the charge blocking layer 313 may include silicon oxide, silicon oxynitride, or a combination of both. For the charge tunneling layer 311, the charge storage layer 312 and the charge blocking layer 313 formed on the surface of the well region 130 outside the first trench 200, dry etching or wet etching is adopted to etch the same, and only the functional dielectric region 310 remains in the first trench 200.
As an example, the charge tunneling layer 311 and the charge blocking layer 313 may be silicon oxide layers, and the charge storage layer 312 may be a silicon nitride layer, where the first silicon oxide layer and the second silicon oxide layer distinguish the same composition of the charge tunneling layer 311 and the charge blocking layer 313, respectively. The first silicon oxide layer is preferably formed by an in-situ vapor method, so that uniformity of the silicon oxide surface can be improved, and the silicon nitride layer and the second silicon oxide layer can be formed by deposition or epitaxial growth techniques known in the art. The silicon nitride layer and the second silicon oxide layer are formed, for example, by chemical vapor deposition. The silicon nitride layer is used to store charge and may trap charge in the silicon nitride, the first silicon oxide layer may be used to block charge stored in the silicon nitride from returning to the semiconductor substrate, and the second silicon oxide layer disposed over the silicon nitride may block charge in the silicon nitride from moving to the gate region 320.
Referring to fig. 4, the well region 130 is formed by implanting second conductive type doped ions into the epitaxial layer 120 at both sides of the gate structure 300 through an ion implantation process. The well region 130 is formed in the epitaxial layer 120, and the second conductivity type ion doping depth is smaller than the thickness of the epitaxial layer 120, and the drift region 140 is the portion of the epitaxial layer 120 existing between the semiconductor substrate 100 and the well region 130.
After the well region 130 is formed, the epitaxial layer above the well region is made into the source region with the first conductivity type through an ion implantation process again; as an example, the source region 140 is formed by implanting first conductivity type dopant ions into the surface of the well region 130 by an ion implantation process using photolithography to define the region of the source region 140.
It is noted that the first trench 200 extends through the source region 140 and the well region 130 to the drift region 150. The source region 140 is formed over the well region 130, and the thickness of the source region 140 is smaller than the thickness of the well region 130.
The channel is formed on the surface of the well region 130 covered by the gate structure 300 and the inner wall of the first trench 200, which provides a current path between the source region 140 and the drain region 110, and the gate region 320 is used to control the current conduction between the source region 140 and the drain region 110. The source region 140 is located at the top of the sidewall of the first trench 200, and the drain region 110 is located at the bottom of the first trench 200, that is, there is a height difference between the source region 140 and the drain region 110, and an effective conductive channel between the two is nonlinear, so that the channel length can be effectively increased, and the short channel effect can be overcome. As an example, the shape of the first trench 200 is U-shaped, and the effective channel length between the source region 140 and the drain region 110 can be adjusted by adjusting the depth of the U-shaped trench and the vertical width of the well region 130, so as to improve the short channel effect of the semiconductor device and reduce the possibility of breakdown of the source and the drain.
Referring to fig. 5, after the formation of the gate region 320 and the source region 140, electrode extraction is further performed, which specifically includes: an insulating layer 400 is formed on the well region 130, and the insulating layer 400 may be an oxide, nitride, or oxynitride. Then, defining a first contact hole and a second contact hole area through a photoetching technology, and forming the first contact hole and the second contact hole through an etching technology. The first contact hole penetrates the upper and lower surfaces of the insulating layer 400 and exposes the well region 130, and the second contact hole penetrates the upper and lower surfaces of the insulating layer 400 and exposes the gate region 320. Finally, the first metal layer 500 is filled in the first contact hole and connected with the source region 140 to form a source electrode contact layer; the second contact hole is filled with a second metal layer 510 inside to be connected with the gate region 320 to form a gate electrode contact layer. The first and second metal layers 500 and 510 may be composed of the same or different kinds of conductive materials, for example, tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more thereof. In addition, after the first and second metal layers 500 and 510 are formed, a third metal layer 520 formed on the insulating layer 400 is further included to be connected to the first and second metal layers 500 and 510.
Referring to fig. 6, after the third metal layer 520 is formed, forming a passivation structure 600 is further included to protect the formed semiconductor device structure. The passivation structure 600 includes a first passivation layer 610 and a second passivation layer 620 formed on the third metal layer 520. Wherein the first passivation layer 600 further includes a partition region 611 penetrating the third metal layer 520, the partition region 611 separating the third metal layer 520 located above the first metal layer 500 and the third metal layer 520 located above the second metal layer 510 from each other; the second passivation layer 620 also includes a filled passivation layer 621 that extends into the isolation region 611.
Referring to fig. 7, finally, a fourth metal layer 530 is formed on the lower surface of the semiconductor substrate 100, which is the surface of the semiconductor substrate remote from the epitaxial layer 120, to serve as a drain electrode layer. Preferably, the semiconductor substrate 100 is also subjected to a thinning process prior to the formation of the fourth metal layer 530.
According to a second aspect of the present application, a semiconductor device is provided. Referring to fig. 7, the semiconductor device includes:
a semiconductor substrate 100 having a first conductivity type;
an epitaxial layer 120 on the semiconductor substrate 100, the epitaxial layer including a well region 130 and a source region 140;
a first trench 200 located within the epitaxial layer 120 and penetrating the source region 140 and the well region 130;
the gate structure 300 is located in the first trench 200, the gate structure 300 includes a functional dielectric region 310 and a gate region 320, the functional dielectric region 310 is located on an inner wall surface of the first trench 200, and sequentially includes a charge tunneling layer 311, a charge storage layer 312 and a charge blocking layer 313 from an inner wall of the first trench 200 to a central direction, and the gate region 320 is located on the charge blocking layer 313 and fills the first trench 200.
The functional dielectric region 310 can improve the source-drain leakage of the channel of the semiconductor device and can controllably adjust the threshold voltage of the semiconductor device. By applying a voltage to the gate region 320, when the applied voltage exceeds the threshold of the charge tunneling layer 311, charges in the channel tunnel through the charge tunneling layer 311 under the action of the electric field, enter the charge storage layer 312, and after stopping applying the voltage, the charges are stored in the charge storage layer 312, and the charges in the charge storage layer 312 can generate induced charges with opposite polarities in the channel, so that the reverse bias effect between the source region 140 and the drain region 110 is enhanced, and the source-drain leakage of the channel is reduced. Meanwhile, the charge in the charge storage layer 312 can also make the turn-on voltage of the semiconductor device become high or low after the semiconductor device is electrified, so as to change the threshold voltage of the semiconductor device and achieve the effect of controllable adjustment of the threshold voltage of the semiconductor device.
Preferably, the thickness of the charge tunneling layer 311 is 2-10 nm, and the charges drift and accelerate along the electric field direction under the action of the electric field, so as to obtain the kinetic energy tunneling into the charge storage layer 312, and the kinetic energy is derived from the voltage applied to the gate region 320. When the charge tunneling layer 311 is too thick, the difficulty of tunneling charges into the charge storage layer 312 is increased, and when the charge tunneling layer 311 is too thin, charges stored in the charge storage layer 312 cannot be well blocked from returning into the channel, that is, the operation voltage of the semiconductor device can be changed by changing the thickness of the charge tunneling layer 311, so that the performance of the semiconductor device can be adjusted.
As an example, the epitaxial layer 120 further includes a drift region 150 having the first conductivity type, located between the semiconductor substrate 100 and the well region 130, the source region 140 located above the well region 130, and the first trench 200 extending through the source region 140 and the well region 130 into the drift region 150. The shape of the first trench 200 is preferably U-shaped, and the U-shaped trench may form a U-shaped channel region, which is advantageous for increasing the effective length of the conductive channel, improving the short channel effect of the semiconductor device, and reducing the possibility of breakdown of the source and drain electrodes.
Preferably, the drift region 150 is a lightly doped region, the source region 140 and the semiconductor substrate 100 are heavily doped regions having the first conductivity type, and the well region 130 is located between the source region 140 and the semiconductor substrate 100 and is a lightly doped region having the second conductivity type, so that the semiconductor substrate 100 and the source region 140 are kept reversely biased.
As an example, the semiconductor device further includes an insulating layer 400 disposed on the well region 130, and a first contact hole and a second contact hole disposed in the insulating layer 400 at intervals, the first contact hole penetrating the insulating layer 400 and exposing the well region 130, the first contact hole being filled with a first metal layer 500 to connect the source region 140 to form a source electrode contact layer, the second contact hole penetrating the insulating layer 400 and exposing the gate region 320, the second contact hole being filled with a second metal layer 510 to connect the gate region 320 to form a gate electrode contact layer, the source electrode layer and the gate electrode layer being isolated from each other by the insulating layer 400. The third metal layer 520 is positioned on the insulating layer 400 and is connected to the first metal layer 500 and the second metal layer 510.
As an example, the semiconductor device further includes a passivation structure layer 600, and the passivation structure 600 includes a first passivation layer 610 and a second passivation layer 620. Wherein the first passivation layer 610 further includes a partition region 611 penetrating the third metal layer 520, the partition region 611 separates the third metal layer 520 located above the first metal layer 500 and the third metal layer 520 located above the second metal layer 510 from each other, and the second passivation layer 620 includes a filling passivation layer 621 that also extends into the partition region 611. The passivation structure 600 is disposed on the surface of the semiconductor device structure to isolate the semiconductor device structure from the external environment, thereby preventing the device structure from being affected by environmental factors.
As an example, a fourth metal layer 530 may be further formed on the lower surface of the semiconductor substrate 100, which is electrically connected to the semiconductor substrate 100 to form a drain electrode layer.
According to a third aspect of the present application, there is provided a method for applying the above semiconductor device, comprising:
after the semiconductor device is turned off and standby, programming voltage is applied to the gate region 320, so that electrons or holes tunnel into the charge storage layer 312 under the action of an electric field, and channel leakage between the source and the drain is blocked;
before the semiconductor device is started to operate, an erasing voltage is applied to the gate region 320 to erase and release electrons or holes in the charge storage layer 312;
the polarity of the erasing voltage is the same as the first conductive type, and the polarity of the programming voltage is opposite to the polarity of the erasing voltage. As an example, when the semiconductor device is an N-type semiconductor device, the first conductivity type is N-type, the applied erase voltage is a negative voltage, and the program voltage is a positive voltage; when the semiconductor device is a P-type semiconductor device, the first conductivity type is P-type, the applied erase voltage is a positive voltage, and the program voltage is a negative voltage.
Specifically, the operation of the semiconductor device may include three states: a program state, an erase state, and a standby state, referring to fig. 8A-8C, are illustrated energy diagrams showing one principle of operation of a semiconductor device according to an embodiment of the present application.
As an example, referring to fig. 8A, in a standby state, i.e., without any operation applied to the N-type semiconductor device, both the charge tunneling layer 311 and the charge blocking layer 313 function as a barrier to prevent tunneling of charges (electrons or holes), so that electrons in the charge storage layer 312 remain relatively stable. In the programming state, referring to fig. 8B, a programming voltage (positive voltage) is applied between the gate region 320 and the channel of the N-type semiconductor device, the band bends under the action of an electric field, and the charge storage layer 312 can draw electrons from the channel, tunnel into the charge storage layer 312 from the charge tunneling layer 311 via the band-tunneling effect, and store in the charge storage layer 312. In the erased state, referring to fig. 8C, an erase voltage (negative voltage) is applied between the gate region 320 and the channel of the N-type semiconductor device, the energy band bends under the action of the electric field, and the charge storage layer 312 can draw holes from the channel, tunnel into the charge storage layer 312 from the charge tunneling layer 311 via the band tunneling effect, and recombine with electrons stored in the charge storage layer 312, so that the trapped electrons stored in the charge storage layer 312 are erased.
Preferably, the internal charge programming or erasing of the charge storage layer 312 can also be achieved by varying the intensity and pulse width of the programming pulse and the erase pulse, varying the amount of charge tunneled into the charge storage layer 312.
As an example, fig. 9A is a schematic diagram illustrating an application process of the semiconductor device according to the embodiment of the present application, and fig. 10 is a simplified schematic diagram of the semiconductor device according to the embodiment of the present application. As an alternative embodiment, first, an N-type semiconductor device is provided, and before the semiconductor device is turned on, referring to fig. 10A, a voltage of-7V is applied to the gate region 320, holes in the channel are led out, tunneled to the charge storage layer 312 through the gate electric field acceleration, and recombined with electrons therein, so that the gate voltage is turned off after the charge in the charge storage layer 312 is erased. Then, the semiconductor device is turned on, and after a threshold voltage of 1.7V is applied to the gate region 320 and the semiconductor device is normally operated, the semiconductor device is turned off; finally, referring to fig. 10B, a voltage of 7V is applied to the gate region 320, electrons in the channel are extracted, and are accelerated to tunnel to the charge storage layer 312 and stored by the gate electric field, so that the charge storage layer 312 is negatively charged, and correspondingly positively charged induced charges are generated in the channel, thereby generating an effect of turning off the gate region 320 and reducing the generation of source-drain leakage of the channel. It should be noted that the structures in fig. 10A and 10B are merely simplified models, and are not the same as the structures of the semiconductor device in the present application, so as to facilitate understanding of the operation principle.
As an example, fig. 9B is a schematic diagram illustrating another application process of the semiconductor device according to the embodiment of the present application. As an alternative embodiment, first, a P-type semiconductor device is provided, a gate voltage of 7V is applied to a gate region 320 before the semiconductor device is turned on, electrons in a channel are led out, tunneling to a charge storage layer 312 is accelerated by a gate electric field, and the electrons are recombined with holes in the charge storage layer 312, so that the gate voltage is turned off after the charges in the charge storage layer 312 are erased; then, the semiconductor device is turned on, and after a threshold voltage of-1.7V is applied to the gate region 320 and the semiconductor device is normally operated, the semiconductor device is turned off; finally, a gate voltage of-7V is applied to the gate region 320, holes in the channel are led out, tunneling is accelerated to the charge storage layer 312 through a gate electric field and stored, the charge storage layer 312 is positively charged, and correspondingly negatively charged induced charges are generated in the channel, so that the effect of turning off the gate region 320 is generated, and the generation of source-drain leakage of the channel is reduced.
As can be seen from the above technical solutions, the semiconductor device, the method for manufacturing the same, and the method for applying the same provided by the present application include providing a semiconductor substrate, forming an epitaxial layer 120 on the semiconductor substrate 100, forming a first trench 200 in the epitaxial layer 120, forming a gate structure 300 in the first trench 200, and forming a well region 130 and a source region 140 in the epitaxial layer 120 outside the first trench 200. The gate structure 300 includes a functional dielectric region 310 and a gate region 320, the functional dielectric region 310 is formed on an inner wall surface of the first trench 200, and sequentially includes a charge tunneling layer 311, a charge storage layer 312 and a charge blocking layer 313 from an inner wall of the first trench 200 toward a center direction, the gate region 320 is formed on the charge blocking layer 313 and fills the first trench 200 completely, and by forming the gate structure 300 in the first trench 200, a reverse bias effect between the source region 140 and the drain region 110 is enhanced by using a charge storage capability of the functional dielectric region 310, so as to reduce channel drain-source leakage. Meanwhile, the charge storage capability of the functional dielectric region 310 is beneficial to changing the threshold voltage of the semiconductor device, so that the application range of the semiconductor device is widened, and the performance of the semiconductor device is improved.
The first U-shaped trench 200 is formed in the well region 130, the gate structure 300 is formed in the U-shaped trench, and the effective channel length between the source region 140 and the drain region 110 can be adjusted by adjusting the depth of the U-shaped trench and the vertical width of the well region 130, so that the effective channel length between the source region 140 and the drain region 110 is increased, and the possibility of breakdown of the source and the drain is reduced. For high power devices, such as IGBTs, the collector and emitter leakage in the off state can be reduced from the nA order to the pA order by utilizing the charge storage capability of the functional dielectric region 310. Meanwhile, the charge storage capability of the functional dielectric region 310 can also make the semiconductor device applicable to some ultra-long standby products, such as mobile phones, electronic bracelets, electronic watches, and GPS trackers.
The foregoing is merely a preferred embodiment of the present application, and it should be noted that modifications and substitutions can be made by those skilled in the art without departing from the technical principles of the present application, and these modifications and substitutions should also be considered as being within the scope of the present application.
Claims (14)
1. A method of manufacturing a semiconductor device, comprising:
providing a semiconductor substrate with a first conductivity type;
forming an epitaxial layer on the upper surface of the semiconductor substrate, wherein the epitaxial layer comprises a well region and a source region;
a first groove is formed in the epitaxial layer, and penetrates through the source electrode region and the well region;
the gate structure comprises a functional medium region and a gate region, the functional medium region is formed on the inner wall surface of the first trench, a charge tunneling layer, a charge storage layer and a charge blocking layer are sequentially formed from the inner wall of the first trench to the center direction, and the gate region is formed on the charge blocking layer and completely fills the first trench.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the well region and the source region are formed after the gate structure is formed, comprising the steps of:
forming an epitaxial layer on the periphery of the side wall of the first groove into the well region with the second conductivity type;
forming the upper surface of the well region into the source region having the first conductivity type;
the well region and the source region are formed by an ion implantation process.
3. The method of manufacturing a semiconductor device according to claim 2, wherein the epitaxial layer further includes a drift region having a first conductivity type, the drift region being located between the semiconductor substrate and the well region, the first trench extending through the source region and the well region and into the drift region.
4. A method of manufacturing a semiconductor device according to any one of claims 1 to 3, wherein the first trench is a U-shaped trench.
5. The method of manufacturing a semiconductor device according to claim 2, further comprising, after the step of forming the well region and the source region, the step of:
forming an insulating layer on the epitaxial layer;
forming a first contact hole in the insulating layer, wherein the first contact hole penetrates through the insulating layer and exposes the well layer, and a first metal layer is filled in the first contact hole to connect the source layer;
forming a second contact hole in the insulating layer, wherein the second contact hole penetrates through the insulating layer and exposes the gate region, and a second metal layer is filled in the second contact hole to connect the gate region;
and forming a third metal layer on the insulating layer, wherein the third metal layer is respectively connected with the first metal layer and the second metal layer.
6. The method of manufacturing a semiconductor device according to claim 5, further comprising forming a passivation structure on the third metal layer;
the passivation structure comprises a first passivation layer and a second passivation layer, the first passivation layer further comprises a partition area penetrating through the third metal layer, and the partition area separates the third metal layer above the first metal layer and the third metal layer above the second metal layer from each other; the second passivation layer further includes a filled passivation layer extending into the isolation region.
7. The method for manufacturing a semiconductor device according to claim 1, further comprising:
and forming a fourth metal layer on the lower surface of the semiconductor substrate, wherein the fourth metal layer is electrically connected with the semiconductor substrate to form a drain electrode layer.
8. A semiconductor device, comprising:
a semiconductor substrate having a first conductivity type;
an epitaxial layer on the semiconductor substrate, the epitaxial layer including a well region and a source region
A first trench located within the epitaxial layer and penetrating the source region and the well region;
the gate structure is positioned in the first groove and comprises a functional medium region and a gate region, the functional medium region is positioned on the surface of the inner wall of the first groove, the gate structure sequentially comprises a charge tunneling layer, a charge storage layer and a charge blocking layer from the inner wall of the first groove to the central direction, and the gate region is positioned on the charge blocking layer and fills the first groove.
9. The semiconductor device of claim 8, wherein the epitaxial layer further comprises a drift region of a first conductivity type, the drift region being located between the semiconductor substrate and the well region, the source region being located on the well region, the first trench extending through the source region and well region and into the drift region; the well region has a second conductivity type and the source region has a first conductivity type.
10. The semiconductor device according to any one of claims 8 to 9, wherein the first trench is a U-shaped trench.
11. The semiconductor device of claim 9, further comprising an insulating layer over the well region, and first and second contact holes spaced apart within the insulating layer; the first contact hole penetrates through the insulating layer and exposes the well region, a first metal layer is filled in the first contact hole to connect the source region, the second contact hole penetrates through the insulating layer and exposes the gate region, and a second metal layer is filled in the second contact hole to connect the gate region; and the third metal layer is positioned on the insulating layer and is respectively connected with the first metal layer and the second metal layer.
12. The semiconductor device of claim 11, further comprising a passivation structure on the third metal layer, the passivation structure comprising a first passivation layer and a second passivation layer, the first passivation layer further comprising a partition region extending through the third metal layer, the partition region separating the third metal layer above the first metal layer and the third metal layer above the second metal layer from each other; the second passivation layer further includes a filled passivation layer extending into the isolation region.
13. The semiconductor device of claim 8, further comprising a fourth metal layer on a lower surface of the semiconductor substrate that is electrically connected to the semiconductor substrate to form a drain electrode layer.
14. A method of applying a semiconductor device comprising the semiconductor device according to any one of claims 8-13, the method comprising:
after the semiconductor device is turned off and standby, programming voltage is applied to the gate region, so that electrons or holes tunnel into the charge storage layer under the action of an electric field, and channel leakage between a source electrode and a drain electrode is blocked;
before the semiconductor device starts to operate, an erasing voltage is applied to the grid electrode region, and electrons or holes in the charge storage layer are released;
wherein the polarity of the erase voltage is the same as the first conductivity type, and the polarity of the program voltage is opposite to the polarity of the erase voltage.
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