KR100859512B1 - A wiring, a method for manufacturing the wiring, and a thin film transistor array substrate including the wiring, and a method for manufacturing the substrate - Google Patents

Abstract

First, a conductive material is stacked and patterned on an upper portion of a substrate to form a horizontal gate wiring including a gate line, a gate electrode, and a gate pad on the substrate. Next, a gate insulating film is formed by laminating silicon nitride, and a semiconductor layer and an ohmic contact layer are sequentially formed thereon. Subsequently, the silicon layer of the semiconductor layer or the ohmic contact layer is HF-processed, and a conductive material of silver alloy is laminated and patterned on the amorphous silicon layer, and the data includes a data line, a source electrode, a drain electrode, and a data pad crossing the gate line. Form the wiring. Subsequently, annealing is performed to form a compound layer containing silicon and a silver alloy additive material between the protective film or the data wiring and the silicon layer including silicon oxide containing silicon diffused from the silicon layer on the data wiring, and then nitriding. Silicon or organic materials are stacked to form a protective film and patterned by dry etching to form contact holes that expose the drain electrode, the gate pad, and the data pad, respectively. Next, IZO or ITO is stacked and patterned to form pixel electrodes, auxiliary gate pads, and auxiliary data pads electrically connected to the drain electrodes, the gate pads, and the data pads, respectively.

Silver alloy, adhesion, resistivity, annealing, silicon

Description

WIRING, A METHOD FOR MANUFACTURING THE WIRING, AND A THIN FILM TRANSISTOR ARRAY SUBSTRATE INCLUDING THE WIRING, AND A METHOD FOR MANUFACTURING THE SUBSTRATE}

1 is a conceptual diagram illustrating a process of forming a protective film on the upper wiring of the silver alloy laminated on the silicon substrate in the manufacturing method of the wiring according to an embodiment of the present invention.

FIG. 2 is a conceptual diagram illustrating a process of forming a compound including a silver alloy additive material and silicon at an interface between a silicon substrate and a wire of a silver alloy in a method of manufacturing a wire according to an embodiment of the present invention.

3A to 3C are graphs showing the results of analyzing the change from the surface of the silver alloy (AgCo alloy) thin film to the silicon substrate according to the change in the annealing temperature through AES (auger electron spectroscopy),

4A and 4B are graphs showing the results of analyzing oxygen (O ₂ ) binding energy on the upper surface of the AgCo alloy thin film by XPS (X-ray photo-emission spectroscopy) according to the annealing process.

FIG. 5 is a graph showing the results of analyzing changes of components from the surface of the AgNi alloy thin film to the silicon substrate after annealing at 500 ° C. through AES (auger electron spectroscopy),

6A and 6B are graphs showing the results of analyzing the change from the surface of the AgCu alloy thin film to the silicon substrate according to the change of the annealing temperature through AES (auger electron spectroscopy),

7 is a layout view of a thin film transistor substrate for a liquid crystal display according to a first exemplary embodiment of the present invention.

FIG. 8 is a cross-sectional view of the thin film transistor substrate of FIG. 7 taken along the line VIII-VIII.

9A, 10A, 11A, and 12A are layout views of a thin film transistor substrate illustrating an intermediate process of manufacturing a thin film transistor substrate for a liquid crystal display device according to a first embodiment of the present invention, according to a process sequence thereof.

FIG. 9B is a cross-sectional view taken along the line IXb-IXb 'of FIG. 9A;

FIG. 10B is a cross-sectional view taken along the line Xb-Xb 'of FIG. 10A and illustrates the next step of FIG. 9B;

FIG. 11B is a cross-sectional view taken along the line XIb-XIb ′ of FIG. 11A, and is a cross-sectional view showing the next step of FIG. 10B;

12B is a cross-sectional view taken along the line XIIb-XIIb ′ in FIG. 12A, and is a cross-sectional view illustrating the next step in FIG. 11B.

13 is a layout view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

14 and 15 are cross-sectional views of the thin film transistor substrate illustrated in FIG. 13 taken along lines XIV-XIV ′ and XV-XV ′;

16A is a layout view of a thin film transistor substrate in a first step of manufacturing according to the second embodiment of the present invention;

16B and 16C are cross-sectional views taken along lines XVIb-XVIb 'and XVIc-XVIc', respectively, of FIG. 16A.

17A and 17B are cross-sectional views taken along the XVIb-XVIb 'line and the XVIc-XVIc' line in FIG. 16A, respectively, and are cross-sectional views in the next steps of FIGS. 16B and 16C;

18A is a layout view of a thin film transistor substrate in the next steps of FIGS. 17A and 17B,

18B and 18C are cross-sectional views taken along the lines XVIIIb-XVIIIb 'and XVIIIc-XVIIIc' in FIG. 18A, respectively;

19A, 20A, 21A and 19B, 20B, 21B are cross-sectional views taken along the lines XVIIIb-XVIIIb 'and XVIIIc-XVIIIc' in FIG. 18A, respectively, illustrating the following steps in the order of processing ,

22A and 22B are cross-sectional views taken along the lines XVIIIb-XVIIIb 'and XVIIIc-XVIIIc' in FIG. 18A, which are cross-sectional views showing the following steps in the order of the processes of FIGS. 21A and 21B;

FIG. 23A is a layout view of a thin film transistor substrate in the next step of FIGS. 22A and 22B;

23B and 23C are cross-sectional views taken along the lines XXIIIb-XXIIIb 'and XXIIIc-XXIIIc' of FIG. 23A, respectively.

The present invention relates to a wiring, a method of manufacturing the same, and a thin film transistor array substrate including the wiring and a method of manufacturing the same.

In general, since the wiring of the semiconductor device or the display device is used as a means for transmitting a signal, it is required to suppress the signal delay.

In order to prevent signal delay, it is required to form wiring using a conductive material having a low resistance, and the conductive material may be silver (Ag) or aluminum (Al) having the lowest specific resistance. However, when the wiring made of an aluminum-based conductive material is in contact with the semiconductor layer made of silicon, the wiring should be formed in a multilayer structure to prevent aluminum from diffusing into the silicon layer, which complicates the manufacturing process. In order to improve this problem, it is preferable to use a silver-based conductive material having a lower resistivity than aluminum. However, in the case of using silver or silver alloy (Ag alloy) has a disadvantage in that the adhesion between the wiring and the silicon layer below it is inferior. In addition, in order to prevent the surface from deteriorating in the manufacturing process of the semiconductor device, a protective film covering the wiring with an insulating material should be formed. NH ₃ , a gas used to form the protective film of silicon nitride, reacts with silver to provide a In order to corrode, it is difficult to apply the process of forming a protective film in the case of silver alloy wiring.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a wiring having low resistance and excellent adhesion and a thin film transistor array substrate having the wiring.

In addition, another technical problem to be achieved by the present invention is to provide a method for manufacturing a wiring that can prevent degradation and a method for manufacturing a thin film transistor array substrate including the same.

In order to solve this problem, in the present invention, a thin film of a silver alloy is laminated on the silicon layer and then annealed to form a compound containing an additive and silicon except for silver in the silver alloy and the silver alloy between the silicon layer and the thin film. A protective film of silicon oxide is formed on the thin film of.

In this case, the silver alloy is based on silver (Ag), and V, W, Cr, Cu, Fe, Li, Mn, Mo, Nb, Ni, Zr, Co, or Ti in an atomic percentage of 0.01-20 atomic%. The additive material for the silver alloy of may include one or two.

Annealing is preferably performed at a temperature range of 200-500 ° C., and an insulating film may be formed on top of the thin film before the compound layer is formed.

Such a wiring and a method of manufacturing the same according to the present invention can be similarly applied to a thin film transistor array substrate and a method of manufacturing the same.

In the method for manufacturing a thin film transistor array substrate according to the present invention, first, a gate wiring including a gate line and a gate electrode is formed, and a gate insulating film is laminated thereon. Subsequently, a semiconductor layer of silicon is formed on the gate insulating film, and a data line including a data line, a source electrode, and a drain electrode is formed of a thin film of silver alloy on the semiconductor layer. Subsequently, annealing is performed to form a protective film made of silicon oxide containing silicon diffused from the semiconductor layer on top of the data wiring, or at least a silicon component of the semiconductor layer and an additive material for silver alloy of the thin film between the semiconductor layer and the data wiring. To form a compound layer comprising a.

In this case, the semiconductor layer may be HF-processed, and may further include a pixel electrode electrically connected to the drain electrode.

Then, a person having ordinary knowledge in the technical field to which the present invention pertains with reference to the accompanying drawings, a wiring, a manufacturing method thereof, a thin film transistor array substrate including the wiring, and a manufacturing method thereof according to the accompanying drawings. It demonstrates in detail so that implementation may be carried out easily.

A wiring thin film 200 made of a conductive material such as a silver alloy containing silver having the lowest specific resistance as a wiring of a semiconductor device, especially a display device, is formed by stacking the silicon thin film 100 on top and patterning it by a photolithography process. do. The silver alloy for forming the wiring thin film 200 according to the embodiment of the present invention is silver (Ag) as a base material, V, W, Cr, Cu, Fe, Li, Additives for silver alloys, such as Mn, Mo, Nb, Ni, Zr, Co, Ti, are included. In this case, the additive material for the silver alloy may include one or two, the silver alloy may be made of a binary or ternary alloy.

However, since the adhesion between the thin film for wiring 200 made of silver alloy and the silicon thin film 100 underneath is weak or it is difficult to laminate a protective film used to prevent deterioration of the semiconductor device, the silver alloy as described above is used for wiring. In order to use it as a conductive material, a technique for solving the aforementioned problems is required. In the manufacturing method of the wiring according to the embodiment of the present invention, the wiring thin film 200 is laminated on the silicon thin film 100, and then subjected to an annealing process, between the wiring thin film 200 and the silicon thin film 100 of the silver alloy. A silicide layer including at least a silver alloy additive material and silicon is formed or a protective film is formed on the wiring thin film 200 of the silver alloy. The annealing process is carried out in a vacuum or hydrogen or nitrogen atmosphere, and the treatment temperature and time range from 30 ° C. to 500 ° C. for 30 minutes to 2 hours. This will be described in detail with reference to the drawings.

FIG. 1 is a conceptual diagram illustrating a process of forming a protective film on a wiring of a silver alloy laminated on a silicon thin film in a method of manufacturing a wiring according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a thin film 200 of AgCo alloy including silver (Ag), which is a base material, and 0.01-20.0atomic% cobalt (Co), is laminated on the silicon thin film 100. As a result of performing annealing, which is a heat treatment, at a temperature range of 200 to 500 ° C., in the silver alloy thin film 200, cobalt (Co) is precipitated at a grain boundary, and the silicon component of the silicon thin film 100 is precipitated cobalt. Accordingly, it diffuses to the surface of the silver alloy thin film 200 and bonds with oxygen in the air on the surface of the silver alloy thin film 200. As a result, a protective film 300 made of silicon oxide (SiO ₂ ) is formed on the silver alloy thin film 200. At this time, the protective film 300 has a function of protecting the thin film 200 in the manufacturing process of the semiconductor device, and can also omit the process of forming a protective film separately can simplify the manufacturing process of the semiconductor device. At this time, at the interface between the silicon thin film 100 and the silver alloy thin film 200, a compound layer including at least silicon and cobalt (Co), which is an additive material for silver alloy, is formed in the silicon thin film 100. And the adhesion between the silver alloy thin film 200 is increased. This will be described in detail with reference to FIG. 2.

FIG. 2 is a conceptual diagram illustrating a process of forming a compound including a silver alloy additive material and silicon at an interface between a silicon thin film and a silver alloy wire in a method of manufacturing a wire according to an embodiment of the present invention.

As shown in FIG. 2, a thin film 200 of AgCo alloy including silver (Ag), which is a base material, and 0.01-20.0 atomic% cobalt (Co), is stacked on top of the silicon thin film 100. Next, in order to suppress the formation of the protective film of silicon oxide on the silver alloy thin film 200 as shown in FIG. 1, a buffer film 400 is formed using an insulating material such as silicon nitride, and then annealing, which is a heat treatment process. Is carried out in the temperature range of 200-500 ° C. As a result, the silicon film of the silicon thin film 100 is prevented from being diffused along the grain boundary due to the buffer film 400, while at the interface between the silver alloy thin film 200 and the silicon thin film 100. A compound layer 120 containing at least silver and cobalt is formed. In this case, the compound layer 120 is formed through annealing to increase the adhesion between the silver alloy thin film 200 and the silicon thin film 100.

Next, the result of annealing after laminating a silver alloy thin film on top of a silicon thin film through an experimental example will be described. In the experimental example of the present invention, the silicon thin film was used as a single crystal silicon substrate.

Experimental Example 1

In Experimental Example 1, after depositing an AgCo alloy thin film containing silver based on silver on the silicon substrate and containing about 10 atomic percent cobalt, or after annealing, the surface of the silicon substrate was sputtered from the surface of the silver alloy thin film. The component was measured by AES (auger electron spectroscopy). Here, AES is a method of analyzing components through the energy emitted by irradiating an electron beam to the thin silver alloy thin film sputtered in an argon atmosphere.

3A to 3C are graphs illustrating the results of analyzing the components from the AgCo alloy thin film surface to the silicon substrate according to the annealing temperature change in Experimental Example 1 of the present invention through auger electron spectroscopy (AES); . Here, the vertical axis represents the content (concentration) of the exposed thin film in atomic%, the horizontal axis represents the sputtering time, Figure 3a is the result of performing AES in the state of laminating a silver alloy thin film, Figure 3b After stacking the silver alloy thin film and performing the AES in a state of annealing at 300 ℃, Figure 3c is a result of performing the AES in a state of annealing at 500 ℃ after laminating a silver alloy thin film. 3A to 3C, sputtering was performed at 100 kV / min, 200 kV / min and 175 kV / min with respect to the silicon oxide film, respectively.

As shown in FIG. 3A, when annealing was not performed, almost no oxygen component appeared on the surface of the AgCo alloy thin film.

As shown in FIG. 3B, when annealing was performed at about 300 ° C., it was confirmed that the silicon component diffused out to the surface of the silver alloy thin film at the initial stage of sputtering as compared with the case without annealing, as shown in FIG. 3C. When annealing is carried out at about ℃, it can be seen that a large amount of oxygen and silicon components are detected on the surface of the silver alloy thin film to form a protective film made of silicon oxide on the surface of the silver alloy thin film.

Experimental Example 2

In Experimental Example 2, the binding energy of the oxygen component detected on the upper portion of the silver alloy thin film will be examined.

4A and 4B illustrate X-ray photo-emission spectroscopy (XPS) of oxygen (O ₂ ) binding energy on the AgCo alloy thin film according to the annealing process in Experimental Example 3 of the present invention. This graph shows the results of the analysis. Here, XPS is a method of measuring the binding energy of the oxygen component by X-ray irradiation to the oxygen component, Figures 4a and 4b is not annealing and after annealing at a temperature of about 500 ℃ silver alloy The binding energy of oxygen formed on the thin film is measured, respectively.

As shown in FIGS. 4A and 4B, when the annealing is performed as compared with the case where the annealing is not performed, the binding energy of oxygen is 532.25 eV (oxygen binding energy in silicon oxide) at 532 eV (oxygen binding energy of oxygen molecules). It can be seen that the protective film of silicon oxide was formed on the upper portion of the silver alloy thin film when the annealing was performed.

Experimental Example 3

In Experimental Example 3, silver is a basic material, and a silver alloy (AgNi) thin film containing about 10.60 atomic% nickel (Ni) is laminated and annealed, and then the components from the surface of the silver alloy thin film to the silicon substrate are described. Let's do it.

FIG. 5 is a graph showing the results of analyzing the components from the AgNi alloy thin film surface to the silicon substrate after annealing at 500 ° C. in Experimental Example 3 of the present invention through auger electron spectroscopy (AES).

As shown in FIG. 5, a silver alloy (AgNi) thin film containing nickel was laminated on the silicon substrate and annealed. As a result, a large amount of silicon component was detected on the surface of the silver alloy thin film at the beginning of sputtering. It was confirmed that the silicon component diffused to the top of the silver alloy thin film.                     

Experimental Example 4

In Experimental Example 4, silver is a basic material, and a silver alloy (AgCu) thin film containing about 10-20 atomic% copper (Cu) is laminated and annealed, and then the components from the surface of the silver alloy (AgCu alloy) thin film to the silicon substrate are applied. This will be described.

6A and 6B are graphs illustrating the results of analyzing the components from the AgCu alloy thin film surface to the silicon substrate by AES (auger electron spectroscopy) according to the annealing temperature change in Experimental Example 4 of the present invention. . Here, FIG. 6A is a result of performing AES in a state of laminating a silver alloy thin film, and FIG. 3B is a result of performing AES in a state of annealing at 500 ° C. after laminating a silver alloy thin film, and sputtering in FIGS. 6A and 6B. The silver silicon oxide film proceeded at a rate of 200 mA / min.

As shown in FIG. 6A, when annealing was not performed, almost no oxygen component appeared on the surface of the AgCo alloy thin film.

As shown in FIG. 6B, when annealing is performed at about 500 ° C., a large amount of oxygen and silicon components are detected on the surface of the silver alloy thin film at the initial stage of sputtering as compared with the case where the annealing is not performed. It can be seen that a protective film made of silicon is formed.

The wiring and the method of manufacturing the same according to the exemplary embodiment of the present invention may be applied to the thin film transistor array substrate and the method of manufacturing the same, which will be described in detail with reference to the accompanying drawings.                     

First, a structure of a thin film transistor array substrate for a liquid crystal display according to a first embodiment of the present invention will be described in detail with reference to FIGS. 7 and 8.

FIG. 7 is a layout view of a thin film transistor substrate for a liquid crystal display according to a first exemplary embodiment of the present invention, and FIG. 8 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 7 taken along the line VIII-VIII ′.

On the insulating substrate 110, a gate wiring made of silver having a low resistance or a binary or ternary silver alloy or a single film of aluminum or an aluminum alloy or a multilayer film including the same is formed. The gate wire is connected to the gate line 121 and the gate line 121 extending in the horizontal direction and connected to the gate pad 125 and the gate line 121 which receive a gate signal from the outside and transfer the gate signal to the gate line. A gate electrode 123 of the thin film transistor. Here, when the gate wirings 121. 125. 123 are a multilayer film, the gate material 121. 125.

On the substrate 110, a gate insulating layer 140 made of silicon nitride (SiN _x ) covers the gate lines 121, 125, and 123.

A semiconductor layer 150 made of a semiconductor such as amorphous silicon is formed on the gate insulating layer 140 of the gate electrode 125, and n + is heavily doped with silicide or n-type impurities on the semiconductor layer 150. Resistive contact layers 163 and 165 made of a material such as hydrogenated amorphous silicon are formed, respectively.                     

On the ohmic contacts 163 and 165 and the gate insulating layer 140, data lines 171, 173, 175, and 179 formed of a single layer of a silver alloy or a multilayer including the same are formed. The data line is formed in the vertical direction and crosses the gate line 121 to define a pixel, which is a branch of the data line 171 and the data line 171 and extends to the upper portion of the ohmic contact layer 163. ), Which is connected to one end of the data line 171 and is separated from the data pad 179 and the source electrode 173 for receiving an image signal from the outside, and is opposite to the source electrode 173 with respect to the gate electrode 123. The drain electrode 175 is formed on the ohmic contact layer 165. In addition, the data line may include an organic capacitor conductor pattern 177 overlapping the gate line 121 to improve the storage capacitance.

Here, the data wirings 171, 173, 175, 177, and 179 of the silver alloy have silver (Ag) as a base material, and V, W, Cr, Cu, Fe, Li, Additives for silver alloys, such as Mn, Mo, Nb, Ni, Zr, Co, Ti, are included. In this case, the additive material for the silver alloy may include one or two, the silver alloy may be made of a binary or ternary alloy. When the data wires 171, 173, 175, 177, and 179 are multi-layer films, a conductive material having excellent contact properties with other materials may be included.

A passivation layer 801 is formed on the data lines 171, 173, 175, 177, and 179 and the semiconductor layer 150 that is not covered by silicon oxide, and has a thickness in the range of 100 to 400 nm.

An interlayer insulating layer 802 made of silicon nitride or an organic material having excellent planarization characteristics is formed on the passivation layer 801 and the substrate 10 that is not covered.

In the passivation layer 801 or the interlayer insulating layer 802, contact holes 185, 187, and 189 respectively exposing the drain electrode 175, the conductive pattern 177 for the organic capacitor, and the data pad 179 are formed. The contact hole 182 exposing the gate pad 125 is formed together with the insulating layer 140.

A pixel electrode 190 is formed on the interlayer insulating layer 802 to be electrically connected to the conductive capacitor conductor 177 and the drain electrode 175 through the contact holes 185 and 187. . In addition, an auxiliary gate pad 92 and an auxiliary data pad 97 connected to the gate pad 125 and the data pad 179 are formed on the interlayer insulating layer 801 through contact holes 182 and 189, respectively. . The pixel electrode 190, the auxiliary gates, and the data pads 92 and 97 are made of indium tin oxide (ITO) or indium zinc oxide (IZO), which are transparent conductive materials.

Here, the conductive capacitor pattern 177 connected to the pixel electrode 190 overlaps the gate line 121 to form a storage capacitor, and when the storage capacitor is insufficient, the same layer as the gate lines 121, 125, and 123. It is also possible to add a storage capacitor wiring.

The thin film transistor substrate for a liquid crystal display according to the first exemplary embodiment of the present invention includes a wire of a silver alloy containing silver having the lowest specific resistance, thereby minimizing a signal delay, thereby allowing a large area and A high resolution liquid crystal display device can be implemented. In addition, since the protective film 801 including the silicon component diffused through the grain boundary of the silver alloy wiring covers the wiring, it is possible to prevent the wiring from deteriorating through the protective film 801.

Next, a method of manufacturing the thin film transistor substrate for a liquid crystal display according to the first embodiment of the present invention will be described in detail with reference to FIGS. 7 and 8 and FIGS. 9A to 12B.

First, as shown in FIGS. 9A and 9B, a single film made of silver or a silver alloy or aluminum or an aluminum alloy having a low resistance thereon on the insulating substrate 110, or including such a single film, chromium, molybdenum, molybdenum alloy, titanium Alternatively, a multi-layered film including a conductive material having excellent contact properties with other materials, such as tantalum, may be stacked and patterned to form a horizontal gate line including the gate line 121, the gate electrode 123, and the gate pad 125. .

Next, as shown in FIGS. 10A and 10B, a three-layer film of a gate insulating layer 140 made of silicon nitride, a semiconductor layer 150 made of amorphous silicon, and a doped amorphous silicon layer 160 is sequentially stacked and a mask is formed. The semiconductor layer 150 and the ohmic contact layer 160 are formed on the gate insulating layer 140 facing the gate electrode 125 by patterning the semiconductor layer 150 and the doped amorphous silicon layer 160 by the patterning process. do.

Next, as shown in FIGS. 11A to 11B, the substrate 110 is immersed in an HF sample solution, taken out, and subjected to HF treatment of the amorphous silicon layer of the semiconductor layer 150 or the ohmic contact layer 160, and then based on silver. And depositing a conductive film by sputtering a target of a silver alloy containing 0.01-20.0 atomic% of an additive material for the silver alloy, and then patterning by a photo process using a mask to intersect the gate line 121 with a data line ( 171, a source electrode 173 connected to the data line 171 and extending to an upper portion of the gate electrode 123, and a data pad 179 and a source electrode 173 connected to one end thereof. A data line is formed, which is separated and includes a drain electrode 175 facing the source electrode 173 and a conductor pattern 177 for a storage capacitor overlapping the gate line 121 with respect to the gate electrode 123. . Here, the target of the silver alloy may be a binary or ternary system containing one or two additive materials for the alloy.

Next, the doped amorphous silicon layer pattern 160, which is not covered by the data wires 171, 173, 175, 177, and 170, is etched and separated from both sides around the gate electrode 123, while the doped amorphous silicon on both sides is etched. The semiconductor layer pattern 150 between the layers 163 and 165 is exposed. Subsequently, in order to stabilize the surface of the exposed semiconductor layer 150, it is preferable to perform oxygen plasma.

Next, as shown in FIGS. 12A and 12B, annealing is performed at a temperature range of about 200 to 500 ° C. to form the data lines 171, 173, 175, 177, and 179 of the silicon alloys 150, 163, and 165. ) A compound layer containing an additive material for silicon and silver alloy, such as a silicide layer (not shown, see FIG. 2), and the top of the exposed silicon layer 150 and the data lines 171, 173, 175, 177, and 179. A protective film 801 is formed on the substrate. In this case, the passivation layer 801 may prevent the data lines 171, 173, 175, 177, and 179 and the exposed semiconductor layer 150 from deteriorating, and the compound layer may include the silicon layers 150, 163, and 165. It has a function of improving the adhesive force between the wirings 171, 173, 175, 177, and 179.

Next, an interlayer insulating film 802 is formed by stacking an insulating material such as an organic material or silicon nitride having low dielectric constant and excellent planarization characteristics. Subsequently, the photoresist pattern is patterned by dry etching together with the gate insulating layer 140 and the passivation layer 801 by a photolithography process, thereby forming the gate pad 125, the drain electrode 175, the conductive capacitor pattern 177 for the storage capacitor, and the like. Contact holes 183, 185, 187, 189 exposing the data pad 179 are formed.

Next, as shown in FIGS. 7 and 8, the ITO or IZO film is laminated and patterned using a mask to conduct the drain electrode 175 and the conductor pattern 175 for the storage capacitor through the contact holes 185 and 187. ) And an auxiliary gate pad 92 and an auxiliary data pad 97 respectively connected to the gate pad 125 and the data pad 179 through the pixel electrode 190 and the contact holes 182 and 189, respectively. do.

As described above, the method can be applied to a manufacturing method using five masks, but the same method can be applied to a manufacturing method of a thin film transistor substrate for a liquid crystal display device using four masks. This will be described in detail with reference to the drawings.

First, the unit pixel structure of the thin film transistor substrate for a liquid crystal display device completed using the four masks according to the exemplary embodiment of the present invention will be described in detail with reference to FIGS. 13 to 15.

FIG. 13 is a layout view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention, and FIGS. 14 and 15 are XIV-XIV ′ and XV-XV ′ lines of the thin film transistor substrate illustrated in FIG. 13, respectively. A cross-sectional view taken along the line.                     

First, a gate line 121 including a gate line 121, a gate pad 125, and a gate electrode 123 including a silver-based or aluminum-based conductive film is formed on the insulating substrate 110 as in the first embodiment. have. The gate wiring includes a storage electrode 131 that is parallel to the gate line 121 on the substrate 110 and receives a voltage such as a common electrode voltage input to the common electrode of the upper plate from the outside. The storage electrode 131 overlaps with the conductive capacitor conductor 177 connected to the pixel electrode 190 to be described later to form a storage capacitor to improve charge retention of the pixel, and the pixel electrode 190 and the gate line to be described later. If the holding capacity generated by the overlap of 121 is sufficient, it may not be formed.

A gate insulating layer 140 made of silicon nitride (SiN _x ) is formed on the gate lines 121, 125, 123, and 28 to cover the gate lines 121, 125, 123, and 28.

The semiconductor patterns 152 and 157 formed of a semiconductor such as hydrogenated amorphous silicon are formed on the gate insulating layer 140, and have a high concentration of n-type impurities such as phosphorus (P) on the semiconductor patterns 152 and 157. An ohmic contact layer pattern or an intermediate layer pattern 163, 165, and 167 formed of an amorphous silicon doped with is formed.

On the ohmic contact layer patterns 163, 165, and 167, a data line made of a silver alloy is formed as in the first embodiment. The data line is a thin film transistor which is a branch of the data line 171 formed in the vertical direction, the data pad 179 connected to one end of the data line 171 to receive an image signal from the outside, and the data line 171. And a data line portion of the source electrode 173 of the source electrode 173, and separated from the data line portions 171, 179, and 173 of the source electrode 173 with respect to the gate electrode 123 or the channel portion C of the thin film transistor. Also included is a conductive capacitor pattern 177 for the storage capacitor located on the drain electrode 175 and the storage electrode 131 of the thin film transistor positioned on the opposite side. When the storage electrode 131 is not formed, the conductor pattern 177 for the storage capacitor is also not formed.

The data lines 171, 173, 175, 177, and 179 may include a conductive film made of aluminum or an aluminum alloy or chromium or molybdenum or molybdenum alloy or tantalum or titanium.

The contact layer patterns 163, 165, and 167 lower the contact resistance between the semiconductor patterns 152 and 157 below and the data lines 171, 173, 175, 177, and 179 above the data layer. (171, 173, 175, 177, 179) is exactly the same form. That is, the data line part intermediate layer pattern 163 is the same as the data line parts 171, 179 and 173, the drain electrode intermediate layer pattern 163 is the same as the drain electrode 173, and the storage capacitor intermediate layer pattern 167 is It is the same as the conductor pattern 177 for holding capacitors.

The semiconductor patterns 15 and 157 may have the same shape as the data lines 171, 173, 175, 177 and 179 and the ohmic contact layer patterns 163, 165 and 167 except for the channel portion C of the thin film transistor. Doing. Specifically, the semiconductor capacitor pattern 157 for the storage capacitor, the conductor pattern 177 for the storage capacitor, and the contact layer pattern 167 for the storage capacitor have the same shape, but the semiconductor pattern 152 for the thin film transistor has a data wiring and Slightly different from the rest of the contact layer pattern. That is, in the channel portion C of the thin film transistor, the data line portions 171, 179, and 173, in particular, the source electrode 173 and the drain electrode 175 are separated, and the data layer intermediate layer 163 and the contact layer pattern for the drain electrode. Although 165 is also separated, the semiconductor pattern 152 for thin film transistors is not disconnected here and is connected to generate a channel of the thin film transistor.

Silicon components of the silicon layers 152, 157, 163, 165, and 167 " are diffused on the data lines 171, 173, 175, 177, and 179 and the semiconductor layer 152 not covered by the data lines through annealing during the manufacturing process. A protective film 801 of silicon oxide combined with oxygen is formed to prevent the data lines 171, 173, 175, 177, and 179 or the semiconductor layer 152 from deteriorating.

In addition, a compound layer 176 formed between the contact layer patterns 163, 165, and 167 and the data lines 171, 173, 175, 177, and 179 through annealing during the manufacturing process to include at least a silicon component and an additive material for silver wiring. ) Is formed, which has a function of securing adhesion between the contact layer patterns 163, 165, and 167 and the data lines 171, 173, 175, 177, and 179.

On the passivation layer 801 and the gate insulating layer 802, an interlayer insulating layer 802 made of an organic material or silicon nitride having low dielectric constant and excellent planarization characteristics is formed.

The interlayer insulating film 802 has a protective film 801 and contact holes 185, 189, and 187 exposing the drain electrode 175, the data pad 179, and the conductive pattern 177 for the storage capacitor, and also the gate. The contact hole 185 exposing the gate pad 125 is formed together with the insulating layer 140.

A pixel electrode 190 is formed on the interlayer insulating layer 802 to receive an image signal from the thin film transistor and generate an electric field together with the electrodes of the upper plate. The pixel electrode 190 is made of a transparent conductive material such as ITO or IZO, and is physically and electrically connected to the drain electrode 175 through the contact hole 185 to receive an image signal. The pixel electrode 190 also overlaps the neighboring gate line 121 and the data line 171 to increase the aperture ratio, but may not overlap. In addition, the pixel electrode 190 is also connected to the storage capacitor conductor pattern 177 through the contact hole 187 to transmit an image signal to the conductor pattern 177. On the other hand, an auxiliary gate pad 92 and an auxiliary data pad 97 connected to the gate pad 125 and the data pad 179 through the contact holes 182 and 189, respectively, are formed. 179) and supplementing the adhesion between the external circuit device and protecting the pad, are not essential, and their application is optional.

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display device having the structure of FIGS. 13 to 15 using four masks will be described in detail with reference to FIGS. 13 to 15 and 16A to 24C. .

 First, as shown in FIGS. 16A to 16C, similar to the first embodiment, a conductive film including a conductive material of silver or silver alloy or aluminum or aluminum alloy is laminated and patterned by a photolithography process using a mask to form a gate line ( A gate wiring including 121, a gate pad 125, a gate electrode 123, and a storage electrode 131 is formed.

Next, as shown in FIGS. 17A and 17B, the gate insulating layer 140 made of silicon nitride, the semiconductor layer 150 of undoped amorphous silicon, and the intermediate layer 160 of doped amorphous silicon are formed by chemical vapor deposition. Continuous deposition is carried out at a thickness of 1,500 kPa to 5,000 kPa, 500 kPa to 2,000 kPa, and 1400 kPa to 600 kPa, respectively. Subsequently, the amorphous silicon layer 160 was subjected to HF treatment in the same manner as in the first embodiment, and the conductor layer 170 including the silver alloy was sputtered to have a thickness of 1,500 kPa to 3,000 kPa as in the first embodiment. After the deposition, the photosensitive film 210 is applied thereon with a thickness of 1 μm to 2 μm.

Thereafter, the photoresist film 210 is irradiated with light through a mask and then developed to form photoresist patterns 212 and 214 as shown in FIGS. 18B and 18C. At this time, the channel portion C of the photosensitive film patterns 212 and 214, that is, the first portion 214 positioned between the source electrode 173 and the drain electrode 175, is the data wiring portion A, that is, the data. The thickness of the wirings 171, 173, 175, 177, and 179 is smaller than that of the second part 212 positioned at the portion where the wirings 171, 173, 175, 177, and 179 are to be formed. At this time, the ratio of the thickness of the photoresist film 214 remaining in the channel portion C and the thickness of the photoresist film 212 remaining in the data wiring portion A should be different depending on the process conditions in the etching process described later. It is preferable that the thickness of the first portion 214 be 1/2 or less of the thickness of the second portion 212, for example, 4,000 kPa or less.                     

As such, there may be various methods of varying the thickness of the photoresist layer according to the position. In order to control the light transmittance in the A region, a slit or lattice-shaped pattern is mainly formed or a translucent film is used.

In this case, the line width of the pattern located between the slits or the interval between the patterns, that is, the width of the slits, is preferably smaller than the resolution of the exposure machine used for exposure, and in the case of using a translucent film, the transmittance is different in order to control the transmittance when fabricating a mask. A thin film having a thickness or a thin film may be used.

When the light is irradiated to the photosensitive film through such a mask, the polymers are completely decomposed at the part directly exposed to the light, and the polymers are not completely decomposed because the amount of light is small at the part where the slit pattern or the translucent film is formed. In the area covered by, the polymer is hardly decomposed. Subsequently, when the photoresist film is developed, only a portion where the polymer molecules are not decomposed is left, and a thin photoresist film may be left at a portion where the light is not irradiated at a portion less irradiated with light. In this case, if the exposure time is extended, all molecules are decomposed, so it should not be so.

The thin photoresist 214 may be exposed to light using a photoresist film made of a reflowable material, and then exposed and exposed to a conventional mask that is divided into a part that can completely transmit light and a part that cannot completely transmit light. It can also be formed by letting a part of the photosensitive film flow to the part which does not remain by making it low.                     

Subsequently, etching is performed on the photoresist pattern 214 and the underlying layers, that is, the conductor layer 170, the intermediate layer 160, and the semiconductor layer 150. In this case, the data line and the layers under the data line remain in the data wiring portion A, only the semiconductor layer should remain in the channel portion C, and the three layers 170, 160, 150 is removed to expose the gate insulating layer 140.

First, as shown in FIGS. 19A and 19B, the exposed conductor layer 170 of the other portion B is removed to expose the lower intermediate layer 160. In this process, both a dry etching method and a wet etching method may be used. In this case, the conductor layer 170 may be etched and the photoresist patterns 212 and 214 may be etched under almost no etching conditions. However, in the case of dry etching, since it is difficult to find a condition in which only the conductor layer 170 is etched and the photoresist patterns 212 and 214 are not etched, the photoresist patterns 212 and 214 may be etched together. In this case, the thickness of the first portion 214 is thicker than that of the wet etching so that the first portion 214 is removed in this process so that the lower conductive layer 170 is not exposed.

In this way, as shown in Figs. 19A and 19B, only the conductor layers of the channel portion C and the data wiring portion B, that is, the conductor pattern 178 for the source / drain and the conductor pattern 177 for the storage capacitor, are present. All of the conductor layer 170 of the remaining portion B is removed, revealing the underlying intermediate layer 50. The remaining conductor patterns 178 and 177 are the same as the data wires 171, 177, 173, 175 and 179 except that the source and drain electrodes 173 and 175 are connected without being separated. In addition, when dry etching is used, the photoresist patterns 212 and 214 are also etched to a certain thickness.

Then, as shown in FIGS. 20A and 20B, the exposed intermediate layer 160 of the other portion B and the semiconductor layer 150 thereunder are simultaneously removed by the dry etching method together with the first portion 214 of the photoresist film. do. At this time, etching is performed under the condition that the photoresist patterns 212 and 214 and the intermediate layer 160 and the semiconductor layer 150 (the semiconductor layer and the intermediate layer have almost no etching selectivity) are simultaneously etched and the gate insulating layer 140 is not etched. In particular, it is preferable to etch under conditions in which the etching ratios of the photoresist patterns 212 and 214 and the semiconductor layer 150 are almost the same. For example, by using a mixed gas of SF ₆ and HCl or a mixed gas of SF ₆ and O ₂ , the two films can be etched to almost the same thickness. When the etch ratios of the photoresist patterns 212 and 214 and the semiconductor layer 150 are the same, the thickness of the first portion 214 should be equal to or smaller than the sum of the thicknesses of the semiconductor layer 150 and the intermediate layer 160.

This removes the first portion 214 of the channel portion C, revealing the source / drain conductor pattern 178, as shown in FIGS. 20A and 20B, and the intermediate layer 160 of the other portion B. The semiconductor layer 150 is removed to expose the gate insulating layer 140 under the semiconductor layer 150. On the other hand, since the second portion 212 of the data line portion A is also etched, the thickness becomes thin. In this step, the semiconductor patterns 152 and 157 are completed. Reference numerals 168 and 167 denote intermediate layer patterns under the source / drain conductor patterns 178 and intermediate layer patterns under the storage capacitor conductor patterns 177, respectively.                     

Subsequently, ashing of the photoresist film remaining on the surface of the source / drain conductor pattern 178 of the channel part C is removed.

Next, as shown in FIGS. 21A and 21B, the source / drain conductor pattern 178 of the channel portion C and the source / drain interlayer pattern 168 thereunder are etched and removed. In this case, the etching may be performed only by dry etching with respect to both the source / drain conductor pattern 178 and the intermediate layer pattern 168. The etching may be performed by wet etching with respect to the source / drain conductor pattern 178. 168) may be performed by dry etching. In the former case, it is preferable to perform etching under a condition in which the etching selectivity of the source / drain conductor pattern 178 and the interlayer pattern 168 is large, which is difficult to find the etching end point when the etching selectivity is not large. This is because it is not easy to adjust the thickness of the semiconductor pattern 1522 remaining in Fig. 2). Examples of the etching gas used to etch the intermediate layer pattern 168 and the semiconductor pattern 152 include the aforementioned mixed gas of CF ₄ and HCl or mixed gas of CF ₄ and O ₂ , and CF ₄ and O _{Using 2} may leave the semiconductor pattern 152 with a uniform thickness. At this time, as shown in FIG. 21B, a portion of the semiconductor pattern 152 may be removed to reduce the thickness, and the second portion 212 of the photoresist pattern may also be etched to a certain thickness at this time. At this time, the etching must be performed under the condition that the gate insulating layer 140 is not etched, and the photosensitive layer is not exposed so that the second portion 212 is etched so that the data lines 171, 173, 175, 177, and 179 below the substrate are not exposed. It is a matter of course that the pattern is thick.

In this way, the source electrode 173 and the drain electrode 175 are separated to complete the data lines 171, 173, 175, 177, and 179 and the contact layer patterns 163, 165, and 167 thereunder.

Finally, the photosensitive film second portion 212 remaining in the data wiring portion A is removed. However, the removal of the second portion 212 may be performed after removing the conductor pattern 178 for the channel portion C source / drain and before removing the intermediate layer pattern 168 thereunder.

As mentioned earlier, wet and dry etching can be alternately used or only dry etching can be used. In the latter case, since only one type of etching is used, the process is relatively easy, but it is difficult to find a suitable etching condition. On the other hand, in the former case, the etching conditions are relatively easy to find, but the process is more cumbersome than the latter.

Then, as shown in FIGS. 22A and 22B, annealing is performed in the temperature range of about 200-600 ° C. as in the first embodiment, so that the data lines 171, 173, 175, 177, and 179 and the silicon layer 163 are formed. A compound layer 176 including at least a silicon component and an additive material for a silver alloy forming the data lines 171, 173, 175, 177, and 179 is formed between 165 and 167, and the data lines 171, 173, 175, A protective film 801 made of silicon oxide is formed on the upper portions 177 and 179.

The annealing process may be performed immediately after stacking the silver alloy data wiring conductor layer 60 and may be performed after the data wirings 171, 173, 175, 177, and 179 are completed.

After forming the data wirings 171, 173, 175, 177, and 179 in this manner, as shown in FIGS. 23A to 23C, an organic insulating material, silicon nitride, or the like is deposited to form an interlayer insulating film 802, and a mask. The interlayer insulating layer 802 is etched together with the passivation layer 801 and the gate insulating layer 140 using the drain electrode 175, the gate pad 125, the data pad 179, and the conductive pattern 177 for the storage capacitor. Contact holes 185, 182, 189, and 187, respectively, to form the contact holes.

Finally, as shown in FIGS. 13 to 15, 400 Å to 500 Å thick IZO or ITO is deposited and etched using a mask to be connected to the drain electrode 175 and the conductor pattern 177 for the storage capacitor. An auxiliary gate pad 92 connected to the pixel electrode 190, a gate pad 125, and an auxiliary data pad 97 connected to the data pad 179 are formed.

In the second embodiment of the present invention, the data wirings 171, 173, 175, 177, and 179, the contact layer patterns 163, 165, 167, and the semiconductor patterns 152 underneath the data wirings 171, 173, 175, 177, and 179, as well as the effects of the first embodiment. , 157 may be formed using one mask, and the source electrode 173 and the drain electrode 175 may be separated in this process to simplify the manufacturing process.

In addition, in the manufacturing method of the thin film transistor array substrate according to the first and second embodiments of the present invention, the annealing process may be replaced by a preheating process for stacking the interlayer insulating layer 802 without any additional process.

In order to form the compound layer 176 more effectively, an insulating film covering the data lines 171, 173, 175, 177, and 179 may be formed as shown in FIG. 2, and then an annealing process may be performed.

As described above, before the lamination of the conductive material for wiring, the silicon layer is HF-treated or the conductive film for the silver alloy is laminated on the silicon layer and then annealed to form a protective film on the silver alloy thin film. By forming the compound layer between the thin film of the alloy and the silicon layer, it is possible to improve the adhesion between the thin film of the silver or silver alloy and the silicon layer and to prevent the wiring from deteriorating. As a result, a silver alloy containing silver having the lowest non-constant can be used as a wiring, thereby minimizing signal delay, and realizing a large-area and high-resolution liquid crystal display device.

Claims (24)

A compound layer formed on the silicon layer and formed between the thin film made of a silver alloy and the thin film and the silicon layer, the compound layer including at least a silicon component of the silicon layer and an additive material for the silver alloy of the silver alloy; Wiring for a display device included. In claim 1, The silver alloy is based on silver (Ag), and is selected from V, W, Cr, Cu, Fe, Li, Mn, Mo, Nb, Ni, Zr, Co, or Ti in the range of 0.01-20 atomic%. And one or two additive materials for the silver alloy. In claim 1, And a protective film formed on the thin film, the protective film made of silicon oxide containing a silicon component diffused from the silicon layer. Laminating a thin film of silver alloy on top of the silicon layer, and Forming a protective film made of silicon oxide including a silicon component diffused from the silicon layer on the thin film; Method of manufacturing a wiring for a display device comprising a. Laminating a thin film of silver alloy on top of the silicon layer, and Forming a compound layer comprising at least a silicon component of the silicon layer and an additive material for silver alloy of the silver alloy between the silicon layer and the thin film Method of manufacturing a wiring for a display device comprising a. In claim 4, And the protective film forming step is performed through annealing. The method of claim 4 or 5,  The thin film stacking step is based on silver (Ag), and V, W, Cr, Cu, Fe, Li, Mn, Mo, Nb, Ni, Zr, Co, or Ti in an atomic percentage of 0.01-20 atomic%. The manufacturing method of the wiring for display apparatuses which sputter | stack and laminate the target containing one or two of the said additive materials for silver alloys of this. In claim 6, And the annealing step is performed at a temperature in a range of 200 to 500 ° C. In claim 5, And forming an insulating film on the thin film before forming the compound layer. Stacking and patterning a conductive material for a gate wiring on the substrate to form a gate wiring including a gate line and a gate electrode; Stacking a gate insulating film on the substrate; Forming a semiconductor layer of silicon on the gate insulating film, Forming a data line including a data line, a source electrode, and a drain electrode as a thin film of silver alloy on the semiconductor layer; Forming a protective film made of silicon oxide including silicon diffused from the semiconductor layer on the data line; Method of manufacturing a thin film transistor array substrate comprising a. Stacking and patterning a conductive material for a gate wiring on the substrate to form a gate wiring including a gate line and a gate electrode; Stacking a gate insulating film on the substrate; Forming a semiconductor layer of silicon on the gate insulating film, Forming a data line including a data line, a source electrode and a drain electrode as a thin film of silver alloy on the semiconductor layer; Forming a compound layer comprising at least a silicon component of the semiconductor layer and an additive material for silver alloy of the thin film between the semiconductor layer and the data line Method of manufacturing a thin film transistor array substrate comprising a. In claim 10, The protective film forming step is a method of manufacturing a thin film transistor array substrate made through annealing. The method of claim 10 or 11,  The silver alloy is based on silver (Ag), and is selected from V, W, Cr, Cu, Fe, Li, Mn, Mo, Nb, Ni, Zr, Co, or Ti in an atomic percentage of 0.01-20 atomic%. A method for manufacturing a thin film transistor array substrate comprising sputtering and stacking a target containing one or two of the additive materials for silver alloy. In claim 12, The annealing step is a method of manufacturing a thin film transistor array substrate carried out in a temperature range of 200-500 ℃. In claim 11, And forming an insulating film on the thin film before forming the compound layer. The method of claim 10 or 11, HF processing the semiconductor layer further comprising the method of manufacturing a thin film transistor array substrate. A gate wiring formed on the glass substrate and including a gate line and a gate electrode connected to the gate line; A gate insulating film covering the gate wiring, A semiconductor layer of silicon formed on the gate insulating film, A conductive material of a silver alloy is formed on the gate insulating layer or the semiconductor layer, and is positioned opposite to the data electrode, the source electrode connected to the data line and adjacent to the gate electrode and the source electrode. A data wiring including a drain electrode, A compound layer formed between the semiconductor layer and the data wiring and including at least a silicon component of the semiconductor layer and an additive material for silver alloy of the silver alloy. Thin film transistor array substrate comprising a. The method of claim 17, The silver alloy is based on silver (Ag), and is selected from V, W, Cr, Cu, Fe, Li, Mn, Mo, Nb, Ni, Zr, Co, or Ti in the range of 0.01-20 atomic%. The thin film transistor array substrate comprising one or two of the additive material for the silver alloy. The method of claim 17, And a passivation layer formed on the data line and comprising a silicon oxide containing a silicon component diffused from the silicon layer. The thin film transistor array substrate of claim 17, further comprising a pixel electrode electrically connected to the drain electrode. In claim 5, And forming the mixture layer through annealing. The method of claim 21, And the annealing step is performed at a temperature in a range of 200 to 500 ° C. In claim 11, The compound layer forming forming step is a method of manufacturing a thin film transistor array substrate made through annealing. The method of claim 23, The annealing step is a method of manufacturing a thin film transistor array substrate carried out in a temperature range of 200-500 ℃.

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