CN106449662B - Array substrate and display device - Google Patents
Array substrate and display device Download PDFInfo
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- CN106449662B CN106449662B CN201611022079.3A CN201611022079A CN106449662B CN 106449662 B CN106449662 B CN 106449662B CN 201611022079 A CN201611022079 A CN 201611022079A CN 106449662 B CN106449662 B CN 106449662B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
Abstract
The present invention provides a kind of array substrates, including grid layer, the first metal layer and second metal layer.The grid layer includes gate line, and the first metal layer includes the first metal segments of multistage, and it is in parallel with the gate line that first metal segments are arranged.The second metal layer includes the second metal segments of multistage, and setting second metal segments are in parallel with the gate line, the projection overlapping of first metal segments, second metal segments and the gate line on array substrate thickness direction.The present invention also provides a kind of display devices.The present invention is by reducing the overall electrical resistance of gate line to gate line in parallel first metal segments and the second metal segments parallel with it, to reduce because gate line overall electrical resistance it is uneven caused by RC retardation ratio, improve gate line display device film flicker problem of non-uniform as caused by RC retardation ratio.
Description
Technical field
The present invention relates to liquid crystal display device manufacturing fields, and in particular to a kind of array substrate and with the array substrate
Display device.
Background technique
With the rapid development of display technology, requirement of the people for display device picture quality is also continuously improved, especially
It is higher and higher for display device film flicker (Flicker) uniformity requirement.
Resistance capacitance (RC) delay is to influence one of the principal element of display device film flicker uniformity.In display device
The gate line of thin film transistor (TFT) (TFT) array substrate is influenced by RC retardation ratio, will be generated electric signal delay, is in turn resulted in
The practical driving voltage of certain positions and ideal driving voltage are inconsistent in display device, i.e. at a time certain in display device
A little position picture intrinsic brilliances and desired level are inconsistent, so as to cause the situation that display device film flicker uniformity is poor,
This drastically influences the image quality of display device and the user experience of people.
The RC retardation ratio influence degree resistance homogeneity integrated therewith of gate line has very big relationship.In general, grid
Overall electrical resistance on the signal wire of pole is smaller, then its resistance homogeneity is better, and gate line is smaller by RC retardation ratio influence degree.?
The length of gate line, thickness and resistivity it is constant in the case where, in order to reduce the overall electrical resistance of gate line, Ke Yizeng
Add the width of gate line or increases gate line in grid layer and make its parallel connection.However increase the width of gate line
Meeting is spent so that effective glazed area is reduced in display area, so as to cause display brightness reduction；Increase parallel connection in grid layer
Gate line can make the distance between gate line smaller, so that the coupled capacitor between gate line increases, from
And aggravate RC retardation ratio influence degree.Both the above method can all generate more serious negative influence, not be suitable for improving display
The film flicker non-uniform phenomenon of device.Therefore, especially for the research for the film flicker problem of non-uniform for improving display device
It is necessary.
Summary of the invention
For above problem, the object of the present invention is to provide a kind of array substrate and display devices, by non-grid
Increase the metal segments in parallel with gate line in layer to reduce the overall electrical resistance of gate line, to improve gate line
On RC retardation ratio, improve the non-uniform problem of display device film flicker.
In order to solve the problems, such as background technique, in a first aspect, the embodiment of the invention provides a kind of array substrate,
The array substrate include the grid layer being stacked, the first metal layer and be located at the grid layer and the first metal layer it
Between the first insulating layer, first insulating layer is for making the grid layer and the first metal layer insulate, the grid layer
Including gate line, the first metal layer includes the first metal wire, and the gate line and first metal wire exist
Projection intersection on the array substrate thickness direction, the first metal layer further includes the first metal segments of multistage, described in every section
First metal segments are between two adjacent first metal wires, and the both ends of first metal segments and first gold medal
Belong to line and form open circuit, the both ends of first metal segments are electrically connected with the gate line.
Further, the array substrate further includes multiple first through hole, and one end of the first through hole is connected to described
One end of first metal segments, the other end connect the gate line, so that first metal segments and the gate line
It is in parallel.
Preferably, the length and width of every first metal segments is identical.
Preferably, the width with the gate line of first metal segments of same size, first metal segments
It coincides with projection of the gate line on the array substrate thickness direction.
The first embodiment with reference to first aspect, in the second embodiment, the array substrate further includes position
In on the first metal layer and the second insulating layer that is cascading, transparent electrode layer and second metal layer, described second absolutely
For edge layer for the insulate the first metal layer and the transparent electrode layer, the second metal layer includes the second metal wire, described
Second metal wire overlaps with projection of first metal wire on the array substrate thickness direction, the second metal layer
It further include the second metal segments of multistage, every section of second metal segments are between two adjacent second metal wires, and described
The both ends of two metal segments and second metal wire form open circuit, the both ends of second metal segments and gate line electricity
Connection.
The first embodiment with reference to first aspect, in the third embodiment, the array substrate further includes being located at
On the first metal layer and the second insulating layer that is cascading, second metal layer and transparent electrode layer, second insulation
For layer for insulating the first metal layer and the second metal layer, the second metal layer includes the second metal wire, and described the
Two metal wires overlap with projection of first metal wire on the array substrate thickness direction, and the second metal layer is also
Including the second metal segments of multistage, every section of second metal segments are between two adjacent second metal wires, and described second
The both ends of metal segments and second metal wire form open circuit, and both ends and the gate line of second metal segments are electrically connected
It connects.
Further, the array substrate further includes multiple second through-holes, and second through-hole one end is connected to described
One end of two metal segments, the other end connect the gate line, so that second metal segments and the gate line are simultaneously
Connection.
Preferably, the length of second metal segments is identical as the first metal segment length, second metal segments with
Projection of first metal segments on the array substrate thickness direction overlaps, described in one end connection of second through-hole
One end of second metal segments, by one end of first metal segments, the other end connects the gate line, so that described the
Two metal segments, first metal segments are in parallel with the gate line.
Preferably, second metal segments, first metal segments are of same size and described with the gate line
Second metal segments, first metal segments are mutually be overlapped with projection of the gate line on the array substrate thickness direction
It closes.
Second aspect, the embodiment of the invention provides a kind of display devices, including above-described array substrate.
The embodiment of the present invention is directed to gate line display device film flicker problem of non-uniform as caused by RC retardation ratio,
The overall electrical resistance of gate line is reduced by the way that metal segments are arranged in non-grid layer, to improve the RC on gate line
Delay, such design will not additionally increase the size of display device, and metal segments in parallel are opposite with the spacing of gate line
Larger, the coupled capacitor of generation is smaller, not will cause aggravation RC retardation ratio.In addition, above-mentioned metal segments are arranged in the embodiment of the present invention
It is overlapped with projection of the gate line on array substrate thickness direction, then the glazed area of display area and display device is bright
Degree not will receive the influence of metal segments in parallel.The embodiment of the present invention combines the above both sides design, is not influencing display area
Glazed area and in the case where not changing display device size, reduce the overall electrical resistance of gate line, and then improve
The RC retardation ratio of gate line influences, and improves the non-uniform problem of film flicker of display device.
Detailed description of the invention
In order to illustrate the technical solution of the embodiments of the present invention more clearly, below will be to needed in the embodiment attached
Figure is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for this field
For those of ordinary skill, without creative efforts, it is also possible to obtain other drawings based on these drawings.
Fig. 1 is a kind of array substrate cross section structure schematic diagram provided in an embodiment of the present invention.
Fig. 2 is the planar structure schematic diagram of the first metal layer in Fig. 1.
Fig. 3 is the display device cross section structure schematic diagram that the first embodiment of the invention provides.
Fig. 4 is the display device cross section structure schematic diagram that second of embodiment of the invention provides.
Fig. 5 is a kind of array substrate cross section structure schematic diagram provided in an embodiment of the present invention.
Fig. 6 is the planar structure schematic diagram of second metal layer in Fig. 5.
Fig. 7 is the display device cross section structure schematic diagram that the third embodiment of the invention provides.
Fig. 8 is a kind of array substrate cross section structure schematic diagram provided in an embodiment of the present invention.
Fig. 9 is the cross section structure schematic diagram for the display device that the 4th kind of embodiment of the invention provides.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, carries out to the technical solution of the embodiment of the present invention clear, complete
Ground description.
Referring to Fig. 1, Fig. 1 is a kind of array substrate cross section structure schematic diagram provided in an embodiment of the present invention.A kind of array
Substrate 10, substrate 101, grid layer 102, the first metal layer 104 and the first insulating layer 103 including lamination setting.The substrate
101 are used to support and protect the grid layer 102.First insulating layer 103 is located at the grid 102 and the first metal layer
Between 104, for making the grid layer 102 and the first metal layer 104 insulate.The grid layer 102 includes a plurality of grid
Signal wire 1021, the gate line 1021 can be parallelly distribute on.The first metal layer 104 includes a plurality of first metal
Line 1041, first metal wire 1041 can be parallelly distribute on.The gate line 1021 and first metal wire
The 1041 projection intersection on 10 thickness direction of array substrate, further, the gate line 1021 and described the
Projection of one metal wire 1041 on 10 thickness direction of array substrate can be perpendicular.
Referring to Fig. 2, Fig. 2 is the planar structure schematic diagram of the first metal layer in Fig. 1.The first metal layer 104 also wraps
Include the first metal segments of multistage 1042, every section of first metal segments 1042 be located at two adjacent first metal wires 1041 it
Between, and the both ends of first metal segments 1042 and first metal wire 1041 form open circuit.The first metal segments of multistage 1042
It can be in array distribution, multiple row is divided by a plurality of first metal wire 1041.In one embodiment, first gold medal
The direction for belonging to section 1042 can be perpendicular with the direction of first metal wire 1041, and first metal segments 1042 and the grid
Pole signal wire 1021 is parallel, i.e., described first metal segments 1042 are with the gate line 1021 in 10 thickness of array substrate
Projection on direction overlaps.
The both ends of first metal segments 1042 are electrically connected with the gate line 1021.In a kind of embodiment, ask
Refering to fig. 1, the array substrate 10 further includes multiple first through hole 113, and the first through hole 113 can be array distribution,
One end of the first through hole 113 is connected to one end of first metal segments 1042, passes through first insulating layer 103, separately
One end connects the gate line 1021.Conductive materials can be filled in first through hole 113, so that first metal segments 1042
It is electrically connected with the gate line 1021, is specially connected in parallel.In other embodiments, can also by metal wire or
Other modes realize that first metal segments 1042 are in parallel with the gate line 1021.
The embodiment of the present invention is by reducing the whole of the gate line to the gate line the first metal segments in parallel
Bulk resistor.First metal segments and the first through hole can be array distribution, on the one hand with the vacant sky in the first metal layer
Between it is corresponding；On the other hand metal segments and every gate line can be locked in a tie for first simultaneously in the same position of the gate line
First metal segment number of connection is identical, can reduce the resistance difference of every gate line in this way, in entire grid layer
Resistance homogeneity it is more preferable so that gate line by RC retardation ratio effect reduce.
Preferably, the length and width of every first metal segments 1042 can be identical, can reduce by every institute in this way
The resistance difference for the first metal segments 1042 stated, so that it is guaranteed that the resistance difference of the gate line after every first metal segments of parallel connection
Different reduction, the resistance homogeneity in entire grid layer is more preferable, so that gate line is subtracted by RC retardation ratio effect
It is few.
Preferably, the width of first metal segments 1042 can be identical with the width of the gate line 1021, institute
It states the first metal segments to coincide with projection of the gate line on the array substrate thickness direction, it is possible to reduce described
Influence of first metal segments to display area effective glazed area and array substrate aperture opening ratio.
In a kind of embodiment, the array substrate can be thin film transistor (TFT) (TFT) array substrate, the first metal layer
For source layer, first metal wire is source signal line.Embodiment of the present invention makes full use of the tft array substrate source electrode
Spare space in layer arranges first metal segments, without additionally increasing metal layer or changing the big of the tft array substrate
Small and thickness, the miniaturization suitable for tft array substrate；First metal segments and the gate line are in the array simultaneously
Projection in substrate thickness direction overlaps, and reduces first metal segments to the effective glazed area in display area and TFT
The influence of array substrate aperture opening ratio；By the first metal segments in parallel on every gate line, the whole of gate line is reduced
Bulk resistor, so as to improve the RC retardation ratio on gate line.
The embodiment of the invention provides a kind of display devices, including the array substrate 10 in above embodiment.By with
A kind of display device provided by the invention is specifically described in lower embodiment.
The first embodiment:
Referring to Fig. 3, Fig. 3 is a kind of display device cross section structure schematic diagram that the first embodiment of the invention provides.Institute
Stating display device can be Thin Film Transistor-LCD (TFT-LCD), including above-mentioned array substrate 10.First gold medal
Belonging to layer 104 is source layer, and first metal wire 1041 is source signal line.The source signal line 1041 is believed with the grid
Number projection of line 1021 on the substrate is orthogonal.The grid layer 102 includes the thin-film transistor gate of array distribution (in figure
It is not shown) and a plurality of gate line 1021, the gate line 1021 is connected to the grid of row arrangement, one end and drives
Dynamic circuit connection, for controlling the pixel voltage of display device.The gate line can be Al alloy-layer or Al alloy with
The laminations such as MoNb, Ti.On the substrate after splash-proofing sputtering metal layer, the gate line is obtained by techniques such as photoetching, etchings
Wiring.In order to allow the grid layer 102 and the source layer 104 to insulate, after completing grid layer, pass through chemical vapor deposition
(CVD) technique coats layer of sin x insulating layer, as the first insulating layer 103, for making grid layer and source layer insulate.
Thin film transistor (TFT) source electrode (not shown) and a plurality of source signal line of the source layer 104 including array arrangement
1041, the source signal line 1041 is electrically connected with the source electrode of column arrangement.The manufacturing process of the source signal line can be with
It is identical as the manufacturing process of the gate line.The source signal line can be Mo or Cr single layer structure, be also possible to Mo/
Al/Mo or Ti/Al/Ti three-layer metal laminated construction.
Also referring to Fig. 1 and Fig. 3, in a display device, the array substrate 10 further includes being located at the first metal layer 104
Upper and successively lamination setting second insulating layer 105, transparent electrode layer 106, third insulating layer 107, pixel electrode layer 110.Institute
It states second insulating layer 105 to be arranged between the tft array substrate 10 and transparent electrode layer 106, for making the tft array base
It insulate between plate 10 and transparent electrode layer 106.The setting of third insulating layer 107 is in the transparent electrode layer 106 and pixel electricity
Between pole layer 110, insulate between the transparent electrode layer 106 and pixel electrode layer 110 for making.The display device further includes
Layer of liquid crystal molecule 111, color membrane substrates 112 in array substrate.The layer of liquid crystal molecule 111 can control by torsion and penetrate
The light luminance of display screen out.Trichromatic light quantity is adjusted in conjunction with layer of liquid crystal molecule 111 in the color membrane substrates 112, obtains institute
The colored display needed.
The embodiment of the present invention makes first by the way that the first metal segments of multistage are arranged between the source signal line of source layer
Metal segments are in parallel with gate line, achieve the effect that reduce gate line overall electrical resistance, to reduce gate line
On RC retardation ratio, improve Thin Film Transistor-LCD (TFT-LCD) in gate line drawn as caused by RC retardation ratio
Face flashes non-uniform problem.
Second of embodiment:
Referring to Fig. 4, Fig. 4 is a kind of cross section structure schematic diagram for display device that second of embodiment of the invention provides.
Display device can be In-cell touch panel, and compared with traditional TFT-LCD, In-cell touch panel is in transparent electrode layer 106 and picture
Second metal layer 108 and the 4th insulating layer 109 are increased between plain electrode layer 110.The second metal layer 108 includes the second gold medal
Belong to line 1081, for touch screen driving and being electrically connected between touch sensor module.Transparent electrode layer 106 can be divided into multiple
Independent touch sensor module.The second metal layer 108 is to touch line layer, and the second metal wire 1081 is touch signal line.
In order to not influence display area effective light transmission area, the touch signal line 1081 in the touch line layer 108 is set as and source
Pole signal wire 1041 is parallel.The display device further includes layer of liquid crystal molecule 111, color membrane substrates 112 in array substrate.
The embodiment of the present invention makes first by the way that the first metal segments of multistage are arranged between the source signal line of source layer
Metal segments are in parallel with gate line, achieve the effect that reduce gate line overall electrical resistance, to reduce gate line
On RC retardation ratio, the gate line film flicker as caused by RC retardation ratio improved in In-cell touch panel non-uniform asks
Topic.
In order to further improve film flicker problem of non-uniform, for In-cell touch panel, proposition of the embodiment of the present invention can
By the way that the second metal segments of multistage are arranged in second metal layer, and it is in parallel with gate line, to be further reduced grid letter
Number line overall electrical resistance, to reduce the RC retardation ratio on gate line.It is specifically shown in embodiment.
Referring to Fig. 5, Fig. 5 is array substrate cross section structure schematic diagram provided in an embodiment of the present invention.A kind of embodiment
In, array substrate 10 further include be located at the first metal layer 104 on and the second insulating layer 105 that is cascading, transparent electricity
Pole layer 106 and second metal layer 108.The second insulating layer 105 is for making the first metal layer 104 and the transparent electrode
Layer 106 insulate.Third insulating layer 107 is equipped between the second metal layer 108 and the transparent electrode layer 106.Described second
Metal layer 108 includes the second metal wire 1081, and second metal wire 1081 is with first metal wire 1041 in the array
Projection in substrate thickness direction overlaps.The second metal layer 108 further includes the second metal segments of multistage 1082, and every section second
Metal segments 1082 are between two adjacent second metal wires 1081, and the both ends of second metal segments 1082 and institute
It states the second metal wire 1081 and forms open circuit, the both ends of second metal segments 1082 are electrically connected with the gate line 1021.
Fig. 6 is the planar structure schematic diagram of second metal layer in Fig. 5.The array substrate further includes multiple second through-holes
114, second through-hole 114 can be array distribution, and one end of second through-hole 114 is connected to second metal segments
1082 one end sequentially passes through the third insulating layer 107, transparency conducting layer 106, second insulating layer 105, source layer 104,
One insulating layer 103, the other end connect the gate line 1021.Conductive materials can be filled in second through-hole 114, so that described
Second metal segments 1082 are in parallel with the gate line 1021.In other embodiments, can also by metal wire or its
His mode realizes that second metal segments 1082 are in parallel with the gate line 1021.
The embodiment of the invention also provides a kind of display devices, including the array substrate 10 in above-mentioned embodiment.It is logical
Following embodiment is crossed a kind of display device provided by the invention is specifically described.
The third embodiment:
Fig. 7 is the display device cross section structure schematic diagram that the third embodiment of the invention provides.Also referring to Fig. 5 and figure
7, display device can be In-cell touch panel, further include being located at the second gold medal including the array substrate 10 in above-mentioned embodiment
Belong to the 4th insulating layer 109 and pixel electrode layer 110 on layer 108.4th insulating layer 109 is for making the pixel electrode layer
It insulate between 110 and the second metal layer 108.The second metal layer 108 includes the second metal wire 1081, is driven for touch screen
Dynamic being electrically connected between touch sensor module.Transparent electrode layer 106 can be divided into multiple independent touch sensor moulds
Block.The second metal layer 108 is to touch line layer, and the second metal wire 1081 is touch signal line.In order to not influence display area
Effective light transmission area, the touch signal line 1081 in the touch line layer 108 are set as parallel with source signal line 1041.Institute
Stating display device further includes layer of liquid crystal molecule 111, color membrane substrates 112 in array substrate.
The embodiment of the present invention passes through between the touch signal line for touching line layer and between the source signal line of source layer points
Not She Zhi the first metal segments of the second metal segments of multistage and multistage, and make the second metal segments, the first metal segments and gate line
It is in parallel, the spare space in display device can be made full use of, gate line overall electrical resistance is further reduced, to reduce
RC retardation ratio on gate line improves the sudden strain of a muscle of the picture as caused by RC retardation ratio of the gate line in the In-cell touch panel
Sparkle non-uniform problem.
Second metal segments are set in array substrate for convenience, and reduce the second metal segments and the second through-hole for other
The influence of layer, the embodiment of the present invention have carried out further improvement for the structure of array substrate, have been detailed in following implementation.
Fig. 8 is a kind of array substrate cross section structure schematic diagram provided in an embodiment of the present invention.In a kind of embodiment, in order to
Reduce influence of second through-hole for transparency conducting layer, the application propose by array substrate second metal layer 108 with it is transparent
106 transposition of electrode layer.Array base-plate structure after changing is as shown in figure 8, array substrate includes being located at the first metal layer
On 104 and the second insulating layer 105 that is cascading, second metal layer 108, third insulating layer 107 and transparent electrode layer 106.
The second insulating layer 105 is for making the first metal layer 104 and the second metal layer 108 insulate, third insulating layer 107
For making to insulate between the second metal layer 108 and the transparent electrode layer 106.The second metal layer 108 includes second
Metal wire 1081, second metal wire 1081 and throwing of first metal wire 1041 on the array substrate thickness direction
Shade overlapping, second metal wire 1081 are electrically connected to the transparent electrode layer 106.
The second metal layer 108 further includes the second metal segments of multistage 1082, and every section of second metal segments 1082 are located at
Between second metal wire 1081 of adjacent two, and the both ends of second metal segments 1082 and second metal wire
1081 form open circuit.The second metal segments of multistage 1082 can be in array distribution, be divided by a plurality of second metal wire 1081
Multiple row.In one embodiment, 1082 direction of the second metal segments can be vertical with 1081 direction of the second metal wire, and
Second metal segments 1082 are parallel with the gate line 1021, second metal segments 1082 and the gate line
1021 projection on the array substrate thickness direction overlaps.The both ends of second metal segments 1082 and the grid are believed
Number line 1021 is electrically connected.
The array substrate further includes multiple second through-holes 114, and second through-hole 114 can be array distribution, institute
The one end for stating the second through-hole 114 is connected to one end of second metal segments 1082, passes through second insulating layer 105, source layer
104, the first insulating layer 103, the other end connect the gate line 1021.Conductive materials can be filled in second through-hole 114, make
It is in parallel with the gate line 1021 to obtain second metal segments 1082.In other embodiments, metal wire can also be passed through
Or other modes realize that second metal segments 1082 are in parallel with the gate line 1021.
Preferably, the length and width of every second metal segments 1082 can be identical.Further, second gold medal
Belong to section 1082 length can be identical with the length of first metal segments 1042, and second metal segments 1082 with it is described
Projection of first metal segments 1042 on the array substrate thickness direction overlaps, one end connection of second through-hole 114
One end of second metal segments 1082, by one end of first metal segments 1042, the other end connects the grid signal
Line 1021, so that second metal segments 1082, first metal segments 1042 are in parallel with the gate line 1021.In this way
It can reduce metal segments resistance difference, so that it is guaranteed that the resistance difference of the gate line after every metal segments in parallel reduces, it is whole
Resistance homogeneity in a grid layer is more preferable, so that gate line is reduced by RC retardation ratio effect.
Further, second metal segments, first metal segments can be identical with the width of the gate line,
It can promote first metal segments, the second metal segments and the gate line on the array substrate thickness direction in this way
Projection coincide, to reduce first metal segments, the second metal segments to the effective glazed area in display area and battle array
The influence of column base openings rate.
The embodiment of the invention also provides a kind of display devices, including the array substrate 10 in above-mentioned embodiment.It is logical
Following embodiment is crossed a kind of display device provided by the invention is specifically described.
4th kind of embodiment:
Fig. 9 is the cross section structure schematic diagram of display device provided in an embodiment of the present invention.Also referring to Fig. 8 and Fig. 9, show
Showing device can be In-cell touch panel, further include being located at transparent electrode layer including the array substrate 10 in above-mentioned embodiment
The 4th insulating layer 109 and pixel electrode layer 110 on 106.4th insulating layer 109 is for making the pixel electrode layer 110
It insulate between the second metal layer 108.The second metal layer 108 includes the second metal wire 1081, is driven for touch screen
Being electrically connected between touch sensor module.Transparent electrode layer 106 can be divided into multiple independent touch sensor modules.
The second metal layer 108 is to touch line layer, and the second metal wire 1081 is touch signal line.It is effective in order to not influence display area
Glazed area, the touch signal line 1081 in the touch line layer 108 are set as parallel with source signal line 1041.It is described aobvious
Showing device further includes layer of liquid crystal molecule 111, color membrane substrates 112 in array substrate.
In a kind of embodiment, settable first metal segments, the second metal segments, the first through hole and described second
Through-hole is array distribution, on the one hand corresponding with the spare space in array substrate source layer and touch line layer；It on the other hand can
In the same position of gate line metal wire arranged side by side, and the quantity of first metal segments and the second metal segments arranged side by side
It is identical, the resistance difference of every gate line can be reduced, the resistance homogeneity in entire grid layer is more preferable, so that
Gate line is reduced by RC retardation ratio effect.
The embodiment of the present invention passes through between the touch signal line for touching line layer and between the source signal line of source layer points
Second metal segments and the first metal segments are not set, so that the second metal segments, the first metal segments and gate line are in parallel, and the
The projection of two metal segments, the first metal segments and gate line on the array substrate thickness direction coincides, and not only reduces
First metal segments, influence of second metal segments to display area effective glazed area and array substrate aperture opening ratio, and
And achieve the effect that reduce gate line overall electrical resistance, to reduce the RC retardation ratio on gate line, improve described embedded
The non-uniform problem of gate line film flicker as caused by RC retardation ratio in formula touch screen.
Although the preferred embodiment is not to limit in conclusion the present invention has been disclosed as a preferred embodiment
The present invention, those of ordinary skill in the art can make various changes and profit without departing from the spirit and scope of the present invention
Decorations, therefore protection scope of the present invention subjects to the scope of the claims.
The above is a preferred embodiment of the present invention, it is noted that for those skilled in the art
For, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications are also considered as
Protection scope of the present invention.
Claims (10)
1. a kind of array substrate, which is characterized in that the array substrate includes the grid layer, the first metal layer and position being stacked
The first insulating layer between the grid layer and the first metal layer, first insulating layer for make the grid layer and
The first metal layer insulation, the grid layer includes gate line, and the first metal layer includes the first metal wire, described
Gate line intersects with projection of first metal wire on the array substrate thickness direction, and the first metal layer is also
Including the first metal segments of multistage, every section of first metal segments are and described between two adjacent first metal wires
The both ends of first metal segments and first metal wire form open circuit, the both ends of first metal segments and the gate line
Electrical connection, first metal segments coincide with projection of the gate line on the array substrate thickness direction.
2. a kind of array substrate according to claim 1, which is characterized in that the array substrate further includes multiple first logical
Hole, one end of the first through hole are connected to one end of first metal segments, and the other end connects the gate line, so that
First metal segments are in parallel with the gate line.
3. a kind of array substrate according to claim 2, which is characterized in that the length and width of every first metal segments
It spends identical.
4. a kind of array substrate according to claim 3, which is characterized in that the width and the grid of first metal segments
Pole signal wire it is of same size.
5. a kind of array substrate according to claim 1, which is characterized in that further include be located at the first metal layer on and
Be cascading second insulating layer, transparent electrode layer and second metal layer, and the second insulating layer is for insulating described first
Metal layer and the transparent electrode layer, the second metal layer include the second metal wire, second metal wire and described first
Projection of the metal wire on the array substrate thickness direction overlaps, and the second metal layer further includes the second metal of multistage
Section, every section of second metal segments are between two adjacent second metal wires, and the both ends of second metal segments and institute
It states the second metal wire and forms open circuit, the both ends of second metal segments are electrically connected with the gate line.
6. a kind of array substrate according to claim 1, which is characterized in that further include be located at the first metal layer on and
Be cascading second insulating layer, second metal layer and transparent electrode layer, and the second insulating layer is for insulating described first
Metal layer and the second metal layer, the second metal layer include the second metal wire, second metal wire and described first
Projection of the metal wire on the array substrate thickness direction overlaps, and the second metal layer further includes the second metal of multistage
Section, every section of second metal segments are between two adjacent second metal wires, and the both ends of second metal segments and institute
It states the second metal wire and forms open circuit, the both ends of second metal segments are electrically connected with the gate line.
7. a kind of array substrate according to claim 6, which is characterized in that the array substrate further includes multiple second logical
Hole, second through-hole one end are connected to one end of second metal segments, and the other end connects the gate line, so that institute
It is in parallel with the gate line to state the second metal segments.
8. a kind of array substrate according to claim 7, which is characterized in that the length of second metal segments and described the
One metal segment length is identical, second metal segments and projection of first metal segments on the array substrate thickness direction
It overlaps, one end of second through-hole connects one end of second metal segments, by one end of first metal segments, separately
One end connects the gate line, so that second metal segments, first metal segments are in parallel with the gate line.
9. a kind of array substrate according to claim 8, which is characterized in that second metal segments, first metal
Section is of same size with the gate line, and second metal segments, first metal segments and the gate line
Projection on the array substrate thickness direction coincides.
10. a kind of display device, which is characterized in that including a kind of array substrate described in claim 1-9 any one.
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| CN107093608B (en) * | 2017-05-04 | 2020-03-27 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
| CN107799537A (en) * | 2017-09-26 | 2018-03-13 | 武汉华星光电技术有限公司 | Array base palte and display device |
| CN110780497A (en) * | 2019-10-22 | 2020-02-11 | 深圳市华星光电技术有限公司 | Wiring structure of display panel, wiring method of display panel and display panel |
| CN110993617A (en) * | 2019-12-03 | 2020-04-10 | 武汉华星光电技术有限公司 | Array substrate, display panel and display device |
| CN111505875A (en) * | 2020-05-09 | 2020-08-07 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, display panel with array substrate and display device |
| CN114994994A (en) * | 2022-06-17 | 2022-09-02 | 北海惠科光电技术有限公司 | Liquid crystal display panel and preparation method thereof |
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| KR100859512B1 (en) * | 2002-04-25 | 2008-09-22 | 삼성전자주식회사 | A wiring, a method for manufacturing the wiring, and a thin film transistor array substrate including the wiring, and a method for manufacturing the substrate |
| CN102135691A (en) * | 2010-09-17 | 2011-07-27 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and liquid crystal display |
| CN202601619U (en) * | 2012-01-09 | 2012-12-12 | 京东方科技集团股份有限公司 | Thin film transistor, array substrate and display |
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| TWI244211B (en) * | 2003-03-14 | 2005-11-21 | Innolux Display Corp | Thin film transistor and method of manufacturing the same and display apparatus using the transistor |
| JP2014186121A (en) * | 2013-03-22 | 2014-10-02 | Panasonic Liquid Crystal Display Co Ltd | Liquid crystal display device and driving method thereof |
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| KR100859512B1 (en) * | 2002-04-25 | 2008-09-22 | 삼성전자주식회사 | A wiring, a method for manufacturing the wiring, and a thin film transistor array substrate including the wiring, and a method for manufacturing the substrate |
| CN102135691A (en) * | 2010-09-17 | 2011-07-27 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and liquid crystal display |
| CN202601619U (en) * | 2012-01-09 | 2012-12-12 | 京东方科技集团股份有限公司 | Thin film transistor, array substrate and display |
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