KR20120058119A - Thin film transistor array substrate and method thereof - Google Patents

Abstract

PURPOSE: A thin film transistor substrate and a manufacturing method thereof are provided to improve performance of the thin film transistor substrate by reducing deviation of an on-current generated by the overlay of an etching barrier pattern. CONSTITUTION: A gate wire comprises a gate electrode(24) and a gate line(22). Storage wires transferring a storage voltage are formed on an insulating substrate. A gate insulating layer is formed on the insulating substrate, the gate wire, and the storage wires. An oxide semiconductor layer pattern for forming a channel of a thin film transistor is formed on the gate insulating layer. An etching barrier pattern(52) is formed on the oxide semiconductor layer pattern. A data wire comprises a data line extended to a crossed direction with the gate line.

Description

Thin film transistor substrate and method for manufacturing same

The present invention relates to a thin film transistor substrate and a method of manufacturing the same.

Liquid Crystal Display (Liquid Crystal Display) is one of the most widely used flat panel display (flat panel display), and consists of two substrates on which electrodes are formed and a liquid crystal layer interposed therebetween, Is applied to rearrange the liquid crystal molecules of the liquid crystal layer to adjust the amount of light transmitted to display an image.

In general, the liquid crystal display includes a thin film transistor for switching each pixel. The thin film transistor forms a switching element using three terminals of a gate electrode to which a switching signal is applied, a source electrode to which a data voltage is applied, and a drain electrode to output a data voltage. The thin film transistor includes an active layer formed between the gate electrode and the source electrode and the drain electrode. At this time, an amorphous silicon layer is mainly used as the active layer included in the thin film transistor. Recently, as the size of a display device increases, an oxide semiconductor has attracted much attention due to the need for a high-performance device.

Using an oxide semiconductor layer as an active layer enables not only high performance device implementation but also reduction of capacitance between the source / drain electrodes and the gate electrode in the thin film transistor region.

When the oxide semiconductor layer is damaged by plasma, etching liquid or etching gas, the performance of the thin film transistor may be greatly reduced. Therefore, in the thin film transistor region, the oxide semiconductor layer may be formed by plasma, etching liquid or etching gas during the etching process or the deposition process. In order to prevent this from being damaged, an etch stop pattern is formed. An etch stop pattern formed in the thin film transistor region is formed to cover the oxide semiconductor layer, particularly to cover the channel region.

In the process of depositing such an etch stop pattern to be aligned at the center between the source electrode and the drain electrode, a deviation (overlay) may occur. In this case, the areas of the regions where the etch stop pattern and the source electrode and the drain electrode contact each other are different from each other. And a current-voltage curve when the voltage is applied in the direction from the source electrode to the drain electrode is different from that in the reverse direction, and the thin film transistor exhibits irregular on-current characteristics according to the amount of deviation. Will cause a decrease in performance.

The technical problem to be achieved by the present invention is to reduce the variation of the on-current caused by the overlay of the anti-etching pattern, which may inevitably occur in the thin film transistor substrate having an oxide semiconductor configuration, especially when the width of the channel region is small. It is to provide a thin film transistor substrate that can exhibit performance.

Another object of the present invention is to provide a method of manufacturing a thin film transistor substrate that can exhibit uniform performance by reducing the variation in on-current caused by the overlay of an etch stop pattern formed on the thin film transistor substrate having an oxide semiconductor configuration. To provide.

The technical objects of the present invention are not limited to the above-mentioned technical problems, and other technical subjects not mentioned can be clearly understood by those skilled in the art from the following description.

According to one or more exemplary embodiments, a thin film transistor substrate includes: a gate wiring disposed on the substrate and including a gate electrode and a gate line; An oxide semiconductor layer pattern disposed on the gate electrode; A data line disposed on the oxide semiconductor layer pattern and including a source electrode and a drain electrode constituting the gate electrode and the thin film transistor, and a data line extending in a direction crossing the gate line; And an etch stop pattern disposed in the first region between the source electrode and drain electrode and the oxide semiconductor layer pattern, wherein the etch stop pattern is formed of a low dielectric constant material, wherein the etch stop pattern overlaps the gate line and the data line. It is further disposed between the gate line and the data line in two regions.

In addition, a thin film transistor substrate according to another embodiment of the present invention for achieving the above object, the gate wiring including a gate electrode and a gate line disposed on the substrate, and the oxide semiconductor layer pattern disposed on the gate electrode And a pair of source and drain electrodes disposed on the oxide semiconductor layer pattern and constituting the gate electrode and the thin film transistor, and a data line extending in a direction crossing the gate line. A first channel region formed between one of the pair of source electrodes and a drain electrode and a second channel region formed between the other one of the pair of source electrodes and the drain electrode on a semiconductor layer pattern, respectively And a pair of anti-etching patterns, wherein the source electrode and the drain in the first channel region The position and the position of the source electrode and the drain electrode of the second channel section is arranged opposed to each other.

In addition, a method of manufacturing a thin film transistor substrate according to an embodiment of the present invention for achieving the above object, forming a gate wiring including a gate electrode and a gate line on the substrate; Forming a gate insulating film and an oxide semiconductor layer on the gate wiring; Forming an etch stop layer made of a low dielectric constant material on the oxide semiconductor layer; Patterning the etch stop layer to form an etch stop pattern in a first region that is a thin film transistor region; And forming a data line on the etch stop pattern, the data line including a source electrode and a drain electrode constituting the gate electrode and the thin film transistor, and the data line extending in a direction crossing the gate line.

In addition, a method of manufacturing a thin film transistor substrate according to another embodiment of the present invention for achieving the above object, forming a gate wiring including a gate electrode and a gate line on the substrate, and a gate insulating film on the gate wiring Forming an oxide semiconductor layer, forming an etch stop layer on the oxide semiconductor layer, patterning the etch stop layer to form a pair of etch stop patterns in the thin film transistor region, and the pair of etch Forming a data line on the protection pattern, the data line including a pair of source and drain electrodes constituting the gate electrode and the thin film transistor and the data line extending in a direction crossing the gate line; The pair of anti-etching patterns may include one of the pair of source electrodes and the drain electrode. And are formed at positions corresponding to the first channel region formed at the position corresponding to the first channel region and at positions corresponding to the second channel region formed between the other one of the pair of source electrodes and the drain electrode, respectively. And positions of the drain electrode and positions of the source electrode and the drain electrode in the second channel region are opposite to each other.

Specific details of other embodiments are included in the detailed description and the drawings.

1 is a layout view of a thin film transistor substrate according to a first exemplary embodiment of the present invention.
FIG. 2 is a cross-sectional view of the thin film transistor substrate of FIG. 1 taken along lines A-A 'and B-B'.
FIG. 3 is a comparison diagram illustrating overlay generation of an etch stop pattern of a thin film transistor substrate according to example embodiments. FIG.
FIG. 4 is a diagram comparing current changes between a data electrode and a source electrode when the overlay of FIG. 3B is generated.
FIG. 5 is a graph illustrating an on-current change amount according to an overlay generation size of FIG. 3 (b) and an on-current change amount according to a thickness change of an etching prevention pattern.
FIG. 6 is a graph illustrating an on-current change amount according to a change in dielectric constant of an etch stop pattern when an overlay occurs in FIG. 3 (b).
7 to 10 are process cross-sectional views sequentially illustrating a method of manufacturing a thin film transistor substrate according to a first exemplary embodiment of the present invention.
11 is a cross-sectional view of a thin film transistor substrate according to a second exemplary embodiment of the present invention.
12 to 15 are cross-sectional views sequentially illustrating a method of manufacturing a thin film transistor substrate according to a second exemplary embodiment of the present invention.
16 is a flowchart sequentially illustrating a process of manufacturing an etch stop pattern in a method of manufacturing a thin film transistor substrate according to a third exemplary embodiment of the present invention.
17 to 19 illustrate an arrangement of etch stop patterns in a thin film transistor substrate according to a fourth exemplary embodiment of the present invention.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and the general knowledge in the art to which the present invention pertains. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Thus, in some embodiments, well known process steps, well known device structures, and well-known techniques are not specifically described to avoid an undesirable interpretation of the present invention. Like reference numerals refer to like elements throughout.

The terms spatially relative, "below", "beneath", "lower", "above", "upper" May be used to readily describe a device or a relationship of components to other devices or components. Spatially relative terms are to be understood as including terms in different directions of the device in use or operation in addition to the directions shown in the figures. For example, when flipping a device shown in the figure, a device described as "below" or "beneath" of another device may be placed "above" of another device. Thus, the exemplary term "below" can include both downward and upward directions. The device can also be oriented in other directions, so that spatially relative terms can be interpreted according to orientation.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. As used herein, “comprises” and / or “comprising” refers to the presence of one or more other components, steps, operations and / or elements. Or does not exclude additions.

Unless otherwise defined, all terms (including technical and scientific terms) used in the present specification may be used in a sense that can be commonly understood by those skilled in the art. Also, commonly used predefined terms are not ideally or excessively interpreted unless explicitly defined otherwise.

As used herein, the term "thin film transistor substrate" refers to a substrate including at least one thin film transistor, and does not exclude a case where another structure is interposed between the thin film transistor and the substrate or another structure is formed thereon. .

Hereinafter, the thin film transistor substrate according to the first embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2. 1 is a layout view of a thin film transistor substrate according to a first exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view of the thin film transistor substrate of FIG. 1 taken along lines A-A 'and B-B'.

1 and 2, gate wirings 22 and 24 for transmitting a gate signal are formed on the insulating substrate 10. The gate lines 22 and 24 include a gate line 22 extending in one direction, for example, a horizontal direction, and a gate electrode 24 of the thin film transistor formed by protruding from the gate line 22 in a protrusion shape.

In addition, storage wirings 28 and 29 are formed on the insulating substrate 10 to transfer storage voltages. The storage wirings 28 and 29 may include a storage line 28 formed substantially parallel to the gate line 22 across the pixel area, and storage branched from the storage line 28 and extending in parallel with the data line 62. Electrode 29.

The storage electrode 29 may be formed in the shape of a square ring formed along the data line 62. In other words, an opening region is formed in the center of the storage electrode 29 so that the data line 62 is positioned, and the ring portion of the storage electrode 29 overlaps the pixel electrode 80 at least partially.

The shape and arrangement of the storage electrode 29 and the storage line 28 may be modified in various forms, and when there is sufficient storage capacitance caused by overlapping the pixel electrode 80 and the gate line 22. The storage electrode 29 and the storage line 28 may not be formed.

The gate wirings 22 and 24 and the storage wirings 28 and 29 include aluminum-based metals such as aluminum (Al) and aluminum alloys, silver-based metals such as silver (Ag) and silver alloys, copper (Cu) and copper alloys, and the like. It may be made of a copper-based metal, molybdenum-based metals such as molybdenum (Mo) and molybdenum alloy, chromium (Cr), titanium (Ti), tantalum (Ta). In addition, the gate lines 22 and 24 and the storage lines 28 and 29 may have a multilayer structure including two conductive layers (not shown) having different physical properties. One of these conductive films is a low resistivity metal, such as aluminum-based metal, silver-based metal, or copper, so as to reduce signal delay or voltage drop in the gate wirings 22 and 24 and storage wirings 28 and 29. It is made of a series metal and the like. In contrast, the other conductive layer is made of a material having excellent contact properties with other materials, in particular zinc oxide (ZnO), indium tin oxide (ITO) and indium zinc oxide (IZO), such as molybdenum-based metals, chromium, titanium, tantalum and the like. Examples of such a combination include a chromium bottom film and an aluminum top film, an aluminum bottom film and a molybdenum top film, and a titanium bottom film and a copper top film. However, the present invention is not limited thereto, and the gate lines 22 and 24 and the storage lines 28 and 29 may be made of various metals and conductors.

The gate insulating film 30 is formed on the insulating substrate 10, the gate wirings 22 and 24, and the storage wirings 28 and 29. The gate insulating layer 30 may be formed of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), or the like. In detail, the gate insulating layer 30 may be formed of a single layer or multiple layers, and when the multilayer layer is formed of a multilayer, the gate insulating layer 30 may have a structure in which silicon nitride and silicon oxide are stacked. In this case, the gate insulating layer 30 may be formed of a silicon oxide layer in a region in contact with the oxide semiconductor layer pattern 42, and a nitrogen oxide layer may be disposed below the silicon oxide layer. When the silicon oxide layer is in contact with the oxide semiconductor layer pattern 42, deterioration of the oxide semiconductor layer pattern 42 may be prevented. When the gate insulating film 30 is formed of a silicon oxynitride layer, it is possible to have an oxygen concentration distribution in the silicon oxynitride layer. Also in this case, the oxygen concentration becomes higher as it is closer to the oxide semiconductor layer pattern 42, whereby deterioration of the oxide semiconductor layer pattern 42 can be prevented.

An oxide semiconductor layer pattern 42 is formed on the gate insulating layer 30 to form a channel of the thin film transistor. The channel region is formed by the oxide semiconductor layer pattern 42 overlapping the gate electrode 24. In the present exemplary embodiment, the oxide semiconductor layer pattern 42 is formed to have substantially the same shape as the data lines 62, 65, and 66 to be described later except for the channel region. This is because the oxide semiconductor layer pattern 42 and the data lines 62, 65, and 66 are patterned using one etching mask in the process of manufacturing the thin film transistor substrate of the present embodiment, which will be described later. In other words, the oxide semiconductor layer pattern 42 has the same shape as the data lines 62, 65, and 66 except that the oxide semiconductor layer pattern 42 is formed in the channel region.

The oxide semiconductor layer pattern 42 includes a compound having a chemical formula represented by, for example, AxBxOx or AxBxCxOx. A is Zn or Cd, B is Ga, Sn or In, C is Zn, Cd, Ga, In, or Hf. X is not 0 and A, B and C are different. According to another embodiment, it may include any one material selected from the group consisting of InZnO, InGaO, InSnO, ZnSnO, GaSnO, GaZnO, GaZnSnO, GaInZnO, HfInZnO and ZnO. Such oxide semiconductors have semiconductor characteristics that are about 2 to 100 times more effective in mobility than hydrogenated amorphous silicon.

An etch stop pattern 52 is formed on the oxide semiconductor layer pattern 42. Here, the etch stop pattern 52 may include a first region A1, which is a thin film transistor region in which the gate electrode 24 and the source / drain electrodes 65 and 66, which will be described later, overlap, the gate line 22, and the data line ( The second region A2 and the storage wirings 28 and 29 and the data line 62 overlap with each other may be formed in the third region A3. If necessary, an etch stop pattern 52 may be formed in at least one of the first to third regions, and in addition, the fourth region may be used to reduce parasitic capacitance in an overlap region with the pixel electrode 80 described later. An etch stop pattern 52 may be formed in the above region.

The etch stop pattern 52 formed in the thin film transistor region is to prevent the oxide semiconductor layer pattern 42 from being damaged by plasma, etching solution, or etching gas during a subsequent etching process or a deposition process. This is because when the oxide semiconductor layer pattern 42 is damaged by plasma, etching liquid or etching gas, the performance of the thin film transistor may be greatly reduced. Accordingly, the etch stop pattern 52 formed in the first region A1, which is the thin film transistor region, is formed to cover the oxide semiconductor layer pattern 42, in particular, to cover the channel region. That is, in order to prevent the oxide semiconductor layer pattern 42 from being exposed in the channel region, the oxide semiconductor layer pattern 42 may be formed to be wider in the length direction of the channel than the channel region in the region overlapping the channel region.

On the other hand, the etch stop pattern 52 formed in the second area A2 is for reducing capacitance generated between the gate line 22 and the data line 62 in the second area A2, and the third area ( The anti-etching pattern 52 formed in A3) is for reducing capacitance generated between the storage lines 28 and 29 and the data line 62 in the third region A3. This is because the capacitance generated between the gate line 22 and the data line 62 or the capacitance generated between the storage lines 28 and 29 and the data line 62 causes an RC delay.

Therefore, the etch stop pattern 52 is formed on the oxide semiconductor layer pattern 42 in the first to third regions A1 to A3.

The pattern formed in the first region A1 of the etch stop pattern 52 may be positioned to be aligned in the center between the source electrode 65 and the drain electrode 66 as described below. At this time, when forming the etch stop pattern 52 in the process, the position of the pattern is biased to the source electrode 65 or the drain electrode 66 may cause a deviation (overlay). In particular, when the width of the channel region is 10 μm or less, since the etch stop pattern 52 must be formed more precisely, the overlay occurrence probability is high.

Hereinafter, referring to FIGS. 3 to 5, changes in device characteristics according to overlay generation of the etch stop pattern 52 will be described. FIG. 3A illustrates a normal case where no overlay occurs in the etch stop pattern 52 formed between the source electrode 65 and the drain electrode 66. FIG. 3B illustrates an overlay of the overlay electrode. It is a figure which shows the case which occurred. In FIG. 3A, the center line of the etch stop pattern 52 penetrates the center of the space where the source electrode 65 and the drain electrode 66 face each other without deviating to either side. Device characteristics in this normal case are shown in Fig. 4A. That is, the graph of FIG. 4A is a current-voltage curve when the etch stop pattern 52 is formed without overlay, and a curve SD when voltage is applied from the source electrode 65 to the drain electrode 66. It can be seen that the curve DS when the voltage is applied from the drain electrode 66 to the source electrode 65 coincides.

On the other hand, when the overlay occurs as shown in FIG. 3B, the center line of the etch stop pattern 52 is biased to one side without passing through the center of the space where the source electrode 65 and the drain electrode 66 face each other. Thus, the areas of the region where the etch stop pattern 52 and the source electrode 65 and the drain electrode 66 contact each other are different from each other, and as shown in the graph of FIG. 4B, the source electrode 65 The curve SD when the voltage is applied to the drain electrode 66 from the curve DS and the curve DS when the voltage is applied from the drain electrode 66 to the source electrode 65 are different from each other.

In this case, the size of the on-current changes according to the overlay size as shown in the graph of FIG. 5. That is, as the overlay value increases on the graph of FIG. 5, the on-current value increases. Therefore, when the overlay occurs, non-uniform on-current is generated, which causes a problem of degrading the performance of the thin film transistor. In particular, as shown in the graph of FIG. 5, the slope of the graph when the thickness of the etch stop pattern 52 is 300 μs has a larger value than that of the graph when the slope of the graph is 1000 μs. That is, the thicker the anti-etching pattern 52 is, the less sensitive the overlay is. Therefore, in order to prevent the transistor performance deterioration due to unavoidable overlay, a method of increasing the thickness of the etch stop pattern 52 may be considered. However, the method of increasing the thickness of the etch stop pattern 52 is disadvantageous in terms of cost, and there is a difficulty in the process because the desired etch stop pattern 52 is difficult to be formed by a subsequent process such as etching.

To solve this problem, the etch stop pattern 52 of the thin film transistor substrate according to the first embodiment of the present invention is formed of a material having a low dielectric constant (low-k). That is, when the etch stop pattern 52 is formed of a material having a relatively low dielectric constant compared to SiOx or SiNx, which is a general etch stop pattern 52 material, based on the same thickness, the sensitivity to the overlay is reduced. The amount of change in the current can be minimized, and the on-current can be maintained substantially uniform despite the occurrence of overlay, thereby preventing the degradation of transistor performance.

Such comparison results are shown in FIG. 6. That is, as can be seen in the comparison graph of FIG. 6, the larger the dielectric constant k, the larger the variation of the on-current due to the overlay generation. Conversely, the smaller the dielectric constant k, the smaller the change in on-current due to overlay generation (reduction of sensitivity to overlay). Referring to FIGS. 5 and 6 together, the case where the thickness of the etch stop pattern 52 is thin and the case where the dielectric constant of the etch stop pattern 52 is high correspond to each other, and there is a constant correspondence between the thickness and the dielectric constant. Can be established. In other words, the configuration in which the dielectric constant of the etch stop pattern 52 is prevented from flowing through the current corresponds to the configuration in which the thickness of the etch stop pattern 52 is increased to increase the possibility of blocking the current. Therefore, when the etch stop pattern 52 is formed of a material having a low dielectric constant, the thickness of the etch stop pattern 52 can be kept thin, and an advantageous effect of minimizing the variation of the on-current due to the overlay generation can be obtained.

In the first embodiment of the present invention, the lower the dielectric constant of the material forming the etch stop pattern 52 is, the more advantageous the effect of reducing the on-current variation caused by the overlay generation, especially if the dielectric constant of SiOx or less has a value of 3.9 or less Compared to the etching prevention pattern 52 made of SiOx or SiNx, the thickness may be maintained as it is, but the variation width of the on-current may be reduced.

In the first embodiment of the present invention, a material having a low dielectric constant forming the etch stop pattern 52 may be used without limitation as long as the material has a dielectric constant lower than that of SiOx. In particular, it may include SiOC: H used as a general inorganic insulating film. In addition, low dielectric constant materials that can be used as the etch stop pattern 52 include, for example, fluorosilicate glass, diamond carbon, silicon oxycarbide, parylene-N, fluorinated diamond carbon and parylene-F, poly Mead, hydrogen silsesquioxane, B-stage polymer, fluorinated polyimide, methyl silsesquioxane, polyarylene ether, polytetrafluoroethylene, porous silica, porous hydrogen silsesquioxane, porous silk, porous methyl silsesquioxane and Porous polyarylene ether is mentioned. The etch stop pattern 52 may be formed of one or more materials selected from the above low dielectric constant materials. By forming the etch stop pattern 52 with a material having such a low dielectric constant, more specifically, a material having a dielectric constant lower than that of SiOx forming the conventional etch stop pattern 52, the on-current even if an overlay occurs. By maintaining a substantially constant, it is possible to improve the performance of the thin film transistor substrate.

Referring back to FIG. 1, data lines 62, 65, and 66 are formed on the gate insulating layer 30, the oxide semiconductor layer pattern 42, and the etch stop pattern 52. The data lines 62, 65, and 66 are formed in a direction different from the gate line 22, for example, in a vertical direction, and intersect the gate line 22 to define a pixel to define a pixel from the data line 62. Branched in the form of a branch and extending to the upper portion of the oxide semiconductor layer pattern 42 and the etch stop pattern 52 of the thin film transistor region, and spaced apart from the source electrode 65 and the gate electrode ( A drain electrode 66 is formed on the oxide semiconductor layer pattern 42 and the etch stop pattern 52 of the first region A1 so as to face the source electrode 65 with respect to 24.

The etch stop pattern 52 is at least partially exposed between the source electrode 65 and the drain electrode 66. An oxide semiconductor layer pattern 42 is disposed under the etch stop pattern 52, the source electrode 65, and the drain electrode 66. That is, the oxide semiconductor layer pattern 42 completely overlaps the etch stop pattern 52, the source electrode 65, and the drain electrode 66. As described above, the source electrode 65 and the drain electrode 66 have substantially the same shape as the oxide semiconductor layer pattern 42 except for the isolation region overlapping the channel region.

The data lines 62, 65, and 66 may be formed of a single film or a multi-layer structure made of Ni, Co, Ti, Ag, Cu, Mo, Al, Be, Nb, Au, Fe, Se, or Ta. have. In addition, an alloy containing at least one element selected from Ti, Zr, W, Ta, Nb, Pt, Hf, O, and N may be applied to the metal. Examples of the multilayer structure include double films such as Ti / Cu, Ta / Al, Ta / Al, Ni / Al, Co / Al, Mo (Mo alloy) / Cu, or Mo / Al / Mo, Ti / Al / Ti, And triple films such as Ta / Al / Ta, Ti / Al / TiN, Ta / Al / TaN, Ni / Al / Ni, Co / Al / Co and the like. However, the data wires 62, 65 and 66 are not limited to the above materials.

The passivation layer 70 is formed on the data lines 62, 65, and 66 and the etch stop pattern 52 exposed by the data lines 62, 65, and 66. Like the gate insulating layer 30, the passivation layer 70 may be formed of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), or the like. According to the first embodiment, the passivation layer 70 may include a double layer including silicon nitride (SiNx) and silicon oxide (SiOx).

In the passivation layer 70, a contact hole 75 exposing a part of the drain electrode 66 is formed.

The pixel electrode 80 is formed on the passivation layer 70 to be electrically connected to the drain electrode 66 through the contact hole 75. The pixel electrode 80 may be made of a transparent conductor such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a reflective conductor such as aluminum.

The pixel electrode 80 to which the data voltage is applied generates an electric field together with the common electrode of the upper substrate facing the thin film transistor substrate to determine the arrangement of liquid crystal molecules of the liquid crystal layer between the pixel electrode 80 and the common electrode.

Hereinafter, a method of manufacturing the thin film transistor substrate according to the first embodiment of the present invention will be described in detail with reference to FIGS. 7 to 10. 7 to 10 are process cross-sectional views sequentially illustrating a method of manufacturing a thin film transistor substrate according to a first exemplary embodiment of the present invention. For convenience of description, in the following embodiments, members having the same functions as the members shown in the drawings of the above-described embodiments are denoted by the same reference numerals, and thus description thereof will be omitted or simplified.

First, referring to FIG. 7, gate wirings 22 and 24 and storage wirings 28 and 29 are formed on an insulating substrate 10.

Specifically, a gate wiring conductive film is formed on the insulating substrate 10 by, for example, sputtering or the like, and then the conductive film is patterned to form the gate wirings 22 and 24 and the storage wirings 28 and 29. Form.

Subsequently, referring to FIG. 8, the gate insulating layer 30, the oxide semiconductor layer 40, and the etch stop pattern 52 are sequentially formed on the resultant product formed with the gate wirings 22 and 24 and the storage wirings 28 and 29. Form.

Specifically, after forming the gate insulating film 30 using chemical vapor deposition (CVD) or sputtering, the oxide semiconductor layer 40 is formed on the gate insulating film 30 using sputtering or the like. do.

Subsequently, an etch stop layer is formed on the oxide semiconductor layer 40 by chemical vapor deposition, spin-on, or the like, and then the etch stop layer is patterned to form an etch stop pattern 52. As described above, the etch stop pattern 52 is formed to cover the first region A1, the second region A2, and the third region A3 of the thin film transistor region.

As described above, the etch stop pattern 52 according to the first embodiment of the present invention is formed of a low dielectric constant material, and the method of forming the etch stop layer is different depending on the selected low dielectric constant material. That is, chemical vapor deposition when at least one material selected from the group consisting of fluorosilicate glass, diamond-like carbon, silicon oxycarbide, parylene-N, fluorinated diamond-like carbon and parylene-F is selected as the low dielectric constant material It is effective to form an etch stop film by the method. On the other hand, polyimide, hydrogen silsesquioxane, B-stage polymer, fluorinated polyimide, methyl silsesquioxane, polyarylene ether, polytetrafluoroethylene, porous silica, porous hydrogen silseschioxane, porous silk, porous methyl silciene In the case where at least one material selected from the group consisting of skioxane and porous polyarylene ether is selected as the low dielectric constant material, it is effective to form an etch stop layer by a spin-on method.

Subsequently, referring to FIG. 9, the oxide semiconductor layer 40 is patterned to form the oxide semiconductor layer pattern 42 while forming the data lines 62, 65, and 66 on the resultant on which the etch stop pattern 52 is formed. do.

Specifically, a data wiring conductive film is formed on the oxide semiconductor layer 40 and the etch stop pattern 52 by, for example, sputtering, and the data wiring conductive film and the oxide semiconductor layer 40 are simultaneously formed by a photolithography process. By patterning, the oxide semiconductor layer pattern 42 and the data wirings 62, 65, and 66 are formed.

The source electrode 65 and the drain electrode 66 are formed to be separated on both sides with respect to the gate electrode 24, and an etch stop pattern 52 is formed in an area where the source electrode 65 and the drain electrode 66 are separated. Exposed. The gate insulating layer 30 and the etch stop pattern 52 are not damaged in the etching process for forming the data lines 62, 65, and 66 and the oxide semiconductor layer pattern 42. Therefore, the oxide semiconductor layer pattern 42 under the etch stop pattern 52 is protected from damage.

In addition, when the etch stop pattern 52 is formed in the second area A2, capacitance generated between the gate line 22 and the data line 62 may be reduced, and the etch stop may be prevented in the third area A3. When the pattern 52 is formed, the capacitance generated between the storage lines 28 and 29 and the data line 62 is reduced.

Next, referring to FIG. 10, after forming the protective film 70 using PECVD or reactive sputtering on the resultant, the protective film 70 is patterned by a photolithography process to expose a part of the drain electrode 66. The hole 75 is formed.

Subsequently, a conductive film for pixel electrodes connected to a part of the drain electrode 66 is formed on the protective film 70, and the conductive film for pixel electrodes is patterned to form the pixel electrode 80.

Hereinafter, a thin film transistor substrate according to a second exemplary embodiment of the present invention will be described in detail with reference to FIG. 11. 8 is a cross-sectional view of a thin film transistor substrate according to a second exemplary embodiment of the present invention, taken along a line corresponding to lines A-A 'and B-B' of FIG. 1.

The thin film transistor substrate according to the second embodiment of the present invention further includes multiple stacked patterns 53a and 53'a formed on or below the etch stop pattern 52a. The multiple stacked patterns 53a and 53'a form a stacked structure with the etch stop pattern 52a and are made of any one material selected from the group consisting of SiOx and SiNx. 11 illustrates a structure in which the entire triple layer is formed by being dually stacked on the upper and lower portions of the etch stop pattern 52a, but may have a structure in which the multiple lamination patterns 53a are stacked only on the upper or lower portions thereof. Accordingly, a structure in which more than one multilayered pattern 53a is stacked is also possible. Although the multi-layered pattern 53a is formed of the same material as a conventional anti-etching pattern, the on-current is generally replaced even when an overlay occurs due to the anti-etching pattern 52a according to the second embodiment of the present invention formed of a low dielectric constant material. You can keep it constant.

The rest of the configuration is the same as that of the thin film transistor substrate of the first embodiment described above.

Hereinafter, a method of manufacturing a thin film transistor substrate according to a second exemplary embodiment of the present invention will be described in detail with reference to FIGS. 12 to 15. 12 to 15 are cross-sectional views sequentially illustrating a method of manufacturing a thin film transistor substrate according to a second exemplary embodiment of the present invention.

First, referring to FIG. 12, gate wirings 22 and 24 and storage wirings 28 and 29 are formed on an insulating substrate 10.

Subsequently, referring to FIG. 13, the gate insulating layer 30, the oxide semiconductor layer 40, and the etch stop pattern 52a are multi-layered on the resultant product formed with the gate wirings 22 and 24 and the storage wirings 28 and 29. The pattern 53a is formed sequentially. The order of the etch stop pattern 52a and the multi-layered pattern 53a may be changed according to a desired stacking order. In the case where the multiple stacked patterns 53a and 53'a are formed in duplicate, first, the multilayered film 53a is formed, and then the etch stop layer 52a is formed, and then the multilayered film 53'a is formed again. do. Next, the etch stop layer 52a and the multiple stacked layers 53a and 53'a are patterned to form the etch stop pattern 52a and the multiple stacked patterns 53a and 53'a.

Subsequently, referring to FIG. 14, the oxide semiconductor layer 40 is patterned while forming the data wirings 62, 65, and 66 on the resultant product on which the etch stop pattern 52a and the multiple stacked pattern 53a are formed. The layer pattern 42 is formed.

The source electrode 65 and the drain electrode 66 are formed to be separated on both sides with respect to the gate electrode 24, and in the region where the source electrode 65 and the drain electrode 66 are separated, an etch stop pattern 52a and The multiple stacked patterns 53a and 53'a are exposed. The gate insulating layer 30 and the etch stop pattern 52 are not damaged in the etching process for forming the data lines 62, 65, and 66 and the oxide semiconductor layer pattern 42. Therefore, the oxide semiconductor layer pattern 42 under the etch stop pattern 52 is protected from damage.

Subsequently, referring to FIG. 15, after forming the protective film 70 using PECVD or reactive sputtering on the resultant, the protective film 70 is patterned by a photolithography process to expose a part of the drain electrode 66. The hole 75 is formed.

Subsequently, a conductive film for pixel electrodes connected to a part of the drain electrode 66 is formed on the protective film 70, and the conductive film for pixel electrodes is patterned to form the pixel electrode 80.

Hereinafter, a thin film transistor substrate according to a third exemplary embodiment of the present invention will be described in detail with reference to FIG. 16. 16 is a flowchart illustrating a part of a manufacturing process of a thin film transistor substrate according to a third exemplary embodiment of the present invention.

The anti-etching pattern 52 according to the third embodiment of the present invention may be formed of an organic material having photosensitivity to simplify the subsequent process. The photosensitive organic material may include all organic materials whose structure is changed by exposure to light, and may include both a negative type and a positive type according to a selection. That is, the etch stop pattern 52 may be formed through an exposure process and a curing process of exposing the photosensitive organic material to light, excluding a series of patterning processes such as general photoresist and etching.

First, as described in the above embodiments, the gate wirings 22 and 24 and the storage wirings 28 and 29 are formed on the insulating substrate 10, and then the gate wirings 22 and 24 and the storage wiring ( The gate insulating film 30 and the oxide semiconductor layer 40 are formed on the resultant formed with 28 and 29.

Subsequently, the photosensitive organic material is coated on the entire surface of the substrate 10 including the oxide semiconductor layer 40 (S10). Next, as described above, the photosensitive organic material is reacted in a desired pattern by selectively performing an exposure process on the first to third regions A1 to A3 (S20). Next, the photosensitive organic material on the area exposed to light is cured to form an etch stop pattern 52 having a desired shape (S30). Thereafter, the photosensitive organic material of the remaining uncured region is removed (S40). The photosensitive organic material used has a low dielectric constant as described above, and the process of coating the photosensitive organic material on the substrate 10 may be a general coating method such as spin coating, roll coating, spray coating and dip coating. have. The selective exposure process may be performed using an optical mask having a shape of a desired etch stop pattern 52 or adjusting an exposure opening of light through an optical filter. The process of curing the photosensitive organic material may be performed in the same manner as a general curing operation.

When the etching prevention pattern 52 is formed of the photosensitive organic material having the low dielectric constant as described above, a series of photoresist coating processes and etching processes can be omitted, thereby simplifying the process and advantageous in terms of cost. Has In addition, due to the low dielectric constant etching prevention pattern 52, even when the overlay occurs, the on-current variation may be minimized to improve the performance of the thin film transistor.

17 to 19, a thin film transistor substrate according to a fourth embodiment of the present invention will be described in detail. 17 to 19 illustrate a plurality of anti-etching patterns 52 of a thin film transistor substrate according to a fourth exemplary embodiment of the present invention.

Due to the overlay generation of the etch stop pattern 52 according to the fourth embodiment of the present invention, the value of the current flowing from the source electrode 65 to the drain electrode 66, and from the drain electrode 66 to the source electrode 65. In order to solve the problem that the value of the flowing current is nonuniform, as shown in FIG. 17, the source electrode 65 and the drain electrode 66 form the dual channels C1 and C2. In addition, a pair of anti-etching patterns 52 may be formed between the source electrode 65 and the drain electrode 66 and between the drain electrode 66 and the source electrode 65 ′. . As the anti-etching pattern 52 is formed by forming a single layer and then etching the patterned pattern as described above, a pair of etch-preventing patterns 52 are formed at the same time. In this case, as shown in FIG. 17, the pair of etch stop patterns 52 are all biased to one side by the same deviation. In this case, the positions of the source electrode and the drain electrode in the first channel region C1 and the positions of the source electrode and the drain electrode in the second channel region C2 are disposed opposite to each other. That is, as shown in FIG. 17, in the first channel region C1 on the left side, the source electrode 65 is positioned on the left side of the etch stop pattern 52 and the drain electrode 66 is positioned on the right side. On the contrary, in the second channel region C2 on the right side, the source electrode 65 is positioned on the right side of the etch stop pattern 52 and the drain electrode 66 is positioned on the left side.

In this case, the overlays of the pair of source electrodes 65 and the drain electrodes 66 cancel each other out so as to be zero overall. That is, when one channel C1 is referenced, the overlay occurs toward the drain electrode 66, and when the other channel C2 is referenced, the same amount of overlay occurs toward the source electrode 65 '. The overall overlay on channels C1 and C2 is zero. Therefore, when the on-current increases in one channel C1, the on-current decreases in the other channel C2, so that the on-current of the entire dual channels C1 and C2 has a constant value. The opposite is also true. That is, even when an overlay occurs in forming a pair of etch stop patterns 52 by forming a complementary relationship between the respective channels when the overlay occurs in the dual channels C1 and C2, the dual channel C1, Due to the complementary action of C2), the amount of on-current flowing through the entire thin film transistor substrate is constant, thereby improving the performance of the thin film transistor.

18, a structure in which one source electrode 65 forms a drain electrode 66 and dual channels C1 and C2 is described below. That is, the source electrode 65 may be formed in a U shape in which the drain electrode 66 is formed at the center and surrounds the drain electrode 66. Even in this case, even when an overlay occurs in the formation of the dual channel C1 and C2 to form the pair of etch stop patterns 52, the entire thin film transistor substrate is formed due to the complementary action of the dual channels C1 and C2. The amount of on-current flowing in the constant is constant, so that the performance of the thin film transistor can be improved.

Subsequently, referring to FIG. 19, one source electrode 65 shows a structure in which the drain electrode 66 and the dual channels C1 and C2 are formed, but the dual channels C1 and C2 are not adjacent to each other and spaced apart from each other. Even when formed in the form can exhibit the same effect. That is, even in this case, even when an overlay occurs when the dual channels C1 and C2 are formed to form a pair of etch stop patterns 52, the entire thin film is formed due to the complementary action of the dual channels C1 and C2. The amount of on-current flowing through the transistor substrate is constant, so that the performance of the thin film transistor can be improved.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

10: insulating substrate 22: gate line
24: gate electrode 28: storage line
29: storage electrode 30: gate insulating film
42: oxide semiconductor pattern 52: etch stop pattern
53a: Multiple laminated pattern 62: Data line
65 source electrode 66 drain electrode
70: Shield 75: Contact Hole
80: pixel electrode

Claims (24)

A gate wiring disposed on the substrate, the gate wiring including a gate electrode and a gate line;
An oxide semiconductor layer pattern disposed on the gate electrode;
A data line disposed on the oxide semiconductor layer pattern and including a source electrode and a drain electrode constituting the gate electrode and the thin film transistor, and a data line extending in a direction crossing the gate line; And
An etching preventing pattern is formed in the first region between the source electrode and the drain electrode and the oxide semiconductor layer pattern, and is formed of a low dielectric constant material.
The etch stop pattern is further disposed between the gate line and the data line in a second region where the gate line and the data line overlap. The method of claim 1,
The low dielectric constant material has a dielectric constant of 3.9 or less thin film transistor substrate. The method of claim 1,
The etch stop pattern is a thin film transistor substrate comprising SiOC: H. The method of claim 1,
The low dielectric constant material includes at least one selected from the group consisting of fluorosilicate glass, diamond-like carbon, silicon oxycarbide, parylene-N, fluorinated diamond-like carbon, and parylene-F. The method of claim 1,
The low dielectric constant material is polyimide, hydrogen silsesquioxane, B-stage polymer, fluorinated polyimide, methylsilsesquioxane, polyarylene ether, polytetrafluoroethylene, porous silica, porous hydrogen silsesuccioxane, porous silk, A thin film transistor substrate comprising at least one selected from the group consisting of porous methylsilsesuccioxane and porous polyarylene ether. The method according to claim 1, wherein
The low dielectric constant material has a photosensitive thin film transistor substrate. The method of claim 1,
And a storage line disposed on the same layer as the gate line, wherein the etch stop pattern is further disposed in a third region in which the storage line and the data line overlap. The method of claim 1,
The thin film transistor substrate further comprising a multi-layered pattern formed on the upper or lower portion of the etch stop pattern to form a stack structure with the etch stop pattern, and made of any one material selected from the group consisting of SiOx and SiNx. A gate wiring disposed on the substrate, the gate wiring including a gate electrode and a gate line;
An oxide semiconductor layer pattern disposed on the gate electrode;
A data line disposed on the oxide semiconductor layer pattern and including a pair of source and drain electrodes constituting the gate electrode and the thin film transistor and extending in a direction crossing the gate line; And
On the oxide semiconductor layer pattern, a first channel region formed between one of the pair of source electrodes and a drain electrode, and a second channel region formed between the drain electrode and another one of the pair of source electrodes. Includes a pair of anti-etch patterns, each of which is disposed,
A thin film transistor substrate having positions of source and drain electrodes in the first channel region and positions of source and drain electrodes in the second channel region opposite to each other. 10. The method of claim 9,
The pair of source electrodes are formed on the thin film transistor substrate branched from one source electrode. 10. The method of claim 9,
The thin film transistor substrate of claim 1, wherein the source electrode has a U or S shape in the first and second channel regions. 10. The method of claim 9,
The thin film transistor substrate of claim 1, wherein the first channel region and the second channel region are spaced apart from each other. Forming a gate wiring including a gate electrode and a gate line on the substrate;
Forming a gate insulating film and an oxide semiconductor layer on the gate wiring;
Forming an etch stop layer made of a low dielectric constant material on the oxide semiconductor layer;
Patterning the etch stop layer to form an etch stop pattern in a first region that is a thin film transistor region; And
Forming a data line on the etch stop pattern, the data line including a source electrode and a drain electrode constituting the gate electrode and the thin film transistor and the data line extending in a direction crossing the gate line; Method of preparation. The method of claim 13,
After the oxide semiconductor layer forming step,
Patterning the oxide semiconductor layer to form an oxide semiconductor layer pattern on at least the gate electrode. The method of claim 13,
The data line forming step,
Forming a conductive film for data wiring; And
Patterning the conductive film for data wiring;
And forming the oxide semiconductor layer pattern by patterning the oxide semiconductor layer together in the conductive film patterning step for data wiring. The method of claim 13,
The etching prevention film forming step,
Depositing a low dielectric constant material having a dielectric constant of 3.9 or less on the oxide semiconductor layer. The method of claim 13,
The etching prevention film forming step,
At least one material selected from the group consisting of fluorosilicate glass, diamond-like carbon, silicon oxycarbide, parylene-N, fluorinated diamond-like carbon, and parylene-F is selected as the low dielectric constant material on the oxide semiconductor layer Depositing in,
The etching prevention film forming step,
And depositing the low dielectric constant material by chemical vapor deposition. The method of claim 13,
The etching prevention film forming step,
Polyimide, hydrogen silsesquioxane, B-stage polymer, fluorinated polyimide, methyl silsesquioxane, polyarylene ether, polytetrafluoroethylene, porous silica, porous hydrogen silsesquioxane, porous silk, porous methyl silsesquioxane And selecting at least one material selected from the group consisting of porous polyarylene ethers as the low dielectric constant material and depositing the same on the oxide semiconductor layer,
The etching prevention film forming step,
Spin-on depositing the low dielectric constant material. The method of claim 13,
The etching prevention film forming step,
Depositing a low dielectric constant material having photosensitivity on said oxide semiconductor layer,
The etching prevention pattern forming step,
Selectively exposing only to the first region;
Curing the etch stop layer of the first region;
Removing the etch stop layer other than the hardened first region. The method of claim 13,
The gate wiring forming step includes forming a storage wiring arranged on the same layer as the gate wiring,
The etching prevention pattern forming step,
Forming the anti-etching pattern in a second region in which the gate line and the data line overlap each other;
And forming the etch stop pattern in a third region in which the storage line and the data line overlap each other. Forming a gate wiring including a gate electrode and a gate line on the substrate;
Forming a gate insulating film and an oxide semiconductor layer on the gate wiring;
Forming an etch stop layer on the oxide semiconductor layer;
Patterning the etch stop layer to form a pair of etch stop patterns in a thin film transistor region; And
Forming a data line on the pair of etch stop patterns, the data line including a pair of source and drain electrodes constituting the gate electrode and the thin film transistor and the data line extending in a direction crossing the gate line; Including,
The pair of etch stop patterns may be formed between a drain electrode and a position corresponding to a first channel region formed between one of the pair of source electrodes and the drain electrode, and the other of the pair of source electrodes and the drain electrode. Thin-film transistors respectively formed at positions corresponding to the second channel region, and the source electrode and the drain electrode in the first channel region and the source electrode and the drain electrode in the second channel region are disposed opposite to each other. Method of manufacturing a substrate. The method of claim 21,
And the pair of source electrodes are branched from one source electrode. The method of claim 21,
The method of claim 1, wherein the source electrode has a U or S shape in the first and second channel regions. The method of claim 21,
And the first channel region and the second channel region are spaced apart from each other.

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