KR101090256B1 - Optical mask and manufacturing method of thin film transistor array panel using the mask - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photomask, wherein the photomask includes a transmissive region and a transflective region, the transflective region having a predetermined area and arranged in a matrix form at predetermined intervals. In this case, each of the plurality of light blocking units has a rectangular shape. The area of each of the plurality of light blocking portions is determined according to the width or length width.

Thin film transistor display panel, slit, mask, undercut, photoresist, photomask, photoresist thickness

Description

Optical mask and manufacturing method of thin film transistor array panel using same {OPTICAL MASK AND MANUFACTURING METHOD OF THIN FILM TRANSISTOR ARRAY PANEL USING THE MASK}

1 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention.

2A and 2B are cross-sectional views of the thin film transistor array panel of FIG. 1 taken along lines IIa-IIa 'and IIb-IIb', respectively.

3 and 6 are layout views at intermediate stages of the method for manufacturing the thin film transistor array panel shown in FIGS. 1 to 2B according to one embodiment of the present invention, respectively, and are arranged in the order of the process.

4A and 4B are cross-sectional views of the thin film transistor array panel of FIG. 3 taken along lines IVa-IVa 'and IVb-IVb', respectively.

5A and 5B are cross-sectional views of the thin film transistor array panel illustrated in FIG. 3 taken along the lines IVa-IVa 'and IVb-IVb', respectively, and are views of the next steps of FIGS. 4A and 4B.

7A and 7B are cross-sectional views of the thin film transistor array panel of FIG. 6 taken along lines VIIa-VIIa 'and VIIb-VIIb', respectively.

8A and 8B are cross-sectional views of the thin film transistor array panel of FIG. 6 taken along the lines VIIa-VIIa 'and VIIb-VIIb', respectively, and are views of the next steps of FIGS. 7A and 7B.

Figures 9a and 9b show the next steps in Figures 8a and 8b respectively.

Figures 10a and 10b show the next steps in Figures 9a and 9b respectively.

11A and 11B are views at the next stage of FIGS. 10A and 10B, respectively.

12A and 12B are views in the next steps of FIGS. 11A and 11B, respectively.

13 is a plan view of a semi-transmissive region of the photomask according to an embodiment of the present invention.

The present invention relates to a thin film transistor array panel and a method of manufacturing the same.

A thin film transistor (TFT) is used as a circuit board for independently driving each pixel in a liquid crystal display device, an organic electroluminescence (EL) display device, or the like.

The thin film transistor array panel includes a gate line transferring a gate signal and a data line transferring a data signal, and includes a thin film transistor connected to the gate line and the data line, a pixel electrode connected to the thin film transistor, and the like.

The thin film transistor is a switching element that controls a data signal transmitted to a pixel electrode through a data line in response to a gate signal transmitted through a gate line. The thin film transistor includes a semiconductor layer and a data line forming a channel and a gate electrode connected to the gate line. A source electrode and a drain electrode facing the source electrode are mainly formed around the semiconductor layer.

However, in order to manufacture the thin film transistor array panel, several photolithography processes are required. Each photolithography process includes a number of complex detailed processes, so the number of photolithography processes determines the time and cost of the thin film transistor array panel manufacturing process.

An object of the present invention is to simplify the manufacturing process of a thin film transistor array panel.

Another technical problem to be achieved by the present invention is to prevent undercuts occurring under the drain electrode.

Another technical problem to be achieved by the present invention is to maintain a constant thickness of the photosensitive film.

According to an aspect of the present invention, a photomask includes a transmissive region and a transflective region, and the transflective region includes a plurality of light blocking units having a predetermined area and arranged in a matrix form.

Preferably, the plurality of light blocking portions have different areas.                     

It is preferable that the plurality of light blocking portions have the same area and have different formation densities according to positions.

Each of the plurality of light blocking units may have a polygonal shape. In this case, each of the plurality of light blocking units may have a rectangular, triangular or rhombus shape.

Each of the plurality of light blocking units may have a circular or elliptical shape.

The plurality of light blocking units may be arranged in a matrix form.

The photomask may further include a light blocking area.

According to another aspect of the present invention, a method of manufacturing a thin film transistor array panel includes forming a gate line including a gate electrode on a substrate, forming a first insulating layer on the gate line, and forming a semiconductor layer on the first insulating layer. Forming a data line including a source electrode, a drain electrode and a storage capacitor conductor on the semiconductor layer, stacking a second insulating film, applying a photoresist film on the second insulating film, and applying a photomask on the photoresist film. Aligning, irradiating light to the photosensitive film through the photomask, and then developing the photosensitive film to form a photosensitive film including a first portion and a second portion thinner than the first portion on the second insulating film; And etching the second insulating film to expose a part of the drain electrode and the conductor for the storage capacitor. Leaving a first portion of the second insulating film under the second portion of the photosensitive film, stacking a conductive film, and removing the first portion of the photosensitive organic film to be connected to the drain electrode and the conductor for the storage capacitor. And forming a pixel electrode, wherein the photomask includes a light blocking region, a transflective region, and a transmissive region, and the transflective region includes a plurality of light blocking portions having a predetermined area and arranged in a matrix form.

Preferably, the plurality of light blocking portions have different areas.

The plurality of light blocking portions may have the same area and have different forming densities according to positions.

Each of the plurality of light blocking units may have a polygonal shape, and in this case, each of the plurality of light blocking units may have a rectangular shape.

Each of the plurality of light blocking portions may have a circular or elliptical shape. The second portion of the photosensitive film may be positioned on a portion of an edge of the conductive capacitor conductor.

Leaving the first portion of the second insulating layer may expose a portion of the data line.

Leaving the first portion of the second insulating layer may further include exposing a portion of the gate line by etching the first insulating layer.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity, and like reference numerals designate like parts throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Hereinafter, a thin film transistor array panel and a method of manufacturing the same according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

First, a thin film transistor array panel according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 to 2B.

1 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention, and FIGS. 2A and 2B are cross-sectional views of the thin film transistor array panel of FIG. 1 taken along lines IIa-IIa 'and IIb-IIb', respectively. One example.

1 to 2B, a plurality of gate lines 121 are formed on the insulating substrate 110.

The gate line 121 mainly extends in the horizontal direction and transmits a gate signal, and has a wide end portion 129 for connection with another layer or an external device. A portion of each gate line 121 protrudes downward to form a plurality of gate electrodes 124.

The gate line 121 may be formed of a silver-based metal such as silver (Ag) or a silver alloy, an aluminum-based metal such as aluminum (Al) or an aluminum alloy, and a copper-based metal such as copper (Cu) or a copper alloy, chromium (Cr), or titanium ( Ti), tantalum (Ta), molybdenum (Mo) and an alloy consisting of an alloy thereof. However, the gate line 121 may have a multi-layer structure including two conductive layers (not shown) having different physical properties. In this case, one conductive film is made of a low resistivity metal such as an aluminum-based metal, a silver-based metal, or a copper-based metal so as to reduce the signal delay or voltage drop of the gate line 121. In contrast, the other conductive film is made of a material having excellent contact properties with other materials, particularly indium tin oxide (ITO) and indium zinc oxide (IZO), such as chromium, molybdenum, titanium, tantalum or alloys thereof. Examples of the structure in which a low resistivity conductive film comes on the top and a conductive film having excellent contact properties on the bottom include a chromium bottom film and an upper film of aluminum-neodymium (Nd) alloy, and vice versa. And an upper film.

The side of the gate line 121 is inclined with respect to the surface of the substrate 110, the inclination angle is in the range of about 30-80 degrees.

A gate insulating layer 140 made of silicon nitride (SiNx) is formed on the gate line 121.

A plurality of linear and island semiconductors 151 and 157 made of hydrogenated amorphous silicon (amorphous silicon is abbreviated a-Si) and the like are formed on the gate insulating layer 140. The linear semiconductor 151 extends mainly in the longitudinal direction from which a plurality of projections 154 extend toward the gate electrode 124. The island semiconductor 157 is separated from the linear semiconductor 151 and has an approximately rectangular shape.                     

On top of the semiconductors 151, 157 a plurality of linear and island ohmic contacts 161, 165, 167 made of a material such as n + hydrogenated amorphous silicon doped with a high concentration of silicide or n-type impurities. ) Is formed. The linear contact member 161 has a plurality of protrusions 163, and the protrusions 163 and the island contact members 165 are paired and positioned on the protrusions 154 of the semiconductor 151. The island contact members 167 are mainly positioned on the island semiconductors 167. The sides of the semiconductors 151 and 157 and the ohmic contacts 161, 165 and 167 are also inclined with respect to the surface of the substrate 110 and the inclination angle is 30. -80 °.

A plurality of data lines 171, a plurality of drain electrodes 175, and a plurality of storage capacitor conductors 177 are formed on the ohmic contacts 161, 165, and 167. Is formed.

The data line 171 transferring the data voltage mainly extends in the vertical direction to intersect the gate line 121 and has a wide end portion 179 for connection with another layer or an external device. A plurality of branches extending from the data line 171 toward the drain electrode 175 forms a source electrode 173. Each drain electrode 175 has one end portion 177 that is wider and the other end portion that is linear for connection with another layer, and each source electrode 173 has the other end of the drain electrode 175. It is curved to partially surround the end. The gate electrode 124, the source electrode 173, and the drain electrode 175 form a thin film transistor together with the protrusion 154 of the semiconductor 151, and a channel of the thin film transistor is a source electrode 173 and a drain electrode. It is formed in the protrusion 154 between the (175).

The storage capacitor conductor 177 overlaps the extension portion 127 of the gate line 121.

The data line 171, the drain electrode 175, and the conductor 177 for the storage capacitor may be made of a refractory metal such as chromium, titanium, tantalum, molybdenum, or an alloy thereof. Or it may have a multilayer film structure including a conductive film made of aluminum-based metal, and other conductive films made of chromium, titanium, tantalum, molybdenum and alloys thereof.

Sides of the data line 171, the drain electrode 175, and the storage capacitor conductor 177 are also inclined, and the inclination angle is in the range of about 30-80 ° with respect to the horizontal plane.

The ohmic contacts 161, 165, and 167 exist only between the semiconductors 151 and 157 thereunder and the data line 171, the drain electrode 175, and the storage capacitor conductor 177 thereon, and have a contact resistance. It serves to lower.

The linear semiconductor 151 has substantially the same shape as the data line 171, the drain electrode 175, and the ohmic contacts 161 and 165 thereunder. However, it has a portion exposed between the source electrode 173 and the drain electrode 175, and not covered by the data line 171 and the drain electrode 175. The island-like semiconductor 157 has a shape substantially the same as the conductor 177 for the storage capacitor and the ohmic contact 167 below.

A passivation layer 180 made of inorganic material such as silicon nitride on the gate line 121, the data line 171, the conductive capacitor 177 for the storage capacitor, and the entire exposed portion of the semiconductor 154 and the drain electrode 175. Is formed. However, the passivation layer 180 is an organic material having excellent planarization characteristics and photosensitivity, but a-Si: C: O and a-Si: O formed by plasma enhanced chemical vapor deposition (PECVD). It may be made of a low dielectric constant insulating material having a dielectric constant of about 4.0 or less, such as: F, and may have a double film structure of a lower inorganic film and an upper organic film.

The passivation layer 180 has a plurality of contact holes 182 that expose respective ends 179 of the data line 171. In addition, the passivation layer 180 together with the gate insulating layer 140 may be formed in a region surrounded by the plurality of contact holes 181 exposing the end portion 129 of the gate line 121 and the gate line 121 and the data line 171. It has a plurality of openings 187. The opening 187 exposes a part of the substrate 110, and a portion M of the protective layer 180 covering the edge of the conductive capacitor conductor 177 may be thinner than other portions.

A plurality of pixel electrodes 190 are formed on the passivation layer 180 formed near the edge portion H of the opening 187 and the conductive capacitor 177 for the storage capacitor, and the contact holes 181 and 182. A plurality of contact assistants 81 and 82 are formed. The pixel electrode 190 and the contact assistants 81 and 82 are made of a transparent conductor or reflective metal such as IZO, ITO, or a-ITO (amorphous ITO). Except for the passivation layer 180 formed near the edge H of the storage capacitor conductor 177, the boundary between the pixel electrode 190 and the contact auxiliary members 81 and 82 is substantially the same as the boundary of the passivation layer 180. Matches.                     

The pixel electrode 190 is physically and electrically connected to the drain electrode 175 to receive a data voltage from the drain electrode 175.

The pixel electrode 190 applied with the data voltage generates an electric field together with a common electrode (not shown) of another display panel (not shown) to which a common voltage is applied, thereby generating liquid crystal molecules of the liquid crystal layer between the two electrodes. Rearrange them.

In addition, the pixel electrode 190 and the common electrode form a capacitor (hereinafter, referred to as a "liquid crystal capacitor") to maintain an applied voltage even after the thin film transistor is turned off. There is another capacitor connected in parallel with it, which is called a storage capacitor. The storage capacitor is made by overlapping the pixel electrode 190 with another gate line 121 adjacent thereto (referred to as a prior gate line), and in order to increase the capacitance of the storage capacitor, that is, the storage line. An extension portion 127 extending from 121 is enlarged to increase the overlapped area, while a conductive capacitor conductor 177 connected to the pixel electrode 190 and overlapping the extension portion is placed under the protective film 180. Keep the distance between them.

The contact auxiliary members 81 and 82 are connected to the end portion 129 of the gate line and the end portion 179 of the data line, respectively, through the contact holes 181 and 182. The contact auxiliary members 81 and 82 complement the adhesion between the end portion 129 of the gate line and the end portion 179 of the data line and the external device, and are not essential to protect them. Is optional.

Next, a method of manufacturing the thin film transistor array panel illustrated in FIGS. 1 to 2B according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 3 to 13 and FIGS. 1 to 2B.

3 and 6 are layout views at intermediate stages of the method for manufacturing the thin film transistor array panel shown in FIGS. 1 to 2B according to one embodiment of the present invention, respectively, and are arranged in the order of the process. 4A and 4B are cross-sectional views of the thin film transistor array panel of FIG. 3 taken along lines IVa-IVa 'and IVb-IVb', respectively. 5A and 5B are cross-sectional views of the thin film transistor array panel illustrated in FIG. 3 taken along the Va-Va 'line and the Vb-Vb' line, respectively, and shown in the subsequent steps of FIGS. 4A and 4B. 7A and 7B are cross-sectional views of the thin film transistor array panel of FIG. 6 taken along lines VIIa-VIIa 'and VIIb-VIIb', respectively. 8A and 8B are cross-sectional views of the thin film transistor array panel of FIG. 6 taken along the lines VIIIa-VIIIa 'and VIIIb-VIIIb', respectively, and are views of the next steps of FIGS. 7A and 7B. 9A and 9B are views at the next stages of FIGS. 8A and 8B, respectively. FIGS. 10A and 10B are views at the next stages of FIGS. 9A and 9B, respectively. FIGS. 11A and 11B are respectively FIGS. 10A and 11B. 10b is the drawing in the next step. Figures 12a and 12b show the following steps in Figures 11a and 11b respectively. Figure 13 is a plan view of a transflective area of an optical mask according to an embodiment of the invention.

First, as shown in FIGS. 3 to 4B, a conductive layer such as a metal is deposited on the insulating substrate 110 made of transparent glass to a thickness of 1,000 kPa to 3,000 kPa by a sputtering method, and photo-etched to form a plurality of gates. A plurality of gate lines 121 including the electrodes 124 are formed.                     

Next, as shown in FIGS. 5A and 5B, the gate insulating layer 140, the intrinsic amorphous silicon layer 150, and the impurity amorphous silicon layer 160 are successively laminated by chemical vapor deposition (CVD) or the like. Subsequently, the conductive layer 170 such as metal is deposited to a predetermined thickness by a sputtering method, and then the photosensitive film 40 is applied thereon to a thickness of 1 μm to 2 μm.

Thereafter, the photosensitive film 40 is irradiated with light through a photomask (not shown) and then developed. The thickness of the developed photoresist film varies depending on the position. In FIGS. 5A and 5B, the photoresist film 40 includes first to third portions of which thickness is changed. The first part located in the area A (hereinafter referred to as the wiring area) and the second part located in the area B (hereinafter referred to as the channel area) are denoted by reference numerals 42 and 44, respectively, and the area C (hereinafter referred to as "other"). Reference numerals are not given to the third portion located in the region, because the third portion has a thickness of zero, so that the lower conductive layer 170 is exposed. The ratio of the thicknesses of the first portion 42 and the second portion 44 varies depending on the process conditions in the subsequent process, but the thickness of the second portion 44 is 1/2 of the thickness of the first portion 42. It is preferable to set it as the following, for example, it is good that it is 4,000 Pa or less.

As such, there may be various methods of varying the thickness of the photoresist film according to the position. The transmissive area as well as the light transmitting area and the light blocking area may be provided in the exposure mask. For example. The semi-transmissive region is provided with a slit pattern, a lattice pattern, or a thin film having a medium transmittance or a medium thickness. When using the slit pattern, it is preferable that the width of the slits and the interval between the slits are smaller than the resolution of the exposure machine used for the photographic process. Another example is to use a photoresist film capable of reflowing. That is, a thin portion is formed by forming a reflowable photoresist film with a conventional mask having only a transmissive area and a light shielding area, and then reflowing so that the photoresist film flows into an area where no photoresist film remains.

Given the appropriate process conditions, the underlying layers can be selectively etched due to the difference in thickness of the photoresist films 42 and 44. Therefore, a plurality of data lines 171 including a plurality of source electrodes 173 and a plurality of drain electrodes 175 and a plurality of storage capacitor conductors as shown in FIGS. 6 to 7B through a series of etching steps are performed. A plurality of linear resistive contact members 161 and a plurality of islands of resistive contact members 165 and 167 forming 177 and each comprising a plurality of protrusions 163, and a plurality of protrusions 154 and a plurality of islands. A plurality of linear semiconductors 151 including the semiconductors 157 are formed.

For convenience of description, portions of the conductor layer 170 located in the wiring region A, the impurity amorphous silicon layer 160, and the intrinsic amorphous silicon layer 150 are referred to as first portions, and the conductor layer located in the channel region B. A portion of the impurity amorphous silicon layer 160 and the intrinsic amorphous silicon layer 150 is referred to as a second portion, and the conductor layer 170 located in the other region C, the impurity amorphous silicon layer 160, and the intrinsic A part of the amorphous silicon layer 150 is called a third part.

One example of the order of forming such a structure is as follows.

(1) removing the third portion of the conductor layer 170, the impurity amorphous silicon layer 160 and the intrinsic amorphous silicon layer 150 located in the other region (C),                     

(2) removing the second portion 44 of the photosensitive film located in the channel region B,

(3) removing the second portion of the conductor layer 170 and the impurity amorphous silicon layer 160 located in the channel region B, and

(4) Removal of the first portion 42 of the photosensitive film located in the wiring region A. FIG.

Another example of this order is as follows.

(1) removing the third portion of conductor layer 170 located in other region (C),

(2) removing the second portion 44 of the photosensitive film located in the channel region B,

(3) removing the third portions of the impurity amorphous silicon layer 160 and the intrinsic amorphous silicon layer 150 located in the other region (C),

(4) removing the second portion of conductor layer 170 located in channel region B,

(5) removing the first portion 42 of the photosensitive film located in the wiring region A, and

(6) Removal of the second portion of the impurity amorphous silicon layer 160 located in the channel region B. FIG.

The thickness of the first portion 42 of the photoresist film will decrease when the second portion 44 of the photoresist film is removed, but since the thickness of the second portion 44 of the photoresist film is thinner than the first portion 42 of the photoresist film, the lower layer The first portion 42 which prevents it from being removed or etched away is not removed.

By selecting an appropriate etching condition, the impurity amorphous silicon layer 160 and the intrinsic amorphous silicon layer 150 and the second portion 44 of the photoresist film under the third part of the photoresist film may be removed at the same time. Similarly, the portion of the impurity amorphous silicon layer 160 under the second portion 44 of the photosensitive film and the first portion 42 of the photosensitive film may be removed at the same time.

If the photoresist residue remains on the surface of the conductor layer 170, it is removed through ashing.

8A and 8B, a protective film 180 is stacked on the data line 171, the drain electrode 175, and the storage capacitor conductor 177, and then a photosensitive film 60 is applied thereon. And align the photomask 50 thereon. In this case, since the surface of the photosensitive film 60 is applied almost flat regardless of the step of the protective film 180, which is the lower film, that is, regardless of the profile, the photosensitive film 60 has different coating thicknesses depending on the position.

The photomask 50 is composed of a transparent substrate 51 and an opaque light shielding layer 52 thereon, the light-transmitting region D having a width of the light shielding layer 52 not less than a predetermined width and a light shielding layer having a predetermined width or more ( 52 and a transflective area F having a width and a spacing of the light shielding layer 52 having a predetermined value or less and arranged in a matrix form.

The transflective region F faces the edge portion M of the conductor 177 for the storage capacitor, and the transmissive region D is the end portion 129 of the gate line and the end portion 179 of the data line, approximately the gate line. It faces the area surrounded by 121 and the drain line 171, and the other part faces the light shielding area E. FIG.

The transflective region F of the optical mask 50 will be described in more detail with reference to FIG. 13.

As shown in FIG. 13, the semi-transmissive region F of the optical mask 50 includes a plurality of rectangular light blocking portions 55 that can adjust widths of widths and lengths. The width × width of each light blocking portion 55 and the distance between the light blocking portions 55 adjacent to each other, the arrangement form, and the density of the light blocking portions 55 having the same area can be adjusted. The light transmittance in (F) changes. Since the amount of light reaching the photosensitive film 60 is finely adjusted by appropriately adjusting the size, spacing and arrangement form, density, and the like of the light blocking portion 55, the light blocking unit is light-blocked according to the thickness of the photosensitive film 60 to be removed. What is necessary is just to design the part 55. Although the light blocking unit 55 shown in FIG. 13 is a quadrangle, it is obvious that the light blocking unit 55 may have various shapes such as a circle, an ellipse, a triangle, a lozenge, and the like. In FIG. 13, the light blocking portion 55 is formed in the semi-transmissive region F as a quadrangle or the like. On the contrary, the light transmissive portion may be formed as a quadrangle or the like.

When the photosensitive film 60 is irradiated with light through the photomask 50 and developed, the first portion 62 and the second thin portion 64 are thick as shown in FIGS. 9A and 9B. At this time, the photosensitive film portion 64 remaining by the transflective region F is finely adjusted based on the size, spacing and arrangement of the light blocking portions 55 formed in the transmission region of the photomask 50 as described above. The lower layer 180 has a profile almost similar to that of the lower layer 180.

Subsequently, as shown in FIGS. 10A and 10B, a plurality of openings exposing a part of the conductive capacitor conductor 177 by etching the portion of the passivation layer 180 in which the remaining photoresist layer portions 62 and 64 are exposed by an etching mask. The upper sidewalls of the plurality of openings 187 exposing a part of the drain electrode 175 and a part of the gate insulating layer 140 are formed in an area surrounded by the gate 1121 and the gate line 121 and the data line 171. A contact hole 182 is formed to expose the end portion 179 of the data line. In addition, a plurality of contact holes 182 exposing the end portions of the data lines are formed, and upper sidewalls of the plurality of contact holes 181 exposing the gate insulating layer 140 are formed at the end portions 129 of the gate lines. In this case, it is preferable that the etching is performed under the condition that the photoresist portions 62 and 64 are not etched and the protective layer 180 is undercut under the photoresist layers 62 and 64. In this case, the passivation layer 180 may remain without being completely removed, and conversely, the gate insulating layer 140 may be etched to a certain thickness.

Next, as shown in FIGS. 11A and 11B, an ashing process is performed to remove the thin photoresist portion 61. At this time, the thickness of the thick photosensitive film portion 62 is reduced. In addition, the passivation layer portion 180 below the thin photoresist layer portion 61, that is, the passivation layer portion 180 of the edge portion M of the storage capacitor conductor 177 may be reduced to a certain thickness.

12A and 12B, the IZO or ITO or a-ITO films are sputtered to form a transparent conductor film 90. In the case of IZO, a product called indium x-metal oxide (IDIXO) manufactured by Idemitsu Co., Ltd. can be used as a target, and includes In ₂ O ₃ and ZnO, and zinc occupies about 15% of the total amount of indium and zinc. It is preferably in the range of -20 atomic%. In addition, the sputtering temperature of IZO is preferably 250 ° C. or lower to minimize contact resistance with other conductors.

At this time, the transparent conductor film 90 is composed of a first portion 91 positioned on the remaining photoresist layer 62 and a second portion 92 positioned elsewhere, due to the thick thickness of the photoresist layer 62. The difference between the portion 62 and the other portions is severe, and in addition, the passivation layer 180 undercuts the photoresist layers 62 and 64 so that the first portion 91 and the second portion 92 of the transparent conductor film 90 are at least. The portions are separated from each other to form a gap, thereby exposing at least a portion of the side surface of the photoresist portion 62.

Subsequently, when the substrate 110 is immersed in the photoresist film solvent, the solvent penetrates into the photoresist film 62 through the exposed side surface of the remaining photoresist film 62, thereby removing the photoresist part 62. At this time, since the first portion 91 of the transparent conductor film 90 positioned on the photosensitive film 62 also falls off together with the photosensitive film portion 62, only the second portion 92 of the transparent conductor film 90 remains. They form a plurality of pixel electrodes 190 and a plurality of contact auxiliary members 81 and 82 (see FIGS. 1 and 2A and 2B).

At this time, since a part of the edge of the storage capacitor conductor 177 is covered with the protective layer 180, undercut does not occur under the storage capacitor conductor 177, so that the pixel electrode 190 and the storage capacitor conductor 177 ( 177) there is no fear of disconnection.

On the other hand, unlike the method shown in Figs. 9a to 11b, the etching conditions in which the protective film 180, the photosensitive film 61 and the gate insulating film 140 are etched together may be selected to etch these films in one etching. . In this case, the etching is performed until all of the gate insulating layer 140 is etched, and the thickness of the portion of the photoresist layer 61 is appropriately selected so that the portion of the passivation layer 180 under the portion of the photoresist layer 61 remains.

In the exemplary embodiment of the present invention, a slit mask is used near the edge of the storage capacitor conductor 177 to prevent disconnection of the storage capacitor conductor 177 and the pixel electrode 190 due to the undercut. In order to prevent disconnection between the drain electrode 175 and the pixel electrode 190, a slit mask may be used near the edge of the drain electrode 175.

As described above, according to the present invention, the entire process may be simplified by omitting a separate photolithography process for forming the pixel electrode by simultaneously forming the contact hole and the pixel electrode connecting the drain electrode and the pixel electrode. Therefore, manufacturing time and cost of the thin film transistor array panel can be reduced.

In addition, the gate insulating layer is overetched to prevent disconnection between the pixel electrode and the storage capacitor conductor or the drain electrode, thereby increasing the reliability of the operation. Furthermore, since the amount of light transmitted to the photosensitive film is finely adjusted by using a semi-transmissive region in which a light blocking layer having a predetermined size is arranged in a matrix at a predetermined interval instead of a slit shape, the thickness of the photosensitive film applied thereon is increased due to the difference in the difference between the lower layers. Even if different, the thickness of the photoresist film to be removed is changed so that a photoresist film having a constant thickness remains. As a result, the difference in thickness of the photoresist film does not occur, and thus a process margin increases in a subsequent process such as a dry etching process. In addition, the reliability of the manufacturing process of the thin film transistor array panel is improved.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (20)

delete delete delete delete delete delete delete delete delete delete delete Forming a gate line on the substrate, Forming a first insulating film on the gate line; Forming a semiconductor layer on the first insulating film, Forming a conductor for a data line, a drain electrode, and a storage capacitor on the semiconductor layer; Stacking a second insulating film on the data line, the drain electrode, and the conductive capacitor conductor; Developing by irradiating light through a photomask, and including a first portion and a second portion thinner than the first portion on the second insulating layer, wherein the first portion is positioned on the thin film transistor and the second portion is Forming a photosensitive film positioned over a portion of an edge of the conductor for the storage capacitor, The second insulating film and the first insulating film are etched using the photosensitive film including the first portion and the second portion as a mask to expose a part of the drain electrode and a part of the conductive capacitor conductor, while Leaving a portion of the second insulating film under the second portion, Removing the second portion of the photosensitive film, Stacking a conductive film, and Removing the first portion of the photosensitive film to form a pixel electrode connected to the drain electrode and the storage capacitor conductor Including, The photomask includes a light shielding region, a transflective region, and a transmission region, The transflective region has a predetermined area and includes a plurality of light blocking portions arranged in a matrix form. The method of claim 12, And a plurality of light blocking portions having different areas. The method of claim 12, The plurality of light blocking portions have the same area and have different formation densities according to positions. The method of claim 13 or 14, And a plurality of light blocking portions each have a polygonal shape. 16. The method of claim 15, The plurality of light blocking portions each have a rectangular shape. The method of claim 13 or 14, And a plurality of light blocking portions each have a circular shape. delete The method of claim 16, The etching of the second insulating film and the first insulating film includes exposing an end portion of the data line. The method of claim 19, The etching of the second insulating film and the first insulating film further includes etching the first insulating film to expose an end portion of the gate line.

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