KR101046925B1 - Thin film transistor array panel and manufacturing method thereof - Google Patents

Abstract

The present invention relates to a method of manufacturing a thin film transistor array panel, the method comprising: forming a gate line including a gate electrode on a substrate, forming a gate insulating film on the gate line, forming a semiconductor layer on the gate insulating film, and Forming a resistive contact member over the semiconductor layer, forming a data line and a drain electrode including a source electrode on the resistive contact member, depositing a passivation layer, thinner than the first portion and the first portion on the passivation layer Forming a photoresist film having a second portion, exposing a portion of the data line, the drain electrode and the gate line by etching the passivation film and the gate insulating film using the photoresist film as a mask, and removing the second part of the photoresist film Depositing a conductor film, and Removing the second photoresist layer by a step of forming a pixel electrode connected with the drain electrode.

Thin Film Transistor Display Board, Slit, Mask, Lift-Off, Undercut

Description

Thin film transistor array panel and manufacturing method thereof {THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF}

1 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention.

2A and 2B are cross-sectional views of the thin film transistor array panel of FIG. 1 taken along lines IIa-IIa ', IIb-IIb', and IIb'-IIb, respectively.

3, 6, and 9 are layout views at intermediate stages of the method for manufacturing the thin film transistor array panel shown in FIGS. 1 to 2B according to one embodiment of the present invention, respectively, and are arranged in order of process.

4A and 4B are cross-sectional views of the thin film transistor array panel of FIG. 3 taken along lines IVa-IVa ', IVb-IVb', and IVb'-IVb, respectively.

5A and 5B are cross-sectional views of the thin film transistor array panel illustrated in FIG. 3 taken along lines IVa-IVa ', IVb-IVb', and IVb'-IVb, respectively. to be.

7A and 7B are cross-sectional views of the thin film transistor array panel of FIG. 6 taken along lines VIIa-VIIa ', VIIb-VIIb', and VIIb'-VIIb, respectively.

8A and 8B are cross-sectional views of the thin film transistor array panel of FIG. 6 taken along lines VIIa-VIIa ', VIIb-VIIb', and VIIb'-VIIb, respectively, and are views of the next steps of FIGS. 7A and 7B.

10A and 10B are cross-sectional views of the thin film transistor array panel illustrated in FIG. 9 taken along lines Xa-Xa ', Xb-Xb', and Xb'-Xb, respectively.

11A and 11B are cross-sectional views of the thin film transistor array panel illustrated in FIG. 9 taken along the lines Xa-Xa ', Xb-Xb', and Xb'-Xb, respectively. to be.

12A and 12B are cross-sectional views at the next stage of FIGS. 11A and 11B, respectively.

The present invention relates to a thin film transistor array panel and a method of manufacturing the same.

A thin film transistor (TFT) is used as a circuit board for independently driving each pixel in a liquid crystal display device, an organic electroluminescence (EL) display device, or the like.

The thin film transistor array panel includes a gate line transferring a gate signal and a data line transferring a data signal, and includes a thin film transistor connected to the gate line and the data line, a pixel electrode connected to the thin film transistor, and the like.

The thin film transistor is a switching element that controls a data signal transmitted to a pixel electrode through a data line according to a gate signal transmitted through a gate line. The thin film transistor includes a semiconductor layer and a data line forming a channel and a gate electrode connected to a gate line. A source electrode and a drain electrode facing the source electrode are mainly formed around the semiconductor layer.

However, in order to manufacture the thin film transistor array panel, several photolithography processes are required. Each photolithography process includes a number of complex detailed processes, so the number of photolithography processes determines the time and cost of the thin film transistor array panel manufacturing process.

One technical problem to be achieved by the present invention is to simplify the manufacturing process of the thin film transistor array panel.

According to an aspect of the present invention, a thin film transistor array panel manufacturing method includes: forming a gate line including a gate electrode on a substrate, forming a gate insulating layer on the gate line, and forming a semiconductor on the gate insulating layer Forming a layer, forming a resistive contact member on the semiconductor layer, forming a data line and a drain electrode including a source electrode on the resistive contact member, and depositing a passivation layer on the data line and the drain electrode Forming a first portion and a photosensitive film thicker than the first portion on the passivation layer; etching the passivation layer and the gate insulating layer using the photosensitive layer as a mask to form a portion of the gate line and the data line and the drain electrode. Revealing part, the photosensitive Of the depositing step, the conductive film to remove the first portion, and a step of forming a pixel electrode connected with the drain electrode by removing the photoresist.

The photosensitive film is preferably formed using an optical mask having a light shielding region, a transflective region, and a transmissive region.

Removing the second portion of the photoresist may include an ashing process.

A portion of the conductor film positioned above the first portion of the photosensitive film may be removed by a lift-off method when removing the photosensitive film.

The passivation layer has a contact hole that exposes an end portion of the gate line and an end portion of the data line, and is connected to an end portion of the gate line and an end portion of the data line through the contact hole in the pixel electrode forming step. It is preferable to form

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity, and like reference numerals designate like parts throughout the specification. When a part of a layer, film, area, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Hereinafter, a thin film transistor array panel and a method of manufacturing the same according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

First, a thin film transistor array panel according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 to 2B.

FIG. 1 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention, and FIGS. 2A and 2B illustrate IIa-IIa ', IIb-IIb', and IIb'-IIb lines of the thin film transistor array panel of FIG. 1, respectively. It is an example of the sectional drawing shown along the cut.

1 to 2B, a plurality of gate lines 121 are formed on the insulating substrate 110.

The gate line 121 mainly extends in the horizontal direction and transmits a gate signal, and has a wide end portion for connection with another layer or an external device. A portion of each gate line 121 protrudes up and down to form a plurality of gate electrodes 124.

The gate line 121 may be formed of a silver-based metal such as silver (Ag) or a silver alloy, an aluminum-based metal such as aluminum (Al) or an aluminum alloy, and a copper-based metal such as copper (Cu) or a copper alloy, chromium (Cr), or titanium ( Ti), tantalum (Ta), molybdenum (Mo), and alloys thereof. However, the gate line 121 may have a multi-layer structure including two conductive layers (not shown) having different physical properties. In this case, one conductive film is made of a low resistivity metal such as Al-based metal, Ag-based metal or Cu-based metal so that the gate line 121 can reduce signal delay or voltage drop. In contrast, the other conductive film is made of a material having excellent contact properties with other materials, particularly indium tin oxide (ITO) and indium zinc oxide (IZO), such as Cr, Mo, Ti, Ta, or alloys thereof. Examples of a structure in which a low resistivity conductive film comes on the top and a conductive film having excellent contact properties on the bottom include a top layer of a chromium bottom layer and an aluminum-neodymium (Nd) alloy, and vice versa. And an upper film.

The side of the gate line 121 is inclined with respect to the surface of the substrate 110, the inclination angle is in the range of about 30-80 degrees.

A gate insulating layer 140 made of silicon nitride (SiNx) is formed on the gate line 121.

A plurality of linear semiconductors 151 made of hydrogenated amorphous silicon (amorphous silicon is abbreviated a-Si) and the like are formed on the gate insulating layer 140. The linear semiconductor 151 extends mainly in the longitudinal direction from which a plurality of projections 154 extend toward the gate electrode 124.

A plurality of linear and island ohmic contacts 161 and 165 made of a material such as n + hydrogenated amorphous silicon doped with silicide or n-type impurities at a high concentration are formed on the semiconductor 151. have. The linear contact member 161 has a plurality of protrusions 163, and the protrusions 163 and the island contact members 165 are paired and positioned on the protrusions 154 of the semiconductor 151.

Side surfaces of the semiconductor 151 and the ohmic contacts 161 and 165 are also inclined with respect to the surface of the substrate 110, and the inclination angle is 30-80 °.

A plurality of data lines 171 and a plurality of drain electrodes 175 are formed on the ohmic contacts 161 and 165.

The data line 171 transferring the data voltage mainly extends in the vertical direction to cross the gate line 121 and has a wide end portion for connection with another layer or an external device. A plurality of branches extending from the data line 171 toward the drain electrode 175 forms a source electrode 173. Each drain electrode 175 has one end portion 177 that is wider and the other end portion that is linear for connection with another layer, and each source electrode 173 has the other end of the drain electrode 175. It is curved to partially surround the part. The gate electrode 124, the source electrode 173, and the drain electrode 175 form a thin film transistor (TFT) together with the protrusion 154 of the semiconductor 151, and the channel of the thin film transistor is a source. A protrusion 154 is formed between the electrode 173 and the drain electrode 175.

The data line 171 and the drain electrode 175 may be made of a refractory metal such as chromium (Cr), titanium (Ti), tantalum (Ta), molybdenum (Mo), or an alloy thereof. It may have a multilayer film structure including a conductive film made of a silver-based metal or an aluminum-based metal and other conductive films made of chromium (Cr), titanium (Ti), tantalum (Ta), molybdenum (Mo), and alloys thereof. .

Sides of the data line 171 and the drain electrode 175 are also inclined, and the inclination angle is in the range of about 30-80 ° with respect to the horizontal plane.

The ohmic contacts 161 and 165 exist only between the semiconductor 151 below and the data line 171 and the drain electrode 175 above and serve to lower the contact resistance.

The linear semiconductor 151 has substantially the same shape as the data line 171, the drain electrode 175, and the ohmic contacts 161 and 165 thereunder. However, it has a portion exposed between the source electrode 173 and the drain electrode 175, and not covered by the data line 171 and the drain electrode 175.

A passivation layer 180 made of an inorganic material such as silicon nitride is formed on the gate line 121, the data line 171, the entire exposed portion of the semiconductor 154, and a portion of the drain electrode 175. However, the passivation layer 180 is an organic material having excellent planarization characteristics and photosensitivity, but a-Si: C: O and a-Si: O formed by plasma enhanced chemical vapor deposition (PECVD). It may be made of a low dielectric constant insulating material having a dielectric constant of about 4.0 or less, such as: F, and may have a double film structure of a lower inorganic film and an upper organic film.

The passivation layer 180 has a plurality of contact holes 182 and 185 exposing the end portion of the data line 171 and a part of the drain electrode 175, respectively, and the passivation layer 180 and the gate insulating layer 140. ) Has a plurality of contact holes 181 exposing end portions of the gate lines 121.

A plurality of pixel electrodes 190 are formed on the passivation layer 180, and a plurality of contact assistants 81 and 82 are formed in the contact holes 181 and 182 of the passivation layer 180. It is. In this case, the pixel electrode 190 and the contact auxiliary members 81 and 82 are made of a transparent conductor or reflective metal such as IZO, ITO or a-ITO (amorphous ITO), and the boundary of the contact protection members 81 and 82 is It substantially coincides with the boundary of the passivation layer 180.

The pixel electrode 190 is physically and electrically connected to the drain electrode 175 exposed through the contact hole 185 to receive a data voltage from the drain electrode 175.

The pixel electrode 190 applied with the data voltage generates an electric field together with a common electrode (not shown) of another display panel (not shown) to which a common voltage is applied, thereby generating liquid crystal molecules of the liquid crystal layer between the two electrodes. Rearrange them.

The contact auxiliary members 81 and 82 are connected to the ends of the gate lines 121 and the ends of the data lines 171 through the contact holes 181 and 182, respectively. The contact auxiliary members 81 and 82 complement the adhesion between the end portion of the gate line 121 and the end portion of the data line 171 and the external device, and do not necessarily serve to protect them. Whether is optional.

Next, a method of manufacturing the thin film transistor array panel shown in FIGS. 1 to 2B according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 3 to 11B and FIGS. 1 to 2B.                     

3, 6, and 9 are layout views at an intermediate stage of the method for manufacturing the thin film transistor array panel shown in FIGS. 1 to 2B according to one embodiment of the present invention, respectively, and are arranged in the order of the process, and FIG. 4A. 4B is a cross-sectional view of the thin film transistor array panel of FIG. 3 taken along lines IVa-IVa ', IVb-IVb', and IVb'-IVb, respectively, and FIGS. 5A and 5B are thin films of FIG. 4A and 4B are cross-sectional views taken along line IVa-IVa ', IVb-IVb', and IVb'-IVb, respectively, and FIGS. 7A and 7B are the thin films of FIG. FIG. 8 is a cross-sectional view of the transistor panel cut along the lines VIIa-VIIa ', VIIb-VIIb', and VIIb'-VIIb, and FIGS. 8A and 8B illustrate the thin film transistor array panel of FIG. 7A and 7B next steps as cross-sectional views taken along lines VIIb 'and VIIb'-VIIb 10A and 10B are cross-sectional views of the thin film transistor array panel illustrated in FIG. 9 taken along lines Xa-Xa ', Xb-Xb', and Xb'-Xb, respectively. 11B is a cross-sectional view of the thin film transistor array panel illustrated in FIG. 9 taken along the Xa-Xa 'line, the Xb-Xb' line, and the Xb'-Xb line, respectively. And FIG. 12B is a sectional view at the next stage of FIGS. 11A and 11B, respectively, and FIGS. 13A and 13B are a sectional view at the next stage of FIGS. 12A and 12B, respectively.

First, as shown in FIGS. 3 to 4B, a conductive layer such as a metal is deposited on the insulating substrate 110 made of transparent glass to a thickness of 1,000 kPa to 3,000 kPa by a sputtering method, and photo-etched to form a plurality of gates. A plurality of gate lines 121 including the electrodes 124 are formed.                     

Next, as shown in FIGS. 5A and 5B, the gate insulating layer 140, the intrinsic amorphous silicon layer 150, and the impurity amorphous silicon layer 160 are successively laminated by chemical vapor deposition (CVD) or the like. Silicon nitride is preferred as the material of the gate insulating film 140, and the lamination temperature is preferably about 250 to 400 DEG C, and the thickness is about 2,000 to 5,000 GPa. Subsequently, the conductive layer 170 such as metal is deposited to a predetermined thickness by a method such as sputtering, and then a photosensitive film 70 is applied thereon to a thickness of 1 μm to 2 μm.

Thereafter, the photosensitive film 70 is irradiated with light through a photomask (not shown) and then developed. The thickness of the developed photoresist film varies depending on the position. In FIGS. 5A and 5B, the photoresist film 70 is formed of first to third portions whose thickness becomes smaller. The first part located in the area A (hereinafter referred to as the wiring area) and the second part located in the area B (hereinafter referred to as the channel area) are indicated by reference numerals 72 and 74, respectively. Reference numerals are not given to the third portion located in the region, because the third portion has a thickness of zero, so that the lower conductive layer 170 is exposed. The ratio of the thicknesses of the first portion 72 and the second portion 74 is different depending on the process conditions in the subsequent process, but the thickness of the second portion 74 is 1/2 of the thickness of the first portion 72. It is preferable to set it as the following, for example, it is good that it is 4,000 Pa or less.

As such, there may be various methods of varying the thickness of the photoresist film according to the position. The transmissive area as well as the light transmitting area and the light blocking area may be provided in the exposure mask. For example. The semi-transmissive region includes a slit pattern, a lattice pattern, or a thin film having a medium or medium transmittance. When using the slit pattern, it is preferable that the width of the slits and the interval between the slits are smaller than the resolution of the exposure machine used for the photographic process. Another example is to use a photoresist film that can be reflowed. That is, a thin portion is formed by forming a reflowable photoresist film with a conventional mask having only a transmissive area and a light shielding area, and then reflowing so that the photoresist film flows into an area where no photoresist film remains.

Given the appropriate process conditions, the underlying layers may be selectively etched due to the difference in thickness of the photoresist films 72 and 74. Therefore, the plurality of drain electrodes 175 including the plurality of data lines 171 including the plurality of source electrodes 173 and the extension 177 as shown in FIGS. 6 to 7B through a series of etching steps. A plurality of linear resistive contact members 161 and a plurality of island resistive contact members 165, each of which includes a plurality of protrusions 163, and a plurality of linear semiconductors 151 that include a plurality of protrusions 154. To form.

For convenience of description, portions of the conductor layer 170 located in the wiring region A, the impurity amorphous silicon layer 160, and the intrinsic amorphous silicon layer 150 are referred to as first portions, and the conductor layer located in the channel region B. A portion of the impurity amorphous silicon layer 160 and the intrinsic amorphous silicon layer 150 is referred to as a second portion, and the conductor layer 170 located in the other region C, the impurity amorphous silicon layer 160, and the intrinsic A part of the amorphous silicon layer 150 is called a third part.

One example of the order of forming such a structure is as follows.

(1) removing the third portion of the conductor layer 170, the impurity amorphous silicon layer 160 and the amorphous silicon layer 150 located in the other region (C),

(2) removing the second portion 74 of the photosensitive film located in the channel region B,

(3) removing the second portion of the conductor layer 170 and the impurity amorphous silicon layer 160 located in the channel region B, and

(4) Removal of the first portion 72 of the photosensitive film located in the wiring region A. FIG.

Another example of this order is as follows.

(1) removing the third portion of conductor layer 170 located in other region (C),

(2) removing the second portion 74 of the photosensitive film located in the channel region B,

(3) removing the third portions of the impurity amorphous silicon layer 160 and the amorphous silicon layer 150 located in the other region (C),

(4) removing the second portion of conductor layer 170 located in channel region B,

(5) removing the first portion 72 of the photosensitive film located in the wiring region A, and

(6) Removal of the second portion of the impurity amorphous silicon layer 160 located in the channel region B. FIG.

The thickness of the first portion 72 of the photoresist film will decrease when the second portion 74 of the photoresist film is removed, but since the thickness of the second portion 74 of the photoresist film is thinner than the first portion 72 of the photoresist film, the lower layer The first portion 72 that prevents it from being removed or etched away is not removed.

By selecting an appropriate etching condition, a portion of the impurity amorphous silicon layer 160 and the intrinsic amorphous silicon layer 150 and the second portion 74 of the photoresist film under the third portion of the photoresist film may be removed at the same time. Similarly, the portion of the impurity amorphous silicon layer 160 under the second portion 74 of the photosensitive film and the first portion 72 of the photosensitive film can be removed at the same time. For example, when a mixed gas of SF ₆ and HCl or a mixed gas of SF ₆ and O ₂ is used, the photosensitive film and the intrinsic amorphous silicon layer 150 (or impurity amorphous silicon layer 160) are etched at almost the same etching rate. can do.

If the photoresist residue remains on the surface of the conductor layer 170, it is removed through ashing.

Subsequently, as shown in FIGS. 8A and 8B, the passivation layer 180 is stacked on the data line 171 and the drain electrode 175, and then the photoresist layer 50 is coated thereon, and the photomask 40 is applied thereon. Sort it.

The photomask 40 is composed of a transparent substrate 41 and an opaque light shielding layer 42 thereon. The light shielding layer 42 has a transparent region 41 having a width of at least a predetermined width and a light shielding layer having a predetermined width or more ( The light shielding area E with 42, and the slit-like transflective area F whose width or space | interval of the light shielding layer 42 is below a predetermined value is included. The transflective region F faces the region surrounded by the gate line 121 and the data line 171, and the transmissive region D is an end portion of the gate line 121, an end portion of the data line 171, and a drain. A part of the electrode 175 is faced, and the other part thereof is faced to the light blocking area E. FIG.

When the photosensitive organic film 50 is irradiated with light through the photomask 40 and developed, the photosensitive film 50 disappears, and the hatched portions in FIGS. 8A and 8B mean portions that disappear after development.                     

Next, as shown in FIGS. 9 to 10B, the passivation layer 180 and the gate insulating layer 140 below are etched using the remaining photoresist layer portions 52 and 54 as an etch mask, and the end portion and data of the gate line 121 are etched. Contact holes 181, 182, and 185 are formed to expose an end portion of the line 171 and a part of the drain electrode 175.

Next, an ashing process is performed to reduce the thickness of the photosensitive film portion 52. At this time, the ashing end point is a time point where the thin photosensitive film portion 54 is completely removed.

12A and 12B, the IZO or ITO or a-ITO films are sputtered to form a transparent conductor film 90. In the case of IZO, a product called indium x-metal oxide (IDIXO) manufactured by Idemitsu Co., Ltd. can be used as a target, and includes In ₂ O ₃ and ZnO, and zinc occupies about 15 indium and zinc. It is preferably in the range of -20 atomic%. In addition, the sputtering temperature of IZO is preferably 250 ° C. or lower to minimize contact resistance with other conductors.

In this case, the transparent conductor film 90 includes a first portion 91 positioned on the passivation layer 180 and a second portion 92 positioned elsewhere. 52) and the other portions are so severe that the first portion 91 and the second portion 92 of the transparent conductor film 90 are at least partially separated from each other, resulting in a gap, whereby the side surface of the photoresist portion 52 Partly exposed.

Subsequently, when the substrate 110 is immersed in the photoresist solvent, the solvent penetrates into the photoresist part 52 through the exposed side surface of the remaining photoresist part 52, thereby removing the photoresist part 52. At this time, since the first part 91 of the transparent conductor film 90 positioned on the remaining photoresist film part 52 also falls off together with the photoresist film part 52 in a lift-off manner, the transparent conductor film eventually becomes Only the second portion 92 of 90 remains, and these form a plurality of pixel electrodes 190 and a plurality of contact assistants 81 and 82 (see FIGS. 1 and 2A and 2B).

In the present exemplary embodiment, the data line 171, the drain electrode 175, the ohmic contacts 161 and 165 and the semiconductor 151 under the same are formed in one photo process, and the pixel electrode 190 and the contact auxiliary member are formed. A separate photographic step for forming (81, 82) is omitted to simplify the overall process.

Meanwhile, as described with reference to FIG. 10B in the present embodiment, in the present embodiment, the passivation layer 180 and the gate covering the end portion of the gate line 121 and the end portion of the data line 171 by the first photoresist pattern. Although the case where the insulating film 140 is etched is shown at the same time, the present invention is not limited thereto.

For example, instead of removing all of the photoresist film 50 on the portion that will be a contact hole 182 exposing a part of the data line 171, the photoresist films 52 and 54 are left first. The protective layer 180 is etched using the mask to complete the contact hole 185, and the gate insulating layer 140 of the portion where the contact hole 181 is to be formed is exposed. The photoresist second portion 54 is removed and the exposed passivation layer 180 and the gate insulation layer 140 are etched to complete the contact holes 181 and 182.

 As described above, according to the present invention, the contact hole connecting the drain electrode and the pixel electrode and the pixel electrode are formed in one photolithography process, thereby eliminating a separate photolithography process for forming the pixel electrode, thereby simplifying the entire process. Can be. Therefore, manufacturing time and cost of the thin film transistor array panel can be reduced.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (11)

delete delete delete delete delete Forming a gate line including a gate electrode on the substrate, Forming a gate insulating film on the gate line; Forming a semiconductor layer on the gate insulating film, Forming an ohmic contact on the semiconductor layer, Forming a data line and a drain electrode including a source electrode on the ohmic contact, Depositing a passivation layer on the data line and the drain electrode; Forming a first photoresist layer on the passivation layer; Etching the passivation layer using the first photoresist layer as a mask to form a first contact hole for exposing a part of the drain electrode, and simultaneously exposing the portion of the gate insulating layer on the portion of the gate line; Changing the first photoresist to form a second photoresist; Forming second and third contact holes exposing at least a portion of the gate line and at least a portion of the data line by etching the passivation layer and the gate insulating layer using the second photoresist layer as a mask, Depositing a conductor film, and Removing the second photoresist layer to form a pixel electrode connected to the drain electrode Method of manufacturing a thin film transistor array panel comprising a. In claim 6, The first photoresist film is formed using a photomask having a light shielding region, a transflective region, and a transmissive region. 8. The method of claim 7, The forming of the second photoresist film includes an ashing process. In claim 8, And the ashing process proceeds to the time point of removing the portion of the first photoresist layer positioned in the region corresponding to the transflective region of the photomask. In claim 6, The portion of the conductor layer on the second photoresist layer is removed in a lift-off manner when the first photoresist layer is removed. In claim 6, And forming a contact auxiliary member connected to an end portion of the gate line and an end portion of the data line through the contact hole in the pixel electrode forming step.

Images