KR100844936B1 - Semicoductor device and Method for fabricating the same - Google Patents

Semicoductor device and Method for fabricating the same Download PDF

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KR100844936B1
KR100844936B1 KR1020020042310A KR20020042310A KR100844936B1 KR 100844936 B1 KR100844936 B1 KR 100844936B1 KR 1020020042310 A KR1020020042310 A KR 1020020042310A KR 20020042310 A KR20020042310 A KR 20020042310A KR 100844936 B1 KR100844936 B1 KR 100844936B1
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interlayer insulating
bit line
landing plug
field oxide
insulating film
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KR1020020042310A
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Korean (ko)
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KR20040008642A (en
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장헌용
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 비트라인콘택과 랜딩플러그의 접촉면적 부족으로 인한 동작속도 저하를 방지하는데 적합한 반도체소자의 제조 방법을 제공하기 위한 것으로, 본 발명의 반도체소자의 제조 방법은 반도체기판에 활성영역을 정의하는 필드산화막을 형성하는 단계, 상기 필드산화막을 포함한 상기 반도체기판상에 제1층간절연막을 형성하는 단계, 상기 제1 층간절연막을 관통하여 상기 활성영역의 전영역 및 상기 필드산화막의 일부 영역 상부까지 걸치는 랜딩플러그를 형성하는 단계, 상기 랜딩플러그를 포함한 상기 제1 층간절연막상에 제2 층간절연막을 형성하는 단계, 및 상기 제2 층간절연막과 상기 랜딩플러그를 동시에 관통하여 상기 필드산화막에 접하는 비트라인을 형성하는 단계을 포함한다.
The present invention is to provide a method for manufacturing a semiconductor device suitable for preventing a decrease in operating speed due to the lack of contact area between the bit line contact and the landing plug, the method of manufacturing a semiconductor device of the present invention is to define an active region on the semiconductor substrate Forming a field oxide film, forming a first interlayer insulating film on the semiconductor substrate including the field oxide film, penetrating through the first interlayer insulating film, and extending over the entire area of the active region and a part of the field oxide film; Forming a landing plug, forming a second interlayer insulating film on the first interlayer insulating film including the landing plug, and simultaneously passing through the second interlayer insulating film and the landing plug to be in contact with the field oxide film. Forming a step.

비트라인, 동작속도, 콘택저항, 랜딩플러그Bit line, speed, contact resistance, landing plug

Description

반도체소자 및 그 제조 방법{Semicoductor device and Method for fabricating the same} Semiconductor device and method for manufacturing the same {Semicoductor device and Method for fabricating the same}             

도 1a는 종래기술에 따른 반도체소자를 도시한 도면, Figure 1a is a view showing a semiconductor device according to the prior art,

도 1b는 도 1a의 A-A'선에 따른 단면도,1B is a cross-sectional view taken along line AA ′ of FIG. 1A;

도 2a 내지 도 2d는 본 발명의 실시예에 따른 반도체소자의 제조 방법을 도시한 공정 단면도, 2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention;

도 3a 내지 도 3e는 도 2c의 B-B'선에 따른 반도체소자의 제조 방법을 도시한 공정 단면도.
3A to 3E are cross-sectional views illustrating a method of manufacturing a semiconductor device along the line BB ′ of FIG. 2C.

*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

31 : 반도체기판 32 : 필드산화막31 semiconductor substrate 32 field oxide film

37a : 제1 층간절연막 38a : 랜딩플러그37a: first interlayer insulating film 38a: landing plug

39 : 제2 층간절연막 40 : 배리어메탈39: second interlayer insulating film 40: barrier metal

41 : 비트라인배선막 42 : 캡핑막41: bit line wiring film 42: capping film

43 : 스페이서
43: spacer

본 발명은 반도체 제조 기술에 관한 것으로, 특히 비트라인콘택의 저항을 감소시키도록 한 반도체소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method of manufacturing a semiconductor device to reduce the resistance of a bit line contact.

반도체 소자의 집적도가 증가함에 따라 게이트라인과 같은 전도라인 간의 간극이 좁아지고 있으며, 이에 따라 콘택 공정 마진이 줄어들고 있다. 이러한 콘택 공정 마진을 확보하기 위하여 자기정렬콘택(Self Aligned Contact; SAC) 공정을 진행하고 있다. 한편, 통상의 자기정렬콘택 공정은 배리어 질화막(barrier nitride)을 사용하여 콘택 식각 공정의 마진을 증대시키는 방법과 랜딩플러그 콘택(Landing plug contact; LPC)을 사용하여 오버레이 마진을 증대시키는 방법을 사용하고 있다.As the degree of integration of semiconductor devices increases, the gap between conductive lines such as gate lines is narrowing, and thus, contact process margins are decreasing. In order to secure such a contact process margin, a self aligned contact (SAC) process is being performed. On the other hand, the conventional self-aligned contact process uses a method of increasing the margin of the contact etching process using a barrier nitride film and a method of increasing the overlay margin using a landing plug contact (LPC). have.

도 1a는 종래기술에 따른 반도체소자를 도시한 도면이고, 도 1b는 도 1a의 A-A'선에 따른 단면도이다.1A is a diagram illustrating a semiconductor device according to the related art, and FIG. 1B is a cross-sectional view taken along line AA ′ of FIG. 1A.

도 1a를 참조하면, 필드산화막(12)이 형성된 반도체기판(11)상에 게이트산화막(13), 게이트전극(14) 및 하드마스크(15)의 순서로 적층된 워드라인이 형성되고, 워드라인의 양측벽에 스페이서(16)가 형성되며, 워드라인 사이의 반도체기판(11)에 랜딩플러그(18a,18b)가 연결되며, 랜딩플러그(18a,18b)가 형성되지 않은 워드라인들 사이는 제1 층간절연막(ILD, 17)이 채워져 있다. 여기서, 랜딩플러그(18a,18b)와 제1 층간절연막(17)은 워드라인 표면을 노출시키면서 평탄화되어 있으며, 랜딩 플러그(18a,18b)는 비트라인이 콘택될 랜딩플러그(18a)와 스토리지노드가 콘택될 랜딩플러그(18b)로 구분된다.Referring to FIG. 1A, word lines stacked in the order of the gate oxide film 13, the gate electrode 14, and the hard mask 15 are formed on the semiconductor substrate 11 on which the field oxide film 12 is formed. Spacers 16 are formed on both side walls of the substrate, and landing plugs 18a and 18b are connected to the semiconductor substrate 11 between the word lines, and between the word lines where the landing plugs 18a and 18b are not formed. One interlayer insulating film ILD 17 is filled. Here, the landing plugs 18a and 18b and the first interlayer insulating layer 17 are planarized while exposing the word line surface, and the landing plugs 18a and 18b are connected to the landing plug 18a and the storage node to which the bit lines are to be contacted. The landing plug 18b to be contacted is divided.

그리고, 제1 층간절연막(17)과 랜딩플러그(18a,18b)를 포함한 전면에 제2 층간절연막(19)이 형성되고, 제2 층간절연막(19)을 관통하는 비트라인콘택홀을 통해 배리어메탈(20)을 사이에 두고 비트라인이 랜딩플러그(18a)에 연결된다. 여기서, 비트라인은 비트라인배선막(21)과 캡핑막(22)의 적층구조물이고 적층구조물의 측벽에 스페이서(23)가 형성된다.A second interlayer insulating film 19 is formed on the entire surface including the first interlayer insulating film 17 and the landing plugs 18a and 18b, and the barrier metal is formed through the bit line contact hole penetrating the second interlayer insulating film 19. The bit line is connected to the landing plug 18a with the gap 20 therebetween. Here, the bit line is a stacked structure of the bit line wiring film 21 and the capping film 22 and a spacer 23 is formed on the sidewall of the stacked structure.

도 1b를 참조하면, 비트라인이 콘택될 랜딩플러그(18a)가 반도체기판(11)의 활성영역은 물론 필드산화막(12)의 일부분까지 걸쳐서 형성되고, 랜딩플러그(18a)의 노즈부위에만 비트라인이 연결된다.Referring to FIG. 1B, the landing plug 18a to which the bit line is to be contacted is formed not only in the active region of the semiconductor substrate 11 but also to a part of the field oxide film 12, and the bit line only at the nose portion of the landing plug 18a. Is connected.

그러나, 상술한 종래기술은 비트라인콘택을 랜딩플러그의 노즈(nose) 부위에만 형성되도록 하므로, 비트라인콘택과 랜딩플러그의 접촉면적이 크지 못하여 콘택체인(contact chain) 저항 특성이 나쁘다. 결국, 소자의 동작속도가 저하될 수밖에 없다.
However, the above-described prior art allows the bit line contact to be formed only at the nose portion of the landing plug, so that the contact area between the bit line contact and the landing plug is not large, resulting in poor contact chain resistance characteristics. As a result, the operation speed of the device is inevitably lowered.

본 발명은 상기한 종래기술의 문제점을 해결하기 위해 안출한 것으로, 비트라인콘택과 랜딩플러그의 접촉면적 부족으로 인한 동작속도 저하를 방지하는데 적합한 반도체소자 및 그 제조 방법을 제공함에 그 목적이 있다.
The present invention has been made to solve the above problems of the prior art, and an object of the present invention is to provide a semiconductor device and a method of manufacturing the same suitable for preventing a decrease in operating speed due to the lack of contact area between the bit line contact and the landing plug.

상기 목적을 달성하기 위한 본 발명의 반도체소자는 반도체기판, 상기 반도체기판에 형성되어 활성영역을 정의하는 필드산화막, 상기 활성영역의 전영역 및 상기 필드산화막의 일부 영역 상부까지 걸쳐서 형성된 랜딩플러그, 상기 랜딩플러그를 절연시키는 상기 필드산화막의 나머지 영역상의 제1 층간절연막, 상기 랜딩플러그를 포함한 상기 제1 층간절연막상에 형성된 제2 층간절연막, 및 상기 제2 층간절연막과 상기 랜딩플러그를 동시에 관통하여 상기 필드산화막에 접하는 비트라인을 포함함을 특징으로 한다.The semiconductor device of the present invention for achieving the above object is a semiconductor substrate, a field oxide film formed on the semiconductor substrate to define an active region, a landing plug formed over the entire region of the active region and the upper portion of the field oxide film, the A first interlayer insulating film on the remaining region of the field oxide film that insulates the landing plug, a second interlayer insulating film formed on the first interlayer insulating film including the landing plug, and simultaneously passes through the second interlayer insulating film and the landing plug. And a bit line in contact with the field oxide layer.

그리고, 본 발명의 반도체소자의 제조 방법은 반도체기판에 활성영역을 정의하는 필드산화막을 형성하는 단계, 상기 필드산화막을 포함한 상기 반도체기판상에 제1층간절연막을 형성하는 단계, 상기 제1 층간절연막을 관통하여 상기 활성영역의 전영역 및 상기 필드산화막의 일부 영역 상부까지 걸치는 랜딩플러그를 형성하는 단계, 상기 랜딩플러그를 포함한 상기 제1 층간절연막상에 제2 층간절연막을 형성하는 단계, 및 상기 제2 층간절연막과 상기 랜딩플러그를 동시에 관통하여 상기 필드산화막에 접하는 비트라인을 형성하는 단계을 포함함을 특징으로 한다.
The method of manufacturing a semiconductor device of the present invention includes forming a field oxide film defining an active region on a semiconductor substrate, forming a first interlayer insulating film on the semiconductor substrate including the field oxide film, and forming the first interlayer insulating film. Forming a landing plug that extends through the entire region of the active region and an upper portion of the field oxide layer through a gap; forming a second interlayer insulating layer on the first interlayer insulating layer including the landing plug; and And forming a bit line through the two interlayer insulating film and the landing plug at the same time to contact the field oxide film.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

도 2a 내지 도 2c는 본 발명의 실시예에 따른 반도체소자의 제조 방법을 도 시한 레이아웃 공정도이고, 도 3a 내지 도 3e는 도 2c의 B-B'선에 따른 반도체소자의 제조 방법을 도시한 공정 단면도이다.2A to 2C are layout process diagrams illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention, and FIGS. 3A to 3E are diagrams illustrating a method of manufacturing a semiconductor device along line B-B 'of FIG. 2C. It is a cross section.

도 2a 및 도 3a에 도시된 바와 같이, 반도체기판(31)에 필드산화막(32)을 형성한 후, 반도체기판(31)상에 게이트산화막(33), 게이트전극(34) 및 하드마스크(35)의 순서로 적층된 워드라인(WL)을 형성한다.As shown in FIGS. 2A and 3A, after the field oxide film 32 is formed on the semiconductor substrate 31, the gate oxide film 33, the gate electrode 34, and the hard mask 35 are formed on the semiconductor substrate 31. Stacked word lines WL are formed in order of

여기서, 워드라인(WL)을 형성하는 방법은, 먼저 게이트산화막(33), 게이트전극(34)용 도전막 및 하드마스크(35)를 차례로 증착한 후, 하드마스크(35)상에 포토레지스트를 도포하고 노광 및 현상을 통해 게이트라인을 정의하는 마스크를 형성한다. 다음으로, 마스크를 식각마스크로 하여 하드마스크(35)를 먼저 식각한 후 마스크를 제거하고, 식각처리된 하드마스크(35)를 식각마스크로 게이트전극(34)용 도전막과 게이트산화막(33)을 식각하여 워드라인을 형성한다.The word line WL may be formed by first depositing a gate oxide film 33, a conductive film for the gate electrode 34, and a hard mask 35, and then depositing a photoresist on the hard mask 35. And a mask defining the gate line through exposure and development. Next, the hard mask 35 is etched first using the mask as an etch mask, and then the mask is removed. The conductive film and gate oxide film 33 for the gate electrode 34 are etched using the etched hard mask 35 as an etch mask. Is etched to form a word line.

한편, 하드마스크(35)는 질화막을 이용한다.On the other hand, the hard mask 35 uses a nitride film.

다음으로, 워드라인의 양측벽에 접하는 스페이서(36)를 형성한 후, 스페이서(36)를 포함한 전면에 제1 층간절연막(ILD, 37)을 형성한다.Next, after forming the spacers 36 in contact with both side walls of the word line, first interlayer insulating films ILD 37 are formed on the entire surface including the spacers 36.

도 2b 및 도 3b에 도시된 바와 같이, 반도체기판(31)에 연결되는 랜딩플러그(38a, 38b)를 형성한다. 도면에 도시되지 않았지만, 랜딩플러그(38a, 38b)를 형성하는 방법은, 먼저 제1 층간절연막(37)상에 랜딩플러그를 정의하는 콘택마스크를 형성한 후, 이 콘택마스크를 식각마스크로 하여 제1 층간절연막(37)을 식각하므로써 워드라인 사이의 반도체기판(31)을 노출시키는 콘택홀을 형성한다. 다음에, 콘택마스크를 제거한 후, 콘택홀을 포함한 전면에 폴리실리콘막을 증착한 다. 그리고, 하드마스크(34)의 표면이 드러날때까지 제1 층간절연막(37)을 화학적기계적연마(CMP)하여 랜딩플러그(38a, 38b)를 형성한다. 여기서, 랜딩플러그(38a, 38b)는 후속 비트라인이 콘택될 랜딩플러그(38a) 및 스토리지노드가 콘택될 랜딩플러그(38b)이고, 화학적기계적연마후 제1 층간절연막(37a)이 잔류한다. 그리고, 스토리지노드가 콘택될 랜딩플러그(38b)는 활성영역상에만 형성되지만, 도 3b에 도시된 바와 같이, 비트라인이 콘택될 랜딩플러그(38a)는 반도체기판(31)의 활성영역과 필드산화막(32)의 일부분까지 걸쳐서 형성되며, 이웃한 랜딩플러그(38a)와는 제1 층간절연막(37)에 의해 절연되고 있다.As shown in FIGS. 2B and 3B, landing plugs 38a and 38b connected to the semiconductor substrate 31 are formed. Although not shown in the drawing, the method for forming the landing plugs 38a and 38b is formed by first forming a contact mask defining a landing plug on the first interlayer insulating film 37, and then using the contact mask as an etch mask. The first interlayer insulating film 37 is etched to form contact holes for exposing the semiconductor substrate 31 between the word lines. Next, after removing the contact mask, a polysilicon film is deposited on the entire surface including the contact hole. Then, the first interlayer insulating layer 37 is chemically mechanically polished (CMP) until the surface of the hard mask 34 is exposed to form landing plugs 38a and 38b. Here, the landing plugs 38a and 38b are the landing plug 38a to be contacted by the subsequent bit line and the landing plug 38b to be contacted by the storage node, and the first interlayer insulating film 37a remains after chemical mechanical polishing. The landing plug 38b to which the storage node is to be contacted is formed only on the active region. However, as shown in FIG. 3B, the landing plug 38a to which the bit line is to be contacted is the active region and the field oxide film of the semiconductor substrate 31. It is formed over a part of 32 and is insulated from the neighboring landing plug 38a by the first interlayer insulating film 37.

도 2c 및 도 3c에 도시된 바와 같이, 랜딩플러그(38a,38b)가 형성된 반도체기판(31)의 전면에 제2 층간절연막(39)을 형성한다.As shown in FIGS. 2C and 3C, a second interlayer insulating film 39 is formed on the entire surface of the semiconductor substrate 31 on which the landing plugs 38a and 38b are formed.

도 2d, 도 3d 및 도 3e에 도시된 바와 같이, 제2 층간절연막(39)을 식각하여 비트라인이 콘택될 랜딩플러그(38a)를 노출시키는 비트라인콘택홀(X)을 형성한 후, 비트라인콘택홀(X)을 통해 랜딩플러그(38a)에 연결되는 비트라인을 형성한다. 이때, 비트라인은 배리어메탈(40)을 사이에 두고 랜딩플러그(38a)와 연결되며, 비트라인배선막(41)과 캡핑막(42)의 적층물이며, 적층물의 측벽에 스페이서(43)가 구비된다.As shown in FIGS. 2D, 3D, and 3E, the second interlayer insulating layer 39 is etched to form the bit line contact hole X exposing the landing plug 38a to which the bit line is to be contacted. A bit line is connected to the landing plug 38a through the line contact hole X. In this case, the bit line is connected to the landing plug 38a with the barrier metal 40 interposed therebetween, and the bit line is a laminate of the bit line wiring layer 41 and the capping layer 42. It is provided.

도 3d 내지 도 3e를 참조하면, 제2 층간절연막(39)를 식각하고 연속해서 드러나는 랜딩플러그(38a)를 추가로 식각하여 필드산화막(32) 상부를 노출시키는 비트라인콘택홀(X)을 형성한다.3D to 3E, the bit line contact hole X exposing the field oxide layer 32 is formed by etching the second interlayer insulating layer 39 and further etching the landing plug 38a that is continuously exposed. do.

다음에, 비트라인콘택홀내에만 배리어메탈(40)을 잔류시킨 후, 비트라인배선 막(41)과 캡핑막(42)으로 이루어진 비트라인을 형성하고, 비트라인의 측벽에 스페이서(43)를 형성한다.Next, after the barrier metal 40 is left only in the bit line contact hole, a bit line formed of the bit line wiring film 41 and the capping film 42 is formed, and the spacer 43 is formed on the sidewall of the bit line. Form.

결국, 비트라인을 이루는 배리어메탈(40)의 일측면은 랜딩플러그(38a)의 측면에 접하고, 배리어메탈(40)의 타측면은 제1 층간절연막(37a)에 접한다.As a result, one side of the barrier metal 40 constituting the bit line is in contact with the side surface of the landing plug 38a, and the other side of the barrier metal 40 is in contact with the first interlayer insulating layer 37a.

전술한 실시예에 의하면, 필드산화막(32) 상부까지 비트라인콘택홀(X)을 형성하므로써 비트라인과 랜딩플러그(38a)간 접촉면적을 증대시킨다. 또한, 종래에는 비트라인콘택 크기가 비트라인 길이(length)보다 컸지만, 본 발명을 이용하면, 비트라인콘택홀의 크기를 줄이는 효과도 얻을 수 있다.According to the above embodiment, the contact area between the bit line and the landing plug 38a is increased by forming the bit line contact hole X up to the field oxide film 32. In addition, although the bit line contact size is larger than the bit line length in the related art, an effect of reducing the size of the bit line contact hole can be obtained by using the present invention.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.
Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 본 발명은 랜딩플러그의 측면에도 비트라인을 접촉시키므로써 비트라인과 랜딩플러그간 접촉면적을 증대시켜 데이터가 입출력되는 비트라인의 동작속도를 향상시킬 수 있는 효과가 있다.
The present invention described above has the effect of increasing the contact area between the bit line and the landing plug by contacting the bit line on the side of the landing plug, thereby improving the operation speed of the bit line through which data is input and output.

Claims (5)

반도체기판;Semiconductor substrates; 상기 반도체기판에 형성되어 활성영역을 정의하는 필드산화막;A field oxide film formed on the semiconductor substrate to define an active region; 상기 활성영역의 전영역 및 상기 필드산화막의 일부 영역 상부까지 걸쳐서 형성된 랜딩플러그; A landing plug formed over an entire region of the active region and an upper portion of a portion of the field oxide layer; 상기 랜딩플러그를 절연시키는 상기 필드산화막의 나머지 영역상의 제1 층간절연막;A first interlayer insulating film on the remaining region of the field oxide film that insulates the landing plug; 상기 랜딩플러그를 포함한 상기 제1 층간절연막상에 형성된 제2 층간절연막; 및A second interlayer insulating film formed on the first interlayer insulating film including the landing plug; And 상기 제2 층간절연막과 상기 랜딩플러그를 동시에 관통하여 상기 필드산화막에 접하는 비트라인A bit line contacting the field oxide layer through the second interlayer insulating layer and the landing plug at the same time 을 포함함을 특징으로 하는 반도체소자.A semiconductor device comprising a. 제1항에 있어서,The method of claim 1, 상기 비트라인의 일측면은 상기 랜딩플러그의 측면에 접하고, 상기 비트라인의 타측면은 상기 제1 층간절연막에 접하는 것을 특징으로 하는 반도체소자.And one side of the bit line is in contact with a side surface of the landing plug, and the other side of the bit line is in contact with the first interlayer insulating layer. 제1항에 있어서,The method of claim 1, 상기 비트라인은 배리어메탈을 포함하는 다층구조물이고, 상기 배리어메탈은 상기 랜딩플러그의 측면과 필드산화막의 상면, 제1,2 층간절연막의 측면에 동시에 접하는 것을 특징으로 하는 반도체소자.The bit line is a multi-layer structure including a barrier metal, the barrier metal is in contact with the side of the landing plug, the top surface of the field oxide film, the side of the first and second interlayer insulating film at the same time. 반도체기판에 활성영역을 정의하는 필드산화막을 형성하는 단계;Forming a field oxide film defining an active region on the semiconductor substrate; 상기 필드산화막을 포함한 상기 반도체기판상에 제1층간절연막을 형성하는 단계:Forming a first interlayer insulating film on the semiconductor substrate including the field oxide film: 상기 제1 층간절연막을 관통하여 상기 활성영역의 전영역 및 상기 필드산화막의 일부 영역 상부까지 걸치는 랜딩플러그를 형성하는 단계;Forming a landing plug that penetrates through the first interlayer insulating layer and extends to an entire region of the active region and an upper portion of the field oxide layer; 상기 랜딩플러그를 포함한 상기 제1 층간절연막상에 제2 층간절연막을 형성하는 단계; 및Forming a second interlayer insulating film on the first interlayer insulating film including the landing plug; And 상기 제2 층간절연막과 상기 랜딩플러그를 동시에 관통하여 상기 필드산화막에 접하는 비트라인을 형성하는 단계Forming a bit line through the second interlayer insulating film and the landing plug at the same time to contact the field oxide film 을 포함함을 특징으로 하는 반도체소자의 제조 방법.Method of manufacturing a semiconductor device comprising a. 제4항에 있어서,The method of claim 4, wherein 상기 비트라인을 형성하는 단계는,Forming the bit line, 상기 제2 층간절연막과 상기 랜딩플러그를 동시에 식각하여 상기 필드산화막의 일부 영역을 노출시키는 비트라인콘택홀을 형성하는 단계;Simultaneously etching the second interlayer dielectric layer and the landing plug to form a bit line contact hole exposing a portion of the field oxide layer; 상기 비트라인콘택홀을 통해 상기 필드산화막에 접하는 비트라인을 형성하는 단계Forming a bit line in contact with the field oxide layer through the bit line contact hole 를 포함함을 특징으로 하는 반도체소자의 제조 방법.Method of manufacturing a semiconductor device, characterized in that it comprises a.
KR1020020042310A 2002-07-19 2002-07-19 Semicoductor device and Method for fabricating the same KR100844936B1 (en)

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US6074918A (en) * 1995-06-23 2000-06-13 Samsung Electronics Co., Ltd. Methods of fabrication DRAM transistor cells with a self-aligned storage electrode contact
US5814862A (en) * 1995-08-03 1998-09-29 Taiwan Semiconductor Manufacturing Company, Ltd. Metallic source line and drain plug with self-aligned contacts for flash memory device
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