KR100825011B1 - A method for forming trench type isolation layer in semiconductor device - Google Patents

A method for forming trench type isolation layer in semiconductor device Download PDF

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KR100825011B1
KR100825011B1 KR1020020033468A KR20020033468A KR100825011B1 KR 100825011 B1 KR100825011 B1 KR 100825011B1 KR 1020020033468 A KR1020020033468 A KR 1020020033468A KR 20020033468 A KR20020033468 A KR 20020033468A KR 100825011 B1 KR100825011 B1 KR 100825011B1
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trench
heat treatment
silicon substrate
semiconductor device
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KR20030095864A (en
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김명진
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls

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Abstract

본 발명은 반도체 기술에 관한 것으로, 특히 소자간의 전기적 분리를 위한 소자분리막 형성 공정에 관한 것이며, 더 자세히는 트렌치형 소자분리막 형성방법에 관한 것이다. 본 발명은 트렌치 영역의 실리콘 기판의 산화를 방지하고, 실리콘 기판의 표면 거칠기를 완화시킬 수 있는 반도체 소자의 트렌치형 소자분리막 형성방법을 제공하는데 그 목적이 있다. 본 발명은 트렌치 식각에 따르는 손상을 방지하기 위한 트렌치 측벽 희생산화 공정을 생략하고, 이를 대신하여 트렌치 식각 후 H2/NH3 분위기에서 열처리를 수행한다. H2 열처리는 실리콘 이주(Si migration) 효과를 유발하여 표면 거칠기를 완화시키며, NH3 열처리는 NH3에 의한 질화에 의해 후속 트렌치 매립 산화막 증착시 실리콘이 산화되는 것을 방지한다.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and more particularly, to a device isolation film forming process for electrical isolation between devices, and more particularly, to a method of forming a trench type device isolation film. SUMMARY OF THE INVENTION An object of the present invention is to provide a method of forming a trench type isolation layer for a semiconductor device, which can prevent oxidation of a silicon substrate in a trench region and reduce surface roughness of the silicon substrate. The present invention omits the trench sidewall sacrificial oxidation process to prevent damage due to trench etching, and instead, heat treatment is performed in H 2 / NH 3 atmosphere after the trench etching. The H 2 heat treatment causes a silicon migration effect to mitigate surface roughness, and the NH 3 heat treatment prevents silicon from oxidizing during subsequent trench buried oxide film deposition by nitriding with NH 3 .

트렌치, 소자분리막, 전계 집중, H2 가스, NH3 가스, 열처리Trench, device isolation film, electric field concentration, H2 gas, NH3 gas, heat treatment

Description

반도체 소자의 트렌치형 소자분리막 형성방법{A method for forming trench type isolation layer in semiconductor device} A method for forming trench type isolation layer in semiconductor device             

도 1a 내지 도 1c는 본 발명의 일 실시예에 따른 STI 공정도.
1A-1C are STI process diagrams in accordance with one embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

10 : 실리콘 기판10: silicon substrate

11 : 패드 산화막11: pad oxide film

12 : 질화막12: nitride film

13 : 트렌치13: trench

14 : 트렌치형 소자분리막
14: trench type isolation film

본 발명은 반도체 기술에 관한 것으로, 특히 소자간의 전기적 분리를 위한 소자분리막 형성 공정에 관한 것이며, 더 자세히는 트렌치형 소자분리막 형성방법 에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and more particularly, to a device isolation film forming process for electrical isolation between devices, and more particularly, to a method of forming a trench type device isolation film.

트렌치 소자분리(shallow trench isolation, STI) 공정은 반도체 소자의 디자인 룰(design rule)의 감소에 따른 필드 산화막의 열화와 같은 공정의 불안정 요인과, 버즈비크(bird's beak)에 따른 활성 영역의 감소와 같은 문제점을 근본적으로 해결할 수 있는 소자분리 공정으로 부각되고 있으며, 1G DRAM 또는 4G DRAM급 이상의 초고집적 반도체 소자 제조 공정에의 적용이 유망한 기술이다.The trench trench isolation (STI) process is a process instability factor such as deterioration of the field oxide film due to the reduction of design rules of the semiconductor device, and the reduction of the active area due to the bird's beak. It is emerging as a device isolation process that can fundamentally solve the same problem, and it is a promising technology to be applied to an ultra-high density semiconductor device manufacturing process of 1G DRAM or 4G DRAM level.

종래의 STI 공정은 실리콘 기판 상에 패드 산화막 및 질화막을 형성하고, 이를 선택 식각하여 트렌치 마스크를 형성한 다음, 패터닝된 질화막을 식각 마스크로 사용하여 실리콘 기판을 건식 식각함으로써 트렌치를 형성하고, 계속하여 일련의 트렌치 측벽 희생산화 공정(건식 식각에 의한 실리콘 표면의 식각 결함의 제거 목적) 및 트렌치 측벽 재산화 공정을 실시한 후, 트렌치 매립용 산화막을 증착하여 트렌치를 매립하고, 화학·기계적 연마(chemical mechanical polishing, CMP) 공정을 실시한 다음, 질화막 및 패드 산화막을 제거하여 소자분리막을 형성하게 된다.A conventional STI process forms a pad oxide film and a nitride film on a silicon substrate, selectively etches to form a trench mask, and then forms a trench by dry etching the silicon substrate using the patterned nitride film as an etch mask, and subsequently After performing a series of trench sidewall sacrificial oxidation processes (to remove etching defects on the silicon surface by dry etching) and trench sidewall reoxidation processes, an oxide film for filling trenches is deposited to fill the trench, and the chemical and mechanical polishing is performed. After the polishing (CMP) process, the nitride and pad oxide layers are removed to form an isolation layer.

그런데, 트렌치 측벽 희생산화 공정은 트렌치 영역의 실리콘 기판 표면의 거칠기를 완화하는 효과가 있으나, 트렌치 측벽 희생산화 공정에 의해 실리콘 기판이 산화된 채로 잔류할 가능성이 있다. 이처럼 실리콘 기판이 산화된 채로 잔류하게 되면 후속 공정에 의해 형성되는 모스 트랜지스터의 접합 영역에 도핑된 붕소가 산화된 실리콘 기판 쪽으로 확산되어 소자의 특성이 열화되는 문제점이 있다.
By the way, although the trench sidewall sacrificial oxidation process has the effect of alleviating the roughness of the silicon substrate surface of the trench region, there is a possibility that the silicon substrate remains oxidized by the trench sidewall sacrificial oxidation process. As such, when the silicon substrate remains oxidized, boron doped in the junction region of the MOS transistor formed by the subsequent process is diffused toward the oxidized silicon substrate, thereby deteriorating device characteristics.

본 발명은 상기와 같은 종래기술의 문제점을 해결하기 위하여 제안된 것으로, 트렌치 영역의 실리콘 기판의 표면 거칠기를 완화하면서, 실리콘 기판의 산화를 방지할 수 있는 반도체 소자의 트렌치형 소자분리막 형성방법을 제공하는데 그 목적이 있다.
The present invention has been proposed to solve the above problems of the prior art, and provides a method of forming a trench type device isolation film for a semiconductor device which can prevent oxidation of the silicon substrate while alleviating the surface roughness of the silicon substrate in the trench region. Its purpose is to.

상기의 기술적 과제를 해결하기 위한 본 발명의 일 측면에 따르면, 실리콘 기판 상에 트렌치 마스크 패턴을 형성하는 단계; 노출된 상기 실리콘 기판을 식각하여 트렌치를 형성하는 단계; H2/NH3 분위기에서 열처리를 수행하는 단계; 및 상기 트렌치에 산화물을 매립하는 단계를 포함하는 반도체 소자의 트렌치형 소자분리막 형성방법이 제공된다.According to an aspect of the present invention for solving the above technical problem, forming a trench mask pattern on a silicon substrate; Etching the exposed silicon substrate to form a trench; Performing heat treatment in an H 2 / NH 3 atmosphere; And a method of forming a trench type isolation layer for a semiconductor device, the method including filling an oxide in the trench.

본 발명은 트렌치 식각에 따르는 손상을 방지하기 위한 트렌치 측벽 희생산화 공정을 생략하고, 이를 대신하여 트렌치 식각 후 H2/NH3 분위기에서 열처리를 수행한다. H2 열처리는 실리콘 이주(Si migration) 효과를 유발하여 표면 거칠기를 완화시키며, NH3 열처리는 NH3에 의한 질화에 의해 후속 트렌치 매립 산화막 증착시 실리콘이 산화되는 것을 방지한다.
The present invention omits the trench sidewall sacrificial oxidation process to prevent damage due to trench etching, and instead, heat treatment is performed in H 2 / NH 3 atmosphere after the trench etching. The H 2 heat treatment causes a silicon migration effect to mitigate surface roughness, and the NH 3 heat treatment prevents silicon from oxidizing during subsequent trench buried oxide film deposition by nitriding with NH 3 .

이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기 로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily implement the present invention.

도 1a 내지 도 1c는 본 발명의 일 실시예에 따른 STI 공정도이다.1A to 1C are STI process diagrams according to an embodiment of the present invention.

본 실시예에 따른 STI 공정은, 우선 도 1a에 도시된 바와 같이 실리콘 기판(10) 상에 패드 산화막(11) 및 질화막(12)을 증착하고, 소자분리 영역의 질화막(12) 및 패드 산화막(11)을 선택 식각하여 소자분리 마스크 패턴을 형성한 다음, 트렌치 마스크 패턴을 식각 마스크로 사용하여 노출된 실리콘 기판(10)을 식각함으로써 트렌치(13)를 형성한다.In the STI process according to the present embodiment, first, as shown in FIG. 1A, the pad oxide film 11 and the nitride film 12 are deposited on the silicon substrate 10, and the nitride film 12 and the pad oxide film (in the isolation region) are formed. 11) is selectively etched to form a device isolation mask pattern, and then the trench 13 is formed by etching the exposed silicon substrate 10 using the trench mask pattern as an etch mask.

이어서, 도 1b에 도시된 바와 같이 H2/NH3 분위기에서 열처리를 수행한다. H2/NH3 분위기에서 열처리는 급속열처리 방식으로 수행하는 것이 바람직하며, 세부 공정 조건은 다음과 같다.Subsequently, heat treatment is performed in an H 2 / NH 3 atmosphere as shown in FIG. 1B. Heat treatment in the H 2 / NH 3 atmosphere is preferably carried out by a rapid heat treatment method, the detailed process conditions are as follows.

(A) 가스 유량 : NH3 1∼20slm, H2 1∼10slm(A) Gas flow rate: NH 3 1-20 slm, H 2 1-10 slm

(B) 온도 : 700∼1100℃(B) Temperature: 700 to 1100 ° C

(C) 압력 : 10∼760Torr(C) Pressure: 10 to 760 Torr

(D) 시간 : 10∼60초(D) time: 10 to 60 seconds

계속하여, 도 1c에 도시된 바와 같이 트렌치 매립 산화막 증착시 기판 손상을 방지하기 위한 버퍼 산화막(도시되지 않음)을 형성하고, 트렌치 매립 산화막을 증착한 후, CMP 공정 및 질화막(12) 제거 공정 등을 수행하여 트렌치형 소자분리막(14)을 형성한다.Subsequently, as shown in FIG. 1C, a buffer oxide film (not shown) is formed to prevent substrate damage during the deposition of the trench buried oxide film, the trench buried oxide film is deposited, and the CMP process, the nitride film 12 removal process, and the like. The trench isolation layer 14 is formed by performing the following steps.

상기와 같이 본 발명에서는 트렌치 영역의 실리콘 기판의 산화를 유발하는 기존의 트렌치 측벽 희생산화 공정을 생략할 수 있으며, 이와 함께 NH3 열처리는 트렌치 영역의 실리콘 기판 표면을 질화시킴으로써 후속 트렌치 매립 산화막 증착시 실리콘이 산화되는 것을 방지함으로써 모스 트랜지스터의 접합 영역에 도핑된 붕소가 산화된 실리콘 기판 쪽으로 확산되는 현상을 억제할 수 있다. 한편, H2 열처리는 실리콘 이주 효과를 유발하여 표면 거칠기를 완화시키며, 트렌치의 상부 및 하부 모서리를 라운딩하는 효과를 기대할 수 있다.
As described above, in the present invention, the conventional trench sidewall sacrificial oxidation process that causes oxidation of the silicon substrate in the trench region may be omitted, and NH 3 heat treatment may be performed by nitriding the surface of the silicon substrate in the trench region to deposit subsequent trench buried oxide films. By preventing the silicon from being oxidized, the phenomenon in which the boron doped in the junction region of the MOS transistor is diffused toward the oxidized silicon substrate can be suppressed. On the other hand, H 2 heat treatment may cause a silicon migration effect to mitigate surface roughness, it can be expected to effect the rounding of the upper and lower edges of the trench.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.
The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

전술한 본 발명은 실리콘 기판의 산화에 따른 붕소 확산 현상을 방지하여 소자의 특성이 열화을 방지할 수 있으며, 트렌치 매립 산화막과 실리콘 기판의 계면의 거칠기를 완화시켜 전계 집중 현상을 억제함으로써 게이트 산화막의 열화를 방지할 수 있다.
The present invention described above can prevent the boron diffusion caused by the oxidation of the silicon substrate to prevent deterioration of the device characteristics, and deterioration of the gate oxide film by reducing the roughness of the interface between the trench buried oxide film and the silicon substrate to suppress electric field concentration. Can be prevented.

Claims (4)

실리콘 기판 상에 트렌치 마스크 패턴을 형성하는 단계;Forming a trench mask pattern on the silicon substrate; 노출된 상기 실리콘 기판을 식각하여 트렌치를 형성하는 단계;Etching the exposed silicon substrate to form a trench; H2/NH3 분위기에서 열처리를 수행하는 단계; 및Performing heat treatment in an H 2 / NH 3 atmosphere; And 상기 트렌치에 산화물을 매립하는 단계Embedding an oxide in the trench 를 포함하는 반도체 소자의 트렌치형 소자분리막 형성방법.Trench type device isolation film forming method of a semiconductor device comprising a. 제1항에 있어서,The method of claim 1, 상기 열처리는 NH3 1∼20slm, H2 1∼10slm을 사용하여 수행하는 것을 특징으로 하는 반도체 소자의 트렌치형 소자분리막 형성방법.The heat treatment is a method for forming a trench type isolation layer of a semiconductor device, characterized in that performed using NH 3 1-20 slm, H 2 1-10 slm. 제2항에 있어서,The method of claim 2, 상기 열처리는 700∼1100℃ 온도에서 10∼60초 동안 급속 열처리 방식으로 수행하는 것을 특징으로 하는 반도체 소자의 트렌치형 소자분리막 형성방법.The heat treatment is a trench type device isolation film forming method of a semiconductor device, characterized in that performed in a rapid heat treatment method for 10 to 60 seconds at a temperature of 700 ~ 1100 ℃. 제3항에 있어서,The method of claim 3, 상기 열처리는 10∼760Torr 압력하에서 수행하는 것을 특징으로 하는 반도체 소자의 트렌치형 소자분리막 형성방법.Wherein the heat treatment is performed under a pressure of 10 to 760 Torr.
KR1020020033468A 2002-06-15 2002-06-15 A method for forming trench type isolation layer in semiconductor device KR100825011B1 (en)

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US9576840B2 (en) 2013-11-26 2017-02-21 Samsung Electronics Co., Ltd. Method of manufacturing semiconductor device using surface treatment and semiconductor device manufactured by the method

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US9576840B2 (en) 2013-11-26 2017-02-21 Samsung Electronics Co., Ltd. Method of manufacturing semiconductor device using surface treatment and semiconductor device manufactured by the method
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