TW419782B - Method for forming shallow trench isolation in integrated circuits - Google Patents

Abstract

A method for forming shallow trench isolation in integrated circuits is provided, which first forms a first silicon oxide layer, a hard mask, and a second silicon oxide layer on the substrate sequentially. Then, the photolithography and etching technique is used to form a shallow trench. A thermal oxidation process is performed followed by forming a third silicon oxide layer. The third silicon oxide layer is removed except the shallow trench region. Then, a fourth silicon oxide layer is formed to fill the shallow trench, wherein the deposition rate of the fourth silicon oxide layer on the third silicon oxide layer is faster than that on the second silicon oxide layer. The silicon nitride layer functions as the etch stop for the etching back process.

Description

419782

. Amendment __ Case No. 87100740 V. Description of the invention (1) Detailed description: Technical field: The present invention relates to a method for forming a shallow trench isolation in an integrated circuit. Background of the invention: In recent years, with the rapid increase of the density of memory cells in integrated circuits, the interval between the crystal vessels has become smaller and smaller. In order to ensure that the operation of the transistor will not be interfered by other transistors, it is necessary to try to isolate all the transistors from each other ’to prevent the occurrence of latch-up. This process technology is called Isolation Process. The early isolation process that was widely used in the industry was the LOcal Oxidation (LOCOS) method. It uses thermal oxidation technology to form a field oxide layer between the transistors with a thickness of several thousand angstroms, and uses the non-conductivity of silicon dioxide to form the barrier between the transistors. There is an unavoidable disadvantage of using the area oxidation method as the isolation process, that is, when the field oxide layer is formed by the wet oxidation method, a bird's beak (Bird, s Beak) phenomenon occurs, which affects the subsequent process of the active device region β After the integrated circuit process technology enters the sub-micron or deep sub-micron, the adverse effects of the bird's beak phenomenon will become more serious. In addition, “before the field oxide layer is formed, ion implantation is usually performed with p-type ions” and then it is driven into the (Drive In) silicon substrate by a high temperature step to form a channel stop. After the integrated circuit process technology enters the sub-micron or deep sub-micron, many subsequent high-temperature steps may cause excessive thermal diffusion ’and cause severe narrow-width effects. To meet the needs of sub-micron or deep sub-micron processes, many new isolation systems

D: \ CSpatent \ 87100740. Ptc 2000.09.11.004 page 4 419782-case number 8710.07 but one -B _ 5. Description of the invention-Process technology was developed to replace the area oxidation method. One of the most promising is called shallow trench isolation. "10w Trench Isolation". The shallow trench isolation is firstly formed on the substrate to form a shallow trench, which is formed by chemical vapor deposition. A dielectric layer is used to fill the shallow trenches and then etch back to form the shallow trench isolations, and the active element area is between the shallow trench isolations. In the actual layout of the integrated circuit, the 'part' Areas only require a small area of shallow trench isolation, while some areas require a large area of shallow trench isolation. "When making a large area of shallow trench isolation, 'When using a chemical vapor deposition method to form a dielectric layer After the area of the shallow trench is filled, a very thick dielectric layer is also formed outside the shallow trench; therefore, the time required for the subsequent etch-back step is extremely long, because it is not easy to control the etch-back termination point. Over-etching to form a dishing effect (Dishing Effect). When the gate oxide layer of the transistor is subsequently formed by thermal oxidation technology in the area of the active element, 'because the stress at the corner of the shallow trench is greater, Significantly reduced gate oxide thickness It is small, which causes the Kink Effect to occur in the subsequent formation of the transistor. The turning effect of the transistor is a phenomenon that the transistor is turned on or turned off earlier. Therefore, the traditional shallow channel The transistor formed by the trench isolation technology will not be able to meet the electrical requirements of the integrated circuit. 'In order to solve the dish-shaped phenomenon, many new processes have been developed, such as changing a large shallow trench to a plurality of shallow trenches Processes such as a small pattern of a shallow trench (Dummy Pattern), a reverse mask (Reverse_Tone Mask), or an over coating process, etc. ^ But the above processes all require quite complicated steps' and are very expensive Cost, are not suitable to be replaced

2000. 09.11.005 Page 5 D: \ CSpatent \ 87100740. Ptc ---- Case No. 87100740_year month n___ V. Description of the invention (3) Regional oxidation method 0 Summary of the invention: The main purpose of the present invention is to provide a Method for forming shallow trench isolation. A secondary object of the present invention is to provide a shallow trench isolation for use in an integrated circuit isolation process. The present invention uses the following process methods to achieve the above-mentioned object: A layer is formed on a semiconductor substrate one after another. The first oxide layer, a polycrystalline silicon layer, a silicon nitride layer, and a second silicon halide layer define a shallow trench area using lithography and etching techniques. Then, the first silicon oxide layer, the polycrystalline silicon layer, the siliconized silicon layer, and the second silicon oxide layer are used as a hard cover, and the semiconductor substrate is etched to form a shallow trench, and then thermal oxidation is performed. step. Then, a third silicon oxide layer is formed, and the third silicon oxide layer is polished by using a chemical mechanical polishing technique to remove the third silicon oxide layer above the second silicon oxide layer. A fourth silicon oxide layer is then formed to fill the shallow trenches. The deposition rate of the fourth silicon oxide layer on the third silicon oxide layer is faster than the deposition rate on the second oxide layer. Perform the tempering step. A chemical-mechanical polishing technique is used to perform a money-back engraving step on the fourth silicon oxide layer and the second silicon halide layer, and the silicon nitride layer is used as an etching stop layer. The method for forming shallow trench isolation in integrated circuits according to the present invention is completed in 焉. Brief description of the drawings: Fig. 1 is a schematic cross-sectional view of a shallow trench formed in the first embodiment of the present invention.

D: \ CSpatent \ 87100740.ptc

2000.09.11.006 41978 ^ Case number 87100740 Rev. V. Description of the invention (4) Figure 2 is a schematic cross-sectional view of a third silicon oxide layer formed in the first embodiment of the present invention. Fig. 3 is a schematic cross-sectional view of the third silicon oxide layer etched back in the first embodiment of the present invention. Fig. 4 is a schematic cross-sectional view of the fourth silicon oxide layer formed in the first embodiment of the present invention. FIG. 5 is a schematic cross-sectional view of the fourth silicon oxide layer and the second oxide dream layer in the first embodiment of the present invention. FIG. 6 is a schematic cross-sectional view of removing a silicon nitride layer in the first embodiment of the present invention. 27 is a schematic cross-sectional view of a shallow trench area formed in the second embodiment of the present invention. Fig. 8 is a schematic cross-sectional view of a third silicon oxide layer formed in the second embodiment of the present invention. Fig. 9 is a schematic cross-sectional view of a third oxidized debris layer in the second embodiment of the present invention. Fig. 10 is a schematic sectional view of a fourth silicon oxide layer formed in the second embodiment of the present invention. FIG. 11 is a schematic cross-sectional view of removing a silicon nitride layer and a first silicon oxide layer in a second embodiment of the present invention. Drawing number description 10- substrate 20- first silicon oxide layer 25- polycrystalline silicon layer 30- silicon nitride layer 35- second silicon oxide layer 40- shallow trench 50- third silicon oxide layer 50a- remaining third Silicon oxide

D: \ CSpatent \ 87100740. Ptc Page 7 2000.09.11.007 419782 --- Case No. 87100740_Year Month ^ V. Description of the invention (5) 60- Fourth silicon oxide layer 70- Shallow trench isolation first implementation For example, please refer to FIG. 1. On the semiconductor substrate 10, a first silicon oxide layer (Oxide) 20, a polycrystalline silicon 25, a nitride nitride layer 3G, and a second emulsified dream layer 35 are successively formed. The lithography and ion-etching techniques were used to define the area of the side channel. Then, the semiconductor substrate is engraved with the first oxide chip 20, the polycrystalline silicon 25, the silicon nitride layer 30, and the second silicon oxide layer 35 as a hard mask to form a shallow trench 40. A thermal oxidation step is subsequently performed, the purpose of which is to subject the shallow trench 40 to high temperature treatment, so that the atoms on the inner wall of the shallow trench can be rearranged to repair defects caused by the impact of high-energy ions during the etching process; A very thin silicon oxide layer (not shown in the figure) will be formed on the inner wall of the shallow trench. The function of forming the silicon nitride layer 30 is to serve as a mask for protecting the active region when performing shallow trench etching, and the thickness is between 1000 angstroms and 2000 angstroms. The first silicon oxide layer 20 is formed by a thermal oxidation technique or a chemical vapor deposition method, and its main function is to serve as a pad (Pad) of the silicon nitride layer 30 to relax the silicon nitride layer 3. Excessive stress between 〇 and the silicon substrate 10 'its thickness is between 30 angstroms and 2000 angstroms. The thickness of the polycrystalline silicon is between 500 Angstroms and 2000 Angstroms. The second silicon oxide layer 35 is a high-temperature silicon oxide layer (Hy

Temperature Oxide), with a thickness between 50 Angstroms and 2000 Angstroms. Please refer to the second step to form a third silicon oxide layer 50. The third silicon oxide layer uses ozone / tetraethoxysilane (〇3 / TEOS) as a reaction gas (where

D: \ CSpatent \ 87100740. Ptc page 8 2000.09.n__ 419782 _ case number 87100740_ year month day correction ___ 5. Description of the invention (6) The flow of ozone is less than the flow of tetraethoxysilane), using atmospheric pressure It is formed by Atmospheric Pressure Chemical Vapor Deposition (APCVD) or Sub-Atmospheric Pressure Chemical Vapor Deposition (SACVD), and its thickness is between 500 and 2000 Angstroms. The third silicon oxide 50 formed by this process has excellent Step Coverage properties, as shown in Figure 2. "Please refer to Figure 3 'and then use chemical mechanical polishing technology or ion money engraving technology for back drilling. Removing the third silicon oxide layer 50 above the second silicon oxide layer 35. After that, a short-time dipping step is performed in the hydrofluoric acid solution to remove impurities in the shallow trench. At this time, the surface of the inner wall of the shallow trench is a residual third oxide layer 50 a with ozone / tetraethoxysilane (〇3 / TEOS) as the reaction gas, and the surface outside the shallow trench is based on high temperature gasification technology. The formed second silicon oxide layer 35 is shown in FIG. 3. Please refer to FIG. 4, a fourth silicon oxide layer is formed, and the shallow trench is filled. The deposition rate of the fourth silicon oxide layer on the third silicon oxide layer is higher than the deposition rate of the second silicon oxide layer. fast. The fourth silicon oxide layer uses ozone / tetraethoxysilane (〇3 / TEOS) as a reaction gas (where the flow rate of stinky odor is more than ten times greater than the flow rate of tetraethoxylithium sinter), using atmospheric pressure chemistry Formed by vapor deposition (A PC VD) or sub-atmospheric chemical vapor deposition (s A c VD). Its reaction temperature is between 350 ° C and 450 ° C, and its thickness is between 3,000 and 15,000 angstroms. between. Subsequently, a tempering step is performed, and nitrogen is passed at a high temperature of 800-110 ° C for a period of time between 15-60 minutes. The fourth silicon oxide 60 formed by this process has a very special

Amendment No. 87100740 5. The nature of the description of invention (7), its deposition rate is very fast on the surface of the silicon oxide layer formed by using ozone / tetraethoxysilane (TE0s) as a reaction gas, but it is oxidized at high temperature The surface of the silicon oxide layer formed by the technology is very slow, and the deposition rate of the latter is only 20-50% of that of the former. Because the surface of the inner wall of the shallow trench is a residual third oxide layer 50 a with ozone / tetraethoxysilane (〇3 / TE〇s) as the reaction gas, and the surface outside the shallow trench is based on high temperature oxidation technology. The second silicon oxide layer 35 is formed, and therefore the deposition rate of the fourth silicon oxide layer 60 on the inner wall of the shallow trench is much higher than the deposition rate of the fourth silicon oxide layer 60 outside the shallow trench. As shown in Figure 4, the fourth silicon oxide layer 60 can fill the shallow trench, but only a very thin silicon oxide layer is formed outside the shallow trench, which is the focus of the present invention. Please refer to FIG. 5 * Chemical mechanical polishing technology is used to etch back the fourth silicon oxide layer 60 and the second silicon oxide layer 35, and the silicon nitride layer 30 is used as an etching stop layer. At this time, the fourth silicon oxide layer 60 outside the shallow trench is extremely thin, so the time required for the etch-back step is much shorter than that of the traditional process. 'This can avoid the dish-like phenomenon caused by the long etch-back time (Dishing Effect), which is conducive to the subsequent process. Please refer to Article 26. Finally, the silicon nitride layer 30 is removed, and a good shallow trench isolation 70 ′ is obtained. The remaining polycrystalline silicon layer 25 and the first silicon oxide layer 20 are left at the same time. The gated layer and gate conductive layer of the crystal. The method for forming a shallow trench in an integrated circuit according to the present invention is completed in a short time. Second Embodiment Referring to FIG. 7, a first layer is formed on the semiconductor substrate 10.

D: \ CSpatent \ 87100740. Ptc Page 10, 2000.09.11.010 419782 Case No. 87100740 Revised month 5. Description of the invention (8) Silicon oxide layer (Oxide) 20, silicon nitride layer (Nitride) 30 and a second oxide The silicon layer 35 'uses lithography and ion etching techniques to define the shallow trench area. Then, the semiconductor substrate 10 is etched with the first silicon oxide layer 20, the silicon argon layer 30, and a second silicon oxide layer 35 as a hard mask to form a shallow trench 4. . Subsequently, a thermal annealing step is performed, whose purpose is to subject the shallow trench 40 to high temperature treatment, so that the atoms on the inner wall of the shallow trench can be rearranged to repair defects caused by high-energy ion impact during the etching process; the thermal oxidation In the step, a very thin silicon oxide layer is formed on the inner wall of the shallow trench (not shown in the figure). The function of forming the silicon nitride layer 30 is to serve as a mask for protecting the active region when performing shallow trench etching, and the thickness is between 1000 angstroms and 2000 angstroms. The first silicon oxide layer 20 is formed by a thermal oxidation technique or a chemical vapor deposition method, and its main function is to serve as a pad (Pad) of the silicon nitride layer 30 to relax the silicon nitride layer 3. Excessive stress between 0 and the silicon substrate 10 has a thickness between 30 angstroms and 200 angstroms. The second silicon oxide layer 50 is a high temperature oxide layer (High Temperature Oxide) formed by using a high temperature deposition technology, and has a thickness between 50 angstroms and 200 angstroms. Please refer to 28. The third silicon oxide layer 50 is formed. The third silicon oxide layer is based on odorant / tetraethoxysilane (〇3 / TEOS) as a reaction gas (wherein the flow rate of ozone is less than the flow rate of tetraethoxysilane), and atmospheric chemical vapor deposition is used. (Atmospheric Pressure Chemical Vapor Depositon; APCVD) method or Sub-atmospheric pressure chemical vapor deposition method (Sub-

Atmospheric Pressure Chemical Vapor Deposition;

D: \ CSpatent \ 87100740.ptc

Page 11 2000.09.11.011 Case No. 87100740 Amendment V. Description of Invention (9) SACVD), its thickness is between 500 and 2000 Angstroms. The third silicon oxide formed by this process has excellent Step Coverage properties, as shown in Figure 8. Please refer to FIG. 9, and then perform etch-back using a chemical mechanical polishing technique or an ion etching technique to remove the third silicon oxide layer above the second silicon oxide layer. Then, a short-time dip (Dip) step is performed in the hydrofluoric acid solution to remove impurities in the shallow trench. At this time, the surface of the inner wall of the shallow trench is a residual third oxide layer using ozone / tetraethoxysilane (03 / TE0S) as a reaction gas, and the surface outside the shallow trench is formed by a high-temperature oxidation technology. Oxidation layer, as shown in Figure 9. Please refer to FIG. 10, a fourth silicon oxide layer is formed, and the shallow trench is filled. The deposition rate of the fourth silicon oxide layer on the third silicon oxide layer is higher than that of the second silicon oxide dream layer. Fast speed. The fourth stone oxide layer uses ozone / tetraethoxysilane (〇a / TEOS) as a reaction gas (wherein the flow rate of ozone is more than ten times greater than the flow rate of tetraethoxysilane), and uses atmospheric pressure chemistry Formed by vapor deposition (APCVD) or subatmospheric chemical vapor deposition (SACV £)), its reaction temperature is between 350 ° C and 450 t, and its thickness is between 3,000 and 15,000 angstroms. Subsequently, a tempering step is performed, and nitrogen gas is passed at a high temperature of 800, and the time is between 5 and 60 minutes. The fourth silicon oxide 60 formed by this process has very special properties. Its deposition rate is on the surface of the silicon oxide layer formed by using ozone / tetraethoxysilane (〇3 / TE〇s) as a reaction gas. It is very fast, but the surface of the silicon oxide layer formed by the high temperature oxidation technology is very slow, and the deposition rate of the latter is only 20-50% of that of the former. Because the surface of the inner wall of the shallow trench is

Page 12 2000.09.11.012 419T〇

No. 1 8Ή00740 V. Description of the invention (10) Ozone / tetraethoxysilane (〇3 / TE〇S) is the residual third oxidation of the reaction gas: 50a, and the surface outside the shallow trench is treated by high temperature oxidation technology. The first silicon oxide layer 35 is formed, so the deposition rate of the fourth silicon oxide layer 60 on the inner wall of the shallow trench is much greater than the deposition rate of the fourth silicon oxide layer 60 outside the shallow trench. The fourth silicon oxide layer 60 formed as shown in Fig. 10 can fill the shallow trench. However, only a very thin silicon oxide layer is formed outside the shallow trench. This is the focus of the present invention. Referring to FIG. 11, the fourth silicon oxide layer 60 and the second silicon oxide layer 35 are etched back by using a chemical mechanical polishing technique, and the silicon nitride layer 30 is used as an etching stop layer. At this time, the fourth silicon oxide layer 60 outside the shallow trench is extremely thin, so the time required for the etch-back step is much shorter than that of the traditional process. Effect), is conducive to the performance of the post-production process. Finally, the silicon nitride layer 30 and the first silicon oxide layer 20 are removed, and a shallow trench isolation 70 of good quality is obtained. The method for forming a shallow trench in an integrated circuit according to the present invention is completed in. The method for forming shallow trench isolation in integrated circuits according to the present invention has the following advantages: ~ 1. The method for forming shallow trench isolation in integrated circuits according to the present invention does not cause a dish-like phenomenon and Affects subsequent processes in the active component area. 2. The method for forming shallow trench isolation in integrated circuits according to the present invention 'will not cause a transition effect in the transistor formed in the active device region.

D: \ CSpatent \ 87100740.ptc page 13 2000.09. 11.013 419782 __case number 87100740_year π Sheng Zheng __ 5. Description of the invention (Π) 3. The invention described in the present invention forms a shallow channel in the integrated circuit The trench isolation method 'does not require the addition of an additional mask step and does not complicate the process too much. The above description uses the preferred embodiments to explain the present invention in detail, but not to limit the scope of the present invention, and those skilled in the art will be able to understand and make slight changes and adjustments, and will still not lose the completeness of the present invention. The spirit and scope of the present invention

D: \ CSpatent \ 87100740. Ptc 200 ° 09.11.014

Claims (1)

4ι ^ 782 87100740 VI. Scope of patent application f () month & amendment 1. A method for forming shallow trench isolation in integrated circuits, including: forming a layer of a first oxide layer and a hard type The shield is on a semiconductor substrate: b. Forming a second silicon oxide layer on the hard shield; c ♦ forming a shallow trench using lithography and ion etching techniques; d forming a third silicon oxide layer E • removing the third silicon oxide layer above the second silicon oxide layer; ♦ forming a fourth oxide layer to fill the shallow trench, and the fourth oxide layer is located in the first silicon oxide layer; The deposition rate on the silicon oxide layer is faster than the deposition rate on the second oxide layer; g is etched back to remove the fourth silicon oxide layer and the second silicon oxide layer above the hard shield, and The hard shield is used as an etching stop layer. 2. The method for forming a shallow trench isolation in an integrated circuit according to item 1 of the scope of patent application. After performing the etch-back step in step g, the method further includes removing The steps of the hard guard are described. 3 _ The method for forming a shallow trench isolation in an integrated circuit according to item 1 of the scope of the patent application, wherein the first silicon oxide layer is formed using a thermal oxidation technology. 4. The method for forming a shallow trench isolation in an integrated circuit as described in the first item of the patent application scope, wherein the first silicon oxide layer is formed by a chemical vapor deposition method. 5. The method for forming a shallow trench isolation in an integrated circuit according to item 1 of the scope of the patent application, wherein the thickness of the first silicon oxide layer is 30 angstroms to D: \ CSpatent \ 87100740.ptc page 15 2000, 09.11.015 419782 ----- 1 ^, 87100740__ 6. The scope of patent application is between 200 Angstroms. 6. The on-off method according to item 丨 of the patent application scope, wherein said forming a hard-type electric secondary; forming a shallow trench trench 7 such as land; forming a layer of multi-crystalline silicon and hard: =: layer on a semiconductor substrate The upper = the sixth item of the profit range in the integrated circuit = method 'wherein the thickness of the polycrystalline sand layer is 50. Angstroms to 2_ 8. The method of forming a shallow trench trench J in an integrated circuit according to item 6 of the Lee range, wherein the thickness of the random fossil layer is between 1,000 angstroms and 〇 堞. 9.:! Please form a shallow trench in the integrated circuit according to item 1 of the patent scope = Method 纟 to form a hard shield on the conductor substrate to form a silicon nitride layer. 1 (1_A method for forming a shallow trench isolation in an integrated circuit as described in item 1 of the scope of patent application, wherein the second silicon oxide layer is formed using a high temperature deposition technique. 11 · As item 1 of the scope of patent application A method for forming a shallow trench isolation in an integrated circuit, wherein the thickness of the second silicon oxide layer is between 500 angstroms and 2000 angstroms. 1 2 _ As in the first item of the scope of the patent application Method for forming shallow trench isolation in integrated circuits' After the shallow trench is formed, it further includes a step of thermal oxidation. 1 3. As described in item 1 of the scope of patent application, forming shallow trench isolation in integrated circuits Method 'wherein the formation of the third silicon oxide layer is based on ozone / quad ISfi D: \ CSpatent \ 87100740. Ptc page 16 2000.09.11.016 419782 case number 87100740 3 Amendment VI. Patent application scope ethoxysilane The flow rate of gas and its base isane. The flow rate of% milk is less than tetraethyl gas] <, as in the scope of the patent application! Item in the method of in-situ ionization, wherein said forming a second Vapor deposition method Chang Fahua 15 'The method of circuit isolation in an integrated circuit as described in the scope of patent application item No.!, Wherein the formation of a third oxide layer is a ^ trench isolation chemical vapor deposition method. Atmospheric 16. == Patent range item 丄 Forms a shallow quasi-ditch of 2000 angstroms in the integrated circuit. The thickness of the oxidized stone layer is from 500 angstroms to Π .: Patent application! The method for forming a shallow trench isolation in an integrated circuit, wherein the removing the first silicon oxide layer above the second silicon oxide layer is by using a chemical mechanical polishing technique. The method for forming a shallow trench isolation in an integrated circuit, wherein the removing the second oxide layer above the second silicon oxide layer is based on an ion etching technique. 1 9 The first method for forming a shallow trench isolation in an integrated circuit 'after removing the third oxide layer above the second silicon oxide layer, the method further includes an immersion step. For example, the scope of application for patent No. 1 9 ways to form shallow trench isolation in integrated circuits The immersion step is performed in a hydrofluoric acid solution. 21 ‘As described in the scope of the first patent application, the formation of shallow trenches in integrated circuits 20 D: \ CSpatent \ 87100740. Ptc Page 17 2000.09.11-017 The formation of shallow trenches is between 15-60 minutes — ___ cable number f? 7infl740 ___ --- ^ ---- --- VI. The method, wherein the fourth silicon oxide layer is formed by using ozone / tetraethoxysilane as a reaction gas, wherein the flow rate of ozone is more than ten times greater than the flow rate of tetraethoxysilane. 22. The method for forming a shallow trench isolation in an integrated circuit according to item 1 of the scope of the patent application, wherein said forming a fourth silicon oxide layer is performed by an atmospheric pressure chemical vapor deposition method. 23. The method for forming a shallow trench isolation in an integrated circuit according to item 1 of the scope of the patent application, wherein said forming a fourth silicon oxide layer is by a sub-atmospheric pressure chemical vapor deposition method. 24. The method for forming a shallow trench isolation in an integrated circuit according to item 1 of the patent application scope, wherein the thickness of the fourth silicon oxide layer is between 3000 and 150000 angstroms. 25. The method of forming a shallow trench isolation in an integrated circuit according to item 1 of the scope of the patent application ', after forming the fourth silicon oxide layer, further includes a tempering step. 26. The method for forming a shallow trench isolation in an integrated circuit according to item 25 of the scope of patent application, wherein the tempering step is performed by passing nitrogen gas at a high temperature of 800-u0 (rc). 27_ The method of isolation in an integrated circuit as described in the scope of application for patent No. 25 ', wherein said tempering step is between clocks. 2000. 09.11. 〇18