KR20020037420A - Method for forming isolation layer in semiconductor device - Google Patents
Method for forming isolation layer in semiconductor device Download PDFInfo
- Publication number
- KR20020037420A KR20020037420A KR1020000067351A KR20000067351A KR20020037420A KR 20020037420 A KR20020037420 A KR 20020037420A KR 1020000067351 A KR1020000067351 A KR 1020000067351A KR 20000067351 A KR20000067351 A KR 20000067351A KR 20020037420 A KR20020037420 A KR 20020037420A
- Authority
- KR
- South Korea
- Prior art keywords
- trench
- oxide film
- film
- device isolation
- forming
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
- H01L21/76235—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls trench shape altered by a local oxidation of silicon process step, e.g. trench corner rounding by LOCOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Element Separation (AREA)
Abstract
Description
본 발명은 반도체 소자의 소자분리막 형성방법에 관한 것으로, 보다 구체적으로는, GOI(Gate Oxide Integrity) 및 트랜지스터 특성을 개선시킬 수 있는 소자분리막 형성방법에 관한 것이다.The present invention relates to a method of forming a device isolation film of a semiconductor device, and more particularly, to a device isolation film formation method capable of improving the gate oxide integrity (GOI) and transistor characteristics.
일반적으로 실리콘 웨이퍼에 형성되는 반도체 장치는 개개의 회로 패턴들을 전기적으로 분리하기 위한 소자 분리 영역을 포함한다. 특히 반도체 장치가 고집적화 되고 미세화 되어감에 따라 각 개별 소자의 크기를 축소시키는 것뿐만 아니라 소자 분리 영역의 축소에 대한 연구가 활발히 진행되고 있다. 그 이유는 소자 분리 영역의 형성은 모든 제조 단계에 있어서 초기 단계의 공정으로서, 활성영역의 크기 및 후공정 단계의 공정마진을 좌우하게 되기 때문이다.In general, semiconductor devices formed on silicon wafers include device isolation regions for electrically separating individual circuit patterns. In particular, as semiconductor devices have been highly integrated and miniaturized, research into not only the size of each individual device but also the device isolation region has been actively conducted. The reason for this is that the formation of the device isolation region is an initial step in all the manufacturing steps, and depends on the size of the active area and the process margin of the post-process step.
일반적으로 반도체 장치의 제조에 널리 이용되는 로코스 소자분리 방법은 공정이 간단하다는 이점이 있지만 256M DRAM급 이상의 고집적화되는 반도체 소자에 있어서는 소자 분리 영역의 폭이 감소함에 따라 버즈비크(Bird' Beak)에 의한 펀 치쓰루(Punch-Through)와 소자 분리막의 두께 감소로 인하여 그 한계점에 이르고 있다.In general, the Locos device isolation method widely used in the manufacture of semiconductor devices has the advantage of simple process, but in the case of highly integrated semiconductor devices of 256M DRAM level or more, the width of the device isolation region decreases in the bird's beak. Due to the punch-through and thickness reduction of the device isolation layer, the limit point is reached.
이에따라, 고집적화된 반도체 장치의 소자 분리에 적합한 기술로 트랜치를 이용한 소자 분리 방법, 예컨대 샬로우 트랜치 분리방법(Shallow Trench Isolation: 이하, STI)이 제안되었다.Accordingly, a device isolation method using a trench, such as a shallow trench isolation method (STI), has been proposed as a technique suitable for device isolation of highly integrated semiconductor devices.
먼저, 도 1a를 참조하면, 실리콘 기판(1)상에 버퍼 역할을 하는 패드 산화막(2)과 산화를 억제하는 실리콘 질화막(3)을 순차적으로 형성한다. 다음, 실리콘 질화막(3) 상부에 소자 분리 예정 영역을 형성시키기 위한 감광막 패턴(4)을 형성한다. 이때, 감광막 패턴(4)은 얇은 폭의 소자 분리막을 형성하기 위하여 해상도가 우수한 DUV(deep ultra violet)광원을 이용하여 형성한다.First, referring to FIG. 1A, a pad oxide film 2 serving as a buffer and a silicon nitride film 3 inhibiting oxidation are sequentially formed on the silicon substrate 1. Next, a photosensitive film pattern 4 for forming a device isolation region is formed on the silicon nitride film 3. In this case, the photoresist pattern 4 is formed using a deep ultra violet (DUV) light source having excellent resolution in order to form a thin device isolation layer.
그 다음 도 1b를 참조하면, 상기 감광막 패턴(4)을 마스크로 하여, 실리콘 질화막(3), 실리콘 산화막(2) 및 실리콘 기판(1)을 소정 깊이만큼 식각하여, 샬로우 트랜치(ST)를 형성한다. 그런다음, 상기 감광막 패턴 제거하고, 트랜치 형성시 데미지 및 스트레스를 최소화 하고, 이후 형성될 갭필 옥사이드막과의 접착강도를 향상시키기 위해 트랜치(ST)가 형성된 실리콘 기판을 산소 분위기하에서 산화공정을 수행함으로써 트랜치내에 산화막(5)을 형성한다. 이어서, 열산화막(5)이 형성된 트랜치(ST) 내에 갭필 옥사이드막(6)을 매립하여 STI 소자분리막을 형성한다.Next, referring to FIG. 1B, the shallow trench ST may be etched by the silicon nitride film 3, the silicon oxide film 2, and the silicon substrate 1 by a predetermined depth using the photoresist pattern 4 as a mask. Form. Then, by removing the photoresist pattern, minimizing damage and stress at the time of trench formation, and oxidizing the silicon substrate having the trench ST under oxygen atmosphere to improve the adhesion strength with the gapfill oxide film to be formed later. An oxide film 5 is formed in the trench. Subsequently, a gapfill oxide film 6 is embedded in the trench ST where the thermal oxide film 5 is formed to form an STI device isolation film.
그러나, 상기 트랜치내에 열산화막 형성시, 도 1b에 도시된 바와같이, 트랜치(ST) 상부의 모서리부분(T) 에서 패드 산화막과 실리콘이 계면을 이루고 있으므로 산소의 확산속도가 느리고, 트랜치 하부의 모서리 부분(B)에서는 실리콘 기판의 결정면, 예컨대, 트랜치 바닥면, 트랜치 측면, 트랜치 하부 모서리의 결정면이 다르게 존재하여 트랜치 모서리 부분(T, B)에서 각화현상이 발생된다.However, when the thermal oxide film is formed in the trench, as shown in FIG. 1B, since the pad oxide film and the silicon form an interface at the corner portion T of the upper portion of the trench ST, the diffusion rate of oxygen is slow and the corner of the trench lower portion is formed. In the portion B, crystal surfaces of the silicon substrate, for example, the trench bottom surface, the trench side surface, and the crystal bottom surface of the trench lower edge are present differently, so that an angular phenomenon occurs in the trench edge portions T and B.
이러한 각화현상이 발생될 경우 전기장이 인가되었을 때, 트랜치 모서리 부분(T, B)에서 전기장의 크기가 선택적으로 증가되는 전기장집중효과가 발생되고, 이로인하여 누설전류가 증대되어 소자의 GOI(Gate Oxide Integrity) 및 트랜지스트 특성이 열화된다.When such an angular phenomenon occurs, when the electric field is applied, an electric field concentration effect is generated in which the size of the electric field is selectively increased at the trench edges (T, B), thereby increasing the leakage current, thereby increasing the gate oxide of the device. Integrity) and transistor characteristics deteriorate.
이에따라, 본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로, 트랜치 내에 불활성 불순물을 주입하여 실리콘 기판을 비정질화 함으로써 각화현상을 방지할 수 있는 반도체 소자의 소자분리막 형성방법을 제공하는 데 그 목적이있다.Accordingly, an object of the present invention is to provide a method for forming a device isolation film of a semiconductor device capable of preventing keratinization by injecting inert impurities into a trench to amorphousize a silicon substrate. There is this.
도 1a 및 도 1b는 종래의 반도체 소자의 소자분리막 형성방법을 설명하기 위한 단면도.1A and 1B are cross-sectional views illustrating a method of forming a device isolation film of a conventional semiconductor device.
도 2a 및 도 2d는 본 발명의 반도체 소자의 소자분리막 형성방법을 설명하기 위한 단면도.2A and 2D are cross-sectional views illustrating a method of forming an isolation layer in a semiconductor device of the present invention.
* 도면의 주요부분에 대한 부호설명 ** Explanation of Signs of Major Parts of Drawings *
11 : 실리콘 기판 12 : 패드 산화막11 silicon substrate 12 pad oxide film
13 : 실리콘 질화막 14 : 감광막 패턴13 silicon nitride film 14 photosensitive film pattern
ST : 샬로우 트랜치 T, B : 트랜치 모서리의 상, 하부ST: Shallow trench T, B: Top and bottom of trench edge
15a : 희생 산화막 15b : 접착용 산화막15a: sacrificial oxide film 15b: adhesion oxide film
16 : 갭필 옥사이드막16: gap fill oxide film
상기와 같은 목적을 달성하기 위하여, 본 발명은, 소자 분리용 트랜치가 형성된 실리콘 기판에 있어서, 상기 트랜치된 실리콘 기판상에 불활성 기체를 이온주입하여 상기 실리콘 기판을 비정질화시키는 단계; 상기 비정질화된 트랜치 내에 트랜치 식각 데미지를 제거하는 희생 산화막을 형성하는 단계; 상기 희생 산화막 상부에 접착용 산화막을 형성하는 단계; 상기 접착용 산화막이 형성된 트랜치내에 갭필 옥사이드막을 매립하는 단계; 및 상기 갭필 옥사이드막을 포함하는 실리콘 기판을 열처리하여 불활성 기체를 제거하는 단계를 포함하여 구성하는 것을 특징으로 한다.In order to achieve the above object, the present invention, in the silicon substrate is formed trench isolation device, the step of amorphous implantation of the silicon substrate by ion implanting an inert gas on the trench silicon substrate; Forming a sacrificial oxide layer to remove trench etch damage in the amorphous trench; Forming an adhesion oxide film on the sacrificial oxide film; Embedding a gapfill oxide film in a trench in which the adhesion oxide film is formed; And removing the inert gas by heat-treating the silicon substrate including the gap fill oxide film.
상기 패드 산화막은 습식산화방식을 이용하여 형성하고, 상기 습식산화방식은 800 ~ 900℃의 온도 및 1 ~ 2.5Torr의 압력범위하에서 H20 + N20 기체의 혼합비(130 ~ 200sccm ; 70 ~ 90sccm)로서 50 ~ 150Å의 두께로 패드 산화막을 형성하는 것을 특징으로 한다.The pad oxide layer is formed using a wet oxidation method, and the wet oxidation method includes a mixture ratio of H 2 0 + N 2 0 gas at a temperature of 800 to 900 ° C. and a pressure range of 1 to 2.5 Torr (130 to 200 sccm; 70 to 70). 90 sccm) to form a pad oxide film with a thickness of 50 to 150 kPa.
상기 실리콘 질화막은 반응기체로서 SiH4+ N20를 이용한 저압화학기상증착법을 이용하여 증착하고, 화학조성비를 Si3N4로 조절하여 상기 패드 산화막과 실리콘 질화막 계면에서 생성되는 압축응력을 102~ 103dyne/cm이하로 조절한다.A compressive stress is generated and the silicon nitride film as a reaction gas SiH 4 + N using a 20 deposited using a low pressure chemical vapor deposition method, and a chemical composition in the Si 3 N adjusted to 4 wherein the pad oxide film and a silicon nitride film interface 10 2 ~ Adjust to less than 10 3 dyne / cm.
한편, 상기 실리콘 질화막은 700 ~ 900℃의 온도 및 2.5 ~ 4Torr의 압력범위하에서 SiH4+ N20 기체의 혼합비(120 ~ 150sccm ; 150 ~ 180sccm)로서 1000 ~ 13000Å의 두께로 형성되는 것을 특징으로 한다.On the other hand, the silicon nitride film is characterized in that it is formed in a thickness of 1000 ~ 13000Å as the mixing ratio (120 ~ 150sccm; 150 ~ 180sccm) of SiH 4 + N 2 0 gas at a temperature of 700 ~ 900 ℃ and a pressure range of 2.5 ~ 4 Torr do.
상기 트랜치는 바람직하게 1000~ 5000Å의 깊이로 트랜치되고, 상기 트랜치의 기하학적 구조에 관련된 인자로서 트랜치 바닥면과 측면의 사이각이 80 ~ 85도 인것을 특징으로 한다.The trench is preferably trenched to a depth of 1000-5000 Å, characterized in that the angle between the trench bottom and side is 80-85 degrees as a factor related to the geometry of the trench.
상기 불활성 기체는 바람직하게 아르곤 기체이며, 상기 불활성 기체의 이온주입시 이온주입범위 값은 40 ~ 60Å이고, 틸트 각도는 2 ~ 4도로 조절하여 수행된다.The inert gas is preferably an argon gas, the ion implantation range value during the ion implantation of the inert gas is 40 ~ 60Å, the tilt angle is performed by adjusting the 2 to 4 degrees.
상기 열처리 공정은 900 ~ 1000℃ 온도 및 1.5 ~ 3Torr 압력하에서 N2+ Ar기체의 혼합비(100 ~ 140sccm : 100 ~ 120sccm)의 분위기에서 열처리하며, 상기 열처리 공정을 수행함으로써 상기 불활성 기체의 농도를 5 ~ 7 ×104atoms /cm3이하로 유지하는것을 특징으로 한다.The heat treatment process is a heat treatment in the atmosphere of the mixing ratio (100 ~ 140sccm: 100 ~ 120sccm) of N 2 + Ar gas at 900 ~ 1000 ℃ temperature and 1.5 ~ 3 Torr pressure, and the concentration of the inert gas by 5 It is characterized by maintaining at or below 7 × 10 4 atoms / cm 3 .
(실시예)(Example)
이하, 첨부된 도면을 참조하여 본 발명의 반도체 소자의 소자분리막 형성방법을 상세히 설명한다.Hereinafter, a device isolation film forming method of a semiconductor device of the present invention will be described in detail with reference to the accompanying drawings.
도 2는 반도체 소자의 소자분리막 형성방법을 설명하기 위한 단면도로서, 도 2a를 참조하면, 실리콘 기판(11)상에 버퍼 역할을 하는 패드 산화막(12)과 산화를 억제하는 실리콘 질화막(13)을 순차적으로 형성한다.FIG. 2 is a cross-sectional view illustrating a method of forming a device isolation film of a semiconductor device. Referring to FIG. 2A, a pad oxide film 12 serving as a buffer on a silicon substrate 11 and a silicon nitride film 13 inhibiting oxidation are illustrated. Form sequentially.
여기서, 상기 패드 산화막(12)은 습식산화방식을 이용하여 실리콘 기판(11)과 상기 패드 산화막(12)간의 계면에서 발생될 수 있는 점결함의 밀도를 102~ 103atoms/cm3이하로 감소시킨다. 이때, 상기 습식산화방식의 조건은 800 ~ 900℃의 온도 및 1 ~ 2.5Torr의 압력범위하에서 H20 + N20 기체의 혼합비(130 ~ 200sccm ; 70 ~ 90sccm)로서 50 ~ 150Å의 두께로 패드 산화막(12)을 형성한다.Here, the pad oxide film 12 reduces the density of point defects that may occur at the interface between the silicon substrate 11 and the pad oxide film 12 to 10 2 to 10 3 atoms / cm 3 or less by using a wet oxidation method. Let's do it. At this time, the wet oxidation method is a mixture of H 2 0 + N 2 0 gas at a temperature of 800 ~ 900 ℃ and a pressure range of 1 ~ 2.5Torr (130 ~ 200sccm; 70 ~ 90sccm) to a thickness of 50 ~ 150Å The pad oxide film 12 is formed.
또한, 상기 실리콘 질화막(13)은 반응기체로서 SiH4+ N20를 이용한 저압화학기상증착법을 이용하여 증착하며, 화학조성비를 Si3N4로 조절하여 패드 산화막(12)/실리콘 질화막(13) 계면에서 생성되는 압축응력을 102~ 103dyne/cm이하로 조절하여 실리콘 질화막(13)의 리프팅 현상을 억제한다. 이때, 상기 실리콘 질화막(13) 증착조건은 700 ~ 900℃의 온도 및 2.5 ~ 4Torr의 압력범위하에서 SiH4+ N20 기체의 혼합비(120 ~ 150sccm ; 150 ~ 180sccm)로서 1000 ~ 13000Å의 두께로 실리콘 질화막(13)을 형성한다. 그런다음, 실리콘 질화막(13) 상부에 소자 분리 예정 영역을 형성시키기 위한 감광막 패턴(14)을 형성한다.In addition, the silicon nitride film 13 is deposited using a low pressure chemical vapor deposition method using SiH 4 + N 2 0 as a reactor, and the pad oxide film 12 / silicon nitride film 13 by adjusting the chemical composition ratio to Si 3 N 4 . ) Lifting phenomenon of the silicon nitride film 13 is suppressed by adjusting the compressive stress generated at the interface to 10 2 ~ 10 3 dyne / cm or less. At this time, the deposition conditions of the silicon nitride film 13 is a mixture ratio of SiH 4 + N 2 0 gas at a temperature of 700 ~ 900 ℃ and a pressure range of 2.5 ~ 4 Torr (120 ~ 150sccm; 150 ~ 180sccm) to a thickness of 1000 ~ 13000Å The silicon nitride film 13 is formed. Then, a photosensitive film pattern 14 for forming a device isolation region is formed on the silicon nitride film 13.
다음 도 2b를 참조하면, 상기 감광막 패턴(14)을 마스크로 하여, 실리콘 질화막(13), 실리콘 산화막(12) 및 실리콘 기판(11)을 소정 깊이만큼 식각하여, 샬로우 트랜치(ST)를 형성한다. 이때, 상기 샬로우 트랜치(ST)는 바람직하게 1000~ 5000Å의 깊이로 트랜치되고, 샬로우 트랜치의 기하학적 구조에 관련된 인자로서 트랜치 바닥면과 측면의 사이각이 80 ~ 85도 정도된다. 그런다음, 상기 감광막 패턴을 제거한 후, 실리콘 질화막(13)을 이온주입장벽으로 하여 실리콘 기판과 불활성 이온인 10 ~ 20KeV의 아르곤 이온을 트랜치(ST)내에 이온주입 공정을 수행함으로써 상기 실리콘 기판을 비정질화 시킨다. 이때, 상기 아르곤 이온의 이온주입시 이온주입범위(Range Projection : Rp)값은 40 ~ 60Å이고, 틸트 각도는 2 ~ 4도로 조절하여 수행한다.Next, referring to FIG. 2B, the shallow trench ST is formed by etching the silicon nitride film 13, the silicon oxide film 12, and the silicon substrate 11 by a predetermined depth using the photoresist pattern 14 as a mask. do. At this time, the shallow trench (ST) is preferably trenched to a depth of 1000 ~ 5000Å, the angle between the trench bottom surface and the side as a factor related to the geometry of the shallow trench is about 80 ~ 85 degrees. After removing the photoresist pattern, the silicon substrate is amorphous by performing an ion implantation process using a silicon nitride film 13 as an ion implantation barrier and argon ions of 10 to 20 KeV inert ions into the trench ST. Make it angry. At this time, the ion implantation range (Range Projection: Rp) value of the ion implantation of the argon ion is 40 ~ 60Å, the tilt angle is performed by adjusting to 2 ~ 4 degrees.
이것은 상기 트랜치(ST) 상하부 모서리(T, B) 부분의 실리콘 원자간 활성화 에너지를 저하시켜 결합력을 감소시킴으로써 이후 공정인 산화공정 수행시 실리콘과 산소간의 반응속도가 증가되어 트랜치 모서리부분(T, B)에서의 각화현상이 억제되도록 한다This decreases the bonding force by lowering the activation energy between the silicon atoms of the upper and lower corners (T, B) of the trench (ST), thereby increasing the reaction rate between silicon and oxygen during the subsequent oxidation process. Keratinization
다음, 도 2c를 참조하면, 트랜치 식각공정시 누적된 식각 데미지 및 스트레스를 최소화 하기위해, 습식방식 또는 건식방식으로 트랜치내에 희생산화막(15a)을 형성한다. 또한 상기 습식방식으로 희생산화막을 형성하는 경우 공정조건은 800 ~ 900℃ 온도 및 1.8 ~ 4Torr의 압력범위하에서 H20 + N20 기체의 혼합비(120 ~ 140sccm : 80 ~ 100sccm)로써, 트랜치(ST)내에 희생산화막(15a)을 50 ~ 200Å 두께로 형성한다. 또한, 건식방식으로 희생산화막을 형성하는 경우, 공정조건은 950 ~ 1050℃ 온도 및 1.2 ~ 2.2Torr의 압력범위하에서 N2O + 02기체의 혼합비(110 ~ 140sccm : 180 ~ 230sccm)로써, 트랜치(ST)내에 희생산화막(15a)을 50 ~ 200Å 두께로 형성한다.Next, referring to FIG. 2C, a sacrificial oxide layer 15a is formed in the trench in a wet or dry manner in order to minimize the etch damage and stress accumulated during the trench etching process. In addition, in the case of forming the sacrificial oxide film by the wet method, the process condition is a trench ratio (120 to 140 sccm: 80 to 100 sccm) of H 2 0 + N 2 0 gas under a temperature range of 800 to 900 ° C. and a pressure of 1.8 to 4 Torr. A sacrificial oxide film 15a is formed to a thickness of 50 to 200 microseconds in ST). In addition, in the case of forming a sacrificial oxide film in a dry manner, the process conditions are trenches with a mixture ratio of N 2 O + 0 2 gas (110 to 140 sccm: 180 to 230 sccm) at a temperature of 950 to 1050 ° C. and a pressure range of 1.2 to 2.2 Torr A sacrificial oxide film 15a is formed in ST at a thickness of 50 to 200 GPa.
이어서, 상기 희생산화막(15a)이 형성된 트랜치(ST)내에 이후 매립될 갭필옥사이드막과의 접착강도를 향상시키기 위해 건식 또는 습식방식으로 산화공정을 수행하여 접착용 산화막(15b)을 형성한다. 이때, 건식방식으로 접착용 산화막(15b)을 형성하는 경우, 공정조건은 900 ~ 1000℃ 온도 및 1.8 ~ 3.3Torr의 압력범위하에서 N20 + 02기체의 혼합비(120 ~ 150sccm : 80 ~ 110sccm)로써 트랜치(ST)내에 절연용 산화막(15b)을 50 ~ 200Å 두께로 형성한다. 또한, 습식방식으로 접착용 산화막(15b)을 형성하는 경우, 공정조건은 800 ~ 850℃ 온도 및 1.2 ~ 3Torr의 압력범위하에서 H20 + N20 기체의 혼합비(120 ~ 140sccm : 80 ~ 100sccm)로써 트랜치(ST)내에 절연용 산화막(15b)을 50 ~ 200Å 두께로 형성한다.Subsequently, in order to improve the adhesion strength with the gap fill oxide film to be subsequently embedded in the trench ST in which the sacrificial oxide film 15a is formed, an oxidation process is performed in a dry or wet manner to form an adhesion oxide film 15b. At this time, in the case of forming the adhesive oxide film 15b in a dry manner, the process conditions are a mixture ratio of N 2 0 + 0 2 gas at a temperature of 900 ~ 1000 ℃ temperature and 1.8 ~ 3.3 Torr (120 ~ 150sccm: 80 ~ 110sccm ), An insulating oxide film 15b is formed in the trench ST to a thickness of 50 to 200 Å. In addition, when the adhesive oxide film 15b is formed in a wet manner, the process conditions include a mixture ratio of H 2 0 + N 2 0 gas at a temperature of 800 to 850 ° C. and a pressure range of 1.2 to 3 Torr (120 to 140 sccm: 80 to 100 sccm). ), An insulating oxide film 15b is formed in the trench ST to a thickness of 50 to 200 Å.
이어서, 도 2d를 참조하면, 상기 열산화막(15)이 형성된 트랜치(ST) 내에 갭필 옥사이드막(16)을 매립하여 반도체 소자의 소자분리막을 형성한다. 그런다음, 상기 아르곤 이온이 실리콘 기판에 대해 불활성 특성을 갖고 있으므로 실리콘 기판과의 화합물생성현상이 없기 때문에 갭필 옥사이드막(16)을 포함하는 실리콘 기판을 열처리 함으로써, 상기 아르곤 이온을 제거한다. 이때, 상기 열처리 공정은 900 ~ 1000℃ 온도 및 1.5 ~ 3Torr 압력하에서 N2+ Ar기체의 혼합비(100 ~ 140sccm : 100 ~ 120sccm)의 분위기에서 열처리한다. 이렇게 열처리함으로써 아르곤 이온의 농도를 5 ~ 7 ×104atoms/cm3이하로 유지한다.Subsequently, referring to FIG. 2D, a gapfill oxide film 16 is embedded in the trench ST where the thermal oxide film 15 is formed to form a device isolation film of a semiconductor device. Then, the argon ions are removed by heat treating the silicon substrate including the gapfill oxide film 16 because the argon ions have inert properties to the silicon substrate and there is no compound generation with the silicon substrate. At this time, the heat treatment process is heat-treated in the atmosphere of the mixing ratio (100 ~ 140sccm: 100 ~ 120sccm) of N 2 + Ar gas at 900 ~ 1000 ℃ temperature and 1.5 ~ 3 Torr pressure. In this way, the concentration of argon ions is maintained at 5 to 7 × 10 4 atoms / cm 3 or less.
이상에서 자세히 설명한 바와같이, 트랜치가 형성된 실리콘 기판상에 불활성 기체를 이온주입하여 비정질화 시킨다음, 트랜치 식각시 식각 데미지를 제거하고 갭필옥사이드막과의 접착강도를 향상시키기 위한 산화공정시 실리콘과 산소간의 반응속도를 증가시켜 트랜치 상, 하부 모서리 부분의 각화현상을 억제한다.As described in detail above, inert gas is implanted into the trench on the silicon substrate where the trench is formed to be amorphous, and the silicon and oxygen during the oxidation process to remove the etch damage and improve the adhesive strength with the gap fill oxide layer during the trench etching. Increasing the reaction rate of the liver to suppress the keratinization of the trench upper and lower corners.
이에의해, 반도체 소자의 누설전류, GOI(Gate Oxide Integrity) 특성 및 트랜지스터 특성을 개선시킴으로써, 소자의 신뢰성 증대와 생산수율 증대의 효과가 있다.Accordingly, by improving the leakage current, the gate oxide integrity (GOI) characteristics and the transistor characteristics of the semiconductor device, there is an effect of increasing the reliability of the device and increasing the production yield.
Claims (12)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000067351A KR20020037420A (en) | 2000-11-14 | 2000-11-14 | Method for forming isolation layer in semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000067351A KR20020037420A (en) | 2000-11-14 | 2000-11-14 | Method for forming isolation layer in semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20020037420A true KR20020037420A (en) | 2002-05-21 |
Family
ID=19698798
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020000067351A KR20020037420A (en) | 2000-11-14 | 2000-11-14 | Method for forming isolation layer in semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20020037420A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040008519A (en) * | 2002-07-18 | 2004-01-31 | 주식회사 하이닉스반도체 | Method for forming an isolation layer in a semiconductor device |
| US6849507B2 (en) * | 2000-04-04 | 2005-02-01 | International Rectifier Corporation | Process for manufacture of low voltage power MOSFET device |
| US7229872B2 (en) | 2000-04-04 | 2007-06-12 | International Rectifier Corporation | Low voltage power MOSFET device and process for its manufacture |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR970072304A (en) * | 1996-04-24 | 1997-11-07 | 김주용 | Device isolation film of semiconductor device and manufacturing method thereof |
| KR19990011636A (en) * | 1997-07-24 | 1999-02-18 | 윤종용 | Device Separation Method of Semiconductor Device |
| JPH11111710A (en) * | 1997-10-01 | 1999-04-23 | Nec Corp | Semiconductor device and its manufacture |
| US5915195A (en) * | 1997-11-25 | 1999-06-22 | Advanced Micro Devices, Inc. | Ion implantation process to improve the gate oxide quality at the edge of a shallow trench isolation structure |
| JP2000058635A (en) * | 1998-08-11 | 2000-02-25 | Mitsubishi Electric Corp | Formation of inter-element isolating insulation film and semiconductor device |
-
2000
- 2000-11-14 KR KR1020000067351A patent/KR20020037420A/en not_active Application Discontinuation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR970072304A (en) * | 1996-04-24 | 1997-11-07 | 김주용 | Device isolation film of semiconductor device and manufacturing method thereof |
| KR19990011636A (en) * | 1997-07-24 | 1999-02-18 | 윤종용 | Device Separation Method of Semiconductor Device |
| JPH11111710A (en) * | 1997-10-01 | 1999-04-23 | Nec Corp | Semiconductor device and its manufacture |
| US5915195A (en) * | 1997-11-25 | 1999-06-22 | Advanced Micro Devices, Inc. | Ion implantation process to improve the gate oxide quality at the edge of a shallow trench isolation structure |
| JP2000058635A (en) * | 1998-08-11 | 2000-02-25 | Mitsubishi Electric Corp | Formation of inter-element isolating insulation film and semiconductor device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6849507B2 (en) * | 2000-04-04 | 2005-02-01 | International Rectifier Corporation | Process for manufacture of low voltage power MOSFET device |
| US7229872B2 (en) | 2000-04-04 | 2007-06-12 | International Rectifier Corporation | Low voltage power MOSFET device and process for its manufacture |
| US8487368B2 (en) | 2000-04-04 | 2013-07-16 | International Rectifier Corporation | Low voltage power MOSFET device and process for its manufacture |
| KR20040008519A (en) * | 2002-07-18 | 2004-01-31 | 주식회사 하이닉스반도체 | Method for forming an isolation layer in a semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7479440B2 (en) | Method of forming an isolation structure that includes forming a silicon layer at a base of the recess | |
| JPH08139176A (en) | Manufacture of semiconductor device | |
| JPH11145273A (en) | Manufacture of semiconductor device | |
| JP3039978B2 (en) | Method of forming an electric field isolation structure and a gate structure in an integrated MISFET device | |
| KR101033359B1 (en) | method for fabricating semiconductor device | |
| KR20020037420A (en) | Method for forming isolation layer in semiconductor device | |
| KR100639194B1 (en) | Method for forming isolation layer in semiconductor device | |
| KR101077014B1 (en) | Method for forming the isolation layer of semiconductor device | |
| KR20040008519A (en) | Method for forming an isolation layer in a semiconductor device | |
| KR100336567B1 (en) | Isolation method of semiconductor device | |
| KR940005611B1 (en) | Method for memory apparatus of in the semiconductor | |
| US6887767B2 (en) | Method for manufacturing semiconductor device | |
| JPH1050693A (en) | Manufacture of semiconductor device | |
| KR20020010971A (en) | Method for forming isolation in semiconductor | |
| KR100595877B1 (en) | Method for manufacturing semiconductor device | |
| KR100514516B1 (en) | Method for fabricating dual gate insulator | |
| CN112349586A (en) | Method for forming semiconductor structure | |
| KR100357304B1 (en) | A method for forming a field oxide of a semiconductor device | |
| KR100745056B1 (en) | Method for forming the Isolation Layer of Semiconductor Device | |
| KR100382556B1 (en) | Method for manufacturing isolation of semiconductor device | |
| TW419782B (en) | Method for forming shallow trench isolation in integrated circuits | |
| KR20080088680A (en) | Method for forming shallow trench isolation of semiconductor device | |
| KR20010038007A (en) | Method for isolating semiconductor devices | |
| KR20040002014A (en) | Method of forming a isolation layer in a semiconductor device | |
| KR20010063262A (en) | Method for isolating semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E601 | Decision to refuse application |