KR100720663B1 - Device for synchronizing with dual port ram and microprocessor using the device - Google Patents

Abstract

The present invention relates to a dual port RAM synchronizing apparatus and a microprocessor using the dual port RAM synchronizing apparatus. The microprocessor is connected to the DPRAM synchronizer to transmit / CS (Chip Select), / RD (Read) and / WR (Write) signals to the DPRAM synchronizer, and the IRQ terminal of the microprocessor is connected to the BUSY signal line of the DPRAM . The DPRAM synchronizing apparatus includes a first signal input unit receiving a BUSY signal from a DPRAM and a second signal input unit receiving a / CS (Chip Select), / RD (Read), and / A signal output unit for outputting signals input to the second signal input unit to a corresponding terminal of the DPRAM and a signal output unit for interrupting output of a signal to the signal output unit when the BUSY signal is input to the first signal input unit, .

If a BUSY signal is output from the DPRAM, / CS (Chip Select), / RD (Read) and / WR (Write) signals of the microprocessor are blocked by the signal interrupter of the DPRAM synchronizer And in response to a signal input to the IRQ terminal, the microprocessor attempts to reconnect to the DPRAM in software.

DPRAM, BUSY signal line, interrupt service routine

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a dual-port RAM synchronizing apparatus and a microprocessor using the same,

FIG. 1 is a configuration diagram illustrating a DPRAM synchronizing apparatus and a microprocessor according to a preferred embodiment of the present invention connected to a DPRAM. Referring to FIG.

2 is a block diagram schematically illustrating an internal configuration of a DPRAM synchronizing apparatus according to a preferred embodiment of the present invention.

Description of the Related Art

10: DPRAM synchronizer

20: DPRAM

30: a first microprocessor

40: a second microprocessor

100: first signal input section

110: second signal input section

120: Signal output section

130:

200: first data area

210: second data area

220: Signal input section

230:

[0001] The present invention relates to a DPRAM synchronizing apparatus enabling use of a DPRAM and a microprocessor connecting the DPRAM synchronizing apparatus to use the DPRAM. More particularly, the present invention relates to a microprocessor connected to a microprocessor which does not support the use of a DPRAM, A DPRAM synchronizer for preventing a data collision by allowing a BUSY signal to be processed, and a microprocessor connected to the DPRAM synchronizer to use the DPRAM.

Dual Port RAM (hereinafter referred to as 'DPRAM') is a RAM that has two address lines and can be accessed by two microprocessors simultaneously. The DPRAM described above is equivalent to accessing a general RAM for a microprocessor, except for driving the BUSY line, which is suitable for an environment where the two processors are tightly coupled.

In order to transfer data between the two microprocessors using the DPRAM as described above, the processors must be able to handle the bus wait signal in hardware, or the processors must be able to process the interrupt signal from the DPRAM.

However, the processors often do not support a bus wait signal, and sometimes the interrupt signal can not be processed due to application to a system requiring precise control in terms of time. In such a case, data transmission between the two processors should be implemented so as to avoid collision solely with software.

In addition, when two microprocessors access the same address simultaneously, the DPRAM applies a busy signal to one microprocessor so that two microprocessors access the same address at the same time to prevent data collision. However, since the DPRAM-supporting processor has a busy line, the DPRAM can transmit the synchronization signal through the busy line. However, since the processor that does not support the DPRAM does not have a separate busy line, the DPRAM transmits the synchronization signal Can not be transmitted.

Accordingly, the present applicant proposes a method of transferring data using a DPRAM even if the processor does not support DPRAM.

SUMMARY OF THE INVENTION An object of the present invention is to provide a DPRAM synchronizing apparatus which can prevent a data conflict in a DPRAM from occurring in a microprocessor that does not support the use of the DPRAM.

It is another object of the present invention to provide a microprocessor capable of processing a BUSY signal from a DPRAM as an interrupt even if it does not have a signal line for supporting use of the DPRAM.

According to an aspect of the present invention, there is provided a DPRAM synchronization apparatus for enabling a DPRAM to be used for a microprocessor that does not support the use of a DPRAM,

 A first signal input unit for receiving a BUSY signal from the DPRAM,

A second signal input unit for receiving a / CS (Chip Select), / RD (Read), and / WR (Write) signals from a microprocessor that does not support the use of the DPRAM,

A signal output unit for outputting the signals input to the second signal input unit to corresponding terminals of the DPRAM,

And a signal blocking unit for blocking a signal from being output to the signal output unit when the BUSY signal is input to the first signal input unit,

When the BUSY signal is input from the DPRAM, the output of the / CS, / RD, and / WR signals to the DPRAM is blocked, thereby enabling the use of the DPRAM of the microprocessor.

Another aspect of the present invention relates to a microprocessor which does not support the use of a DPRAM, wherein the microprocessor is connected to a DPRAM synchronizer and outputs a / CS (Chip Select) / RD (Read) And the IRQ terminal of the microprocessor is connected to the BUSY signal line of the DPRAM,

The DPRAM synchronizer comprises:

A first signal input unit for receiving a BUSY signal from the DPRAM,

A second signal input unit receiving a / CS (Chip Select), / RD (Read), and / WR (Write) signals from the microprocessor;

A signal output unit for outputting the signals input to the second signal input unit to corresponding terminals of the DPRAM,

And a signal blocking unit for blocking a signal from being output to the signal output unit when a BUSY signal is input to the first signal input unit,

If a BUSY signal is output from the DPRAM and is input to the IRQ terminal of the DPRAM synchronizer and the microprocessor, the / CS (Chip Select) / RD (Read) / WR The output to the DPRAM is interrupted by the signal interrupter of the synchronizing device and the microprocessor attempts to reconnect to the DPRAM in response to the signal input to the IRQ terminal.

Hereinafter, a DPRAM synchronizer 10 connected to a microprocessor that does not support the use of a DPRAM according to a preferred embodiment of the present invention will be described with reference to the accompanying drawings, and a DPRAM synchronizer 10 using the DPRAM synchronizer 20 will be described in detail.

1 is a block diagram illustrating a DPRAM synchronizer 10 and a first microprocessor 30 and a second microprocessor 40 connected to a DRPAM 20 according to a preferred embodiment of the present invention. As shown in FIG. 1, the first microprocessor 30 and the second microprocessor 40 transmit data through the DPRAM 20. The first microprocessor 30 does not support the use of the DPRAM And the second microprocessor 40 supports the use of the DPRAM.

The DPRAM 20 includes a first data area 200, which is a write-only area of the first microprocessor and a read-only area of the second microprocessor, a second data area 200, which is a read-only area of the first microprocessor and a write- A signal input unit 220 to which a control signal such as an area 210, / CS (Chip Select), / RD (Read) or / WR (Write) signal is inputted, and two microprocessors And a control unit 230 for outputting a BUSY signal to the first or second microprocessor in order to prevent a collision.

The second microprocessor 40 is a microprocessor that supports the use of the DPRAM. Since the BUSY signal output from the control unit of the DPRAM is input to the corresponding terminal of the second microprocessor, the second microprocessor 40 needs to be connected to a separate DPRAM synchronizer none.

The first microprocessor 30 is a microprocessor that does not support the use of the DPRAM and can not process the BUSY signal output from the control unit of the DPRAM. Therefore, the first microprocessor 30 can control / CS (Chip Select), / RD (Read), and / WR (Write) signals via the DPRAM synchronizer 10 to process the BUSY signal output from the DPRAM And receives the BUSY signal from the DPRAM 20 at the IRQ terminal of the first microprocessor 30. [

If a BUSY signal for preventing collision is output from the control unit of the DPRAM 20 and input to the IRQ terminal of the DPRAM synchronizer 10 and the first microprocessor 30, The output of the / CS (Chip Select), / RD (Read), and / WR (Write) signals input from the first microprocessor is blocked to prevent the first microprocessor from writing or reading data to or from the DPRAM. In addition, a BUSY signal is input to the IRQ terminal of the first microprocessor 30 to operate an interrupt service routine (Interrupt Service Routine), thereby attempting to connect to the DPRAM in software again. A detailed description of the above-described interrupt service routine will be described later.

Therefore, even in the case of a microprocessor which does not support the use of the DPRAM according to the present invention, it is possible to prevent collision with another microprocessor, thereby making it possible to use the DPRAM.

Hereinafter, the configuration and operation of the DPRAM synchronizer 20 according to the preferred embodiment of the present invention will be described in detail with reference to FIG.

2, the DPRAM synchronizer 10 according to the preferred embodiment of the present invention includes a first signal input unit 100, a second signal input unit 110, a signal output unit 120, and a signal blocking unit 130, .

The first signal input unit 100 receives a BUSY signal from the DPRAM.

The second signal input unit 110 receives a / CS (Chip Select), / RD (Read), and / WR (Write) signals from a microprocessor that does not support the use of the DPRAM.

The signal output unit 120 outputs signals input to the second signal input unit 110 to corresponding terminals of the DPRAM.

The signal blocking unit 130 determines whether a BUSY signal is input to the first signal input unit 100 and outputs a signal to the signal output unit when a BUSY signal is input to the first signal input unit .

Therefore, when the BUSY signal is not input from the DPRAM, the DPRAM synchronizing apparatus 10 according to the preferred embodiment of the present invention performs a / CS (Chip Select), RD (Read), / WR (Read / Write) signal from the microprocessor is prevented from being transferred to the DPRAM when the BUSY signal is input from the DPRAM, Thereby preventing the processor from writing or reading data to the DPRAM. As a result, two microprocessors can prevent the DPRAM from colliding at the same time.

Hereinafter, the interrupt service routine of the first microprocessor operated when the BUSY signal from the DPRAM is input to the IRQ terminal of the first microprocessor will be described in detail. The first microprocessor accesses the DPRAM using the interrupt service routine and writes or reads the data. After the data read or write operation, a code "No Operation" is added to check the malfunction of the software. One embodiment of the program code for the data read function (DPRAM_READ) and the data write function (DPRAM_WRITE) created in accordance with the preferred embodiment of the present invention will be described below as an example.

char DPRAM_READ (dpram_address)

{

data ← [dpram_address];

No Operation;

return data;

}

void DPRAM_WRITE (dpram_address, data)

{

[dpram_address] ← data;

No Operation;

}

As described above, by using the code "No Operation" added to the data reading and writing function, it is possible to check whether or not the interruption currently occurring in the interrupt service routine is an interrupt related to the DPRAM.

The following program code is an exemplary illustration of one embodiment of the program code for the interrupt service routine according to the preferred embodiment of the present invention.

interrupt service routine

{

disable interrupt;

preserve flag register;

get PREVIOUS_PC from stack;

while ([PREVIOS_PC] is "No Operation")

PREVIOUS_PC ← PREVIOUS_PC - 1;

restore flag register;

enable interrupt;

return to PREVIOUS_PC;

}

When the instruction of the PC position at which the PC value at the time of interruption is obtained by executing the interrupt service routine as described above is "No Operation ", it returns to the position of the previous instruction so that interruption by IRQ signal input Together they will be able to retry DPRAM access.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be understood that various changes and modifications may be made without departing from the spirit and scope of the invention. It is to be understood that the present invention may be embodied in many other specific forms without departing from the spirit or essential characteristics thereof.

According to the present invention, even if the microprocessor does not support the DPRAM, it is possible to process the BUSY signal transmitted from the DPRAM in order to prevent data collision. As a result, the microprocessor can also use the DPRAM . ≪ / RTI >

Claims (2)

delete For microprocessors that do not support the use of DPRAM, The microprocessor is connected to the DPRAM synchronizer to transmit / CS (Chip Select), / RD (Read), and / WR (Write) signals to the DPRAM synchronizer, The IRQ terminal of the microprocessor is connected to the BUSY signal line of the DPRAM, The DPRAM synchronizer comprises: A first signal input unit for receiving a BUSY signal from the DPRAM, A second signal input unit receiving a / CS (Chip Select), / RD (Read), and / WR (Write) A signal output unit for outputting the signals input to the second signal input unit to corresponding terminals of the DPRAM, And a signal blocking unit for blocking a signal from being output to the signal output unit when a BUSY signal is input to the first signal input unit, If a BUSY signal is output from the DPRAM and is input to the IRQ terminal of the DPRAM synchronizer and the microprocessor, the / CS (Chip Select) / RD (Read) / WR The output to the DPRAM is interrupted by the signal interrupter of the synchronizing device, and in response to the signal input to the IRQ terminal, the microprocessor attempts to reconnect to the DPRAM in a software manner using an interrupt routine.

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