KR100210813B1 - Apparatus for resetting packet handler in full electronic switching system - Google Patents

Abstract

The present invention relates to an apparatus for resetting a packet handler of an electronic switch, which is suitable for causing a device control board to reset packet handlers using a parallel bus address line in a TDX-100 electronic switch. When there are multiple in-packet handler boards, there is a drawback that a complicated signal line must be configured because as many separate reset signal lines must be connected as the number of boards in the upper device control board. By accessing (30, 40) to reset the packet handler board in case of system initialization or malfunction of the lower packet handler board (30, 40), the packet handler board, which is the lower device, is reset without a separate complicated reset signal line. So that the entire device Since it will be simplified to improve the above drawbacks.

Description

Packet handler reset device of electronic switchboard

The present invention relates to a packet handler reset device of an electronic switchboard, and more particularly, to a device control board in a TDX-100 electronic switchboard, suitable for causing the device control board to reset packet handlers using a parallel bus address line. It relates to a packet handler reset device of the electronic exchange.

In this regard, when the device control board according to the related art resets the packet handlers that are the lower devices, there is a reset signal line between the device control board and the lower packet handlers to reset the lower packet handlers in the device control board. In order to do this, the lower packet handler is reset by activating the reset signal line.

However, in the related art, when there are several packet handler boards as lower devices, a complicated reset signal line has to be formed since separate reset signal lines must be connected in the upper device control board.

The present invention has been made to solve the drawbacks of the prior art, by using a method that allows the packet handler board to be reset by accessing a specific packet handler board through an address line. It is an object of the present invention to provide a packet handler reset device of an electronic switchboard that enables the packet handler board to be reset.

In order to achieve the above object, the present invention provides a packet switch, an upper processor, and a time switch, wherein the switch includes the above-described packet block through a time switch under control of a device control board. The lower 16 sheets that set up or disconnect the packet link by processing the received packet data and transmitting it to another packet handler board through the device control board, or by transmitting control packets such as call connection request and call disconnection request to the upper processor. Control the lower 16 packet handler boards through communication with the packet handler board and the upper processor, and exchange the packet data processed by the packet handler board between the 16 packet handler boards or from the 16 packet handler boards. A device that analyzes the processed control data to request and report the processing to the upper processor. It characterized by comprising a device control board.

1 is a block diagram showing an embodiment of a packet handler reset apparatus of an electronic switch according to the present invention.

2 is a block diagram showing an embodiment of a packet handler board according to FIG.

* Explanation of symbols for main parts of the drawings

10: packet block 20: device control board

30,40: 1st, 16th packet handler board 50: the upper processor

60: time switch 110: central processing unit

120: reset unit 130: address decoder

140: local bus matching unit 150: other functions

160: packet shared memory 170: packet memory arbitration unit

The above and other objects and various advantages of the present invention will become more apparent from the preferred embodiments of the invention described below with reference to the accompanying drawings by those skilled in the art.

Hereinafter, an embodiment of the present invention for achieving the above object in detail.

Referring to FIG. 1, FIG. 1 is a block diagram showing an embodiment of an apparatus for resetting a packet handler of an electronic switch according to the present invention. The packet block 10, the upper processor 50, and the time switch 60 are shown in FIG. In the all-electronic exchanger including the above, the above-described packet block 10 processes the packet data received through the above-described time switch 60 under the control of the device control board to process other packet handlers through the device control board. The lower 16 packet handler boards 30 and 40 for setting up or cutting down the packet link by transmitting to the board or transmitting control packets for the call connection request and the call disconnection request to the upper processor 50 described above, Through the communication with the processor 50, the lower 16 packet handler boards 30 and 40 described above are controlled through a 16-bit local bus, and the packet data processed by the packet handler board is controlled. Interchange between the 16 packet handler boards 30 and 40 described above, or analyze and process control data processed from the 16 packet handler boards 30 and 40 described above to process and report to the upper processor 50 described above. The device control board 20 is made to include.

The present invention thus achieved will be described in detail with reference to FIG.

First, the 16 packet handler boards 30 and 40 in the packet block 10 process the packet data received through the time switch 60 under the control of the device control board 20 to process the device control board 20. The packet link is set up or disconnected by transmitting to another packet handler board or by transmitting control packets such as a call connection request and a call disconnection request to the higher processor 50.

Next, the device control board 20 controls the lower 16 packet handler boards 30 and 40 described above through a 16-bit local bus through communication with the upper processor 50 described above, and is processed by the packet handler board. The packet data is exchanged between the above-described 16 packet handler boards 30 and 40, or the control data processed from the above-described 16 packet handler boards 30 and 40 is analyzed and transmitted to the upper processor 50 described above. Processing requests and reports.

FIG. 2 is a block diagram showing an embodiment of the packet handler boards 30 and 40 according to FIG.

First, the local bus matching unit 140 matches a signal so that its packet handler board can communicate with the above-described device control board 20 through the above-described 16-bit local bus.

Next, the device control board 20 may access the packet sharing memory 160 existing in each packet handler board 30 and 40 to store or read the packet data. In this case, the address decoder 130 may Packet sharing memory 160 receives the address signal from the device control board 20 as described above via the local bus matching unit 140 and decodes the address signal for writing / reading the packet data of the device control board 20. To provide.

In this case, when the decoded address signal is a specific reset region, the address decoder 130 activates the reset signal line, and the reset unit 120 detects this to reset the entire packet handler board.

In addition, the central processing unit (CPU) 110 detects the above-described reset signal of the reset unit 120, and performs the above-described packet sharing memory 160 by arbitration of the packet memory arbitration unit 170. Can be accessed.

Next, the packet memory arbitration unit 170 accesses the packet sharing memory 160 described above by the above-described device control board 20, the above-described central processing unit 110, and an X.25 controller (not shown). If desired, only one access is performed through mediation between them according to a predetermined priority.

The other function unit 150 is connected to the time switch 60 to control the data flow of the central processing unit 110 described above.

That is, one device control board 20 according to the present invention controls the 16 packet handler boards 30 and 40 to perform data transmission between these packet handler boards 30 and 40. In the case of malfunction of the handler boards 30 and 40, the device control board 20 may reset the respective lower packet handler boards 30 and 40 by the above-described method.

As described above, the present invention provides a method for accessing the packet handler boards 30 and 40 through a 16-bit local bus so that the corresponding packet handler boards are reset when a system initialization or a lower packet handler board 30 or 40 malfunctions. By using this function, it is possible to reset the packet handler board as a lower device without a separate complicated reset signal line, thereby simplifying the whole device.

Claims (2)

In an electronic switch comprising a packet block, an upper processor, and a time switch, the packet block processes packet data received through the time switch under the control of a device control board, and receives another packet handler through the device control board. 16 lower packet handler boards to set up or tear down a packet link by transmitting to a board or transmitting control packets for a call connection request and a call disconnection request to the upper processor. Controls the packet handler board through a 16-bit local bus and exchanges packet data processed by the packet handler board between the 16 packet handler boards or processes processed from the above-described 16 packet handler boards. Analyze the data to process and report to the upper processor Before the packet handler, the reset device of the electronic switching device comprises a control board. The apparatus of claim 1, wherein at least one or more packet handler boards of the 16 packet handler boards match signals so that their packet handler boards can communicate with the device control board via the 16-bit local bus. A local bus matching unit; Decode the address signal from the device control board output from the local bus matching section to allow the device control board to write or read data to a preset packet sharing memory through the local bus matching section, and the decrypted address is reset to a specific reset value. An address decoder to activate the reset signal line in the case of the region; A reset unit for detecting the reset signal line when the decoder of the present invention activates the reset signal line and resetting its packet handler board; A central processing unit for detecting a reset signal of the reset unit and accessing the packet shared memory by arbitration of a packet memory arbitration unit; A packet memory arbitration unit for arbitration according to a priority order so that the device control board and the central processing unit can access the packet shared memory so that only one can access it; And a second function unit connected to the time switch to control the data flow of the central processing unit.