KR0136520B1 - Distributed control system - Google Patents

Abstract

The present invention relates to a distributed control system for operating a plurality of subscriber apparatuses in a high speed communication system if necessary, and provides information such as a network management frame, a call setup frame, or an error in data that the communication devices do not process. A plurality of (n) high speed data transfer units 1 incorporating a control unit 3 for collecting processing and transferring information as necessary; The processor includes a real-time processing unit 2 that controls the plurality of high-speed data transmission units 1 corresponding to each port, collects information, and configures a distributed processing system to smoothly process the communication data. It can be applied to communication systems that can adapt to bottlenecks and complicated network structures, and can be applied not only to communication but also to general control systems to improve productivity.

Description

Distributed control system

1 is a schematic diagram of a distributed control system for high speed communication;

2 is a schematic diagram of a built-in control unit.

3 is a diagram illustrating a communication protocol between a local interface and a device.

4 is a diagram illustrating how two interrupter sources share one interrupt request signal.

* Explanation of symbols for main parts of the drawings

1: High speed data transfer unit 2: Real time processing unit

3: built-in control unit 21: processor bus

22: local memory 23: dual port RAM

24: shared bus interface 25: local interface

26: control processor

The present invention relates to a distributed control system for operating multiple subscriber devices in a high speed communication system.

Conventionally, a communication system having several subscribers has managed a network using a centralized processor. In the case of low-speed communication, data processing was possible due to the high speed of the processor, but as the communication speeds up, another processing method capable of processing the data in real time is required. Such high-speed data processing is possible using hardware instead of software, but processing of management functions due to complicated network requires high performance of the processor. However, high performance processors are expensive and result in system development that is processor dependent. In addition, the high performance speed of the processor does not keep up with the speed of communication data and complicated network configuration.

That is, due to the high speed of communication data and the complicated network configuration, a processor capable of processing the data in real time is required. However, high performance processors are economically burdensome, resulting in a problem that system performance is limited to the processor.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems with the prior art. In the high-speed communication system having a plurality of subscriber ports, the present invention uses a built-in processor to distribute data processing. It is an object of the present invention to provide a distributed control system that enables high-speed communication data processing and a communication system having multiple ports to operate smoothly.

In order to achieve the above object, the present invention provides a control for collecting and processing information such as a network management frame, a call setup frame, or an error occurring in data, which are not processed by communication devices, and transmitting the information as necessary. A plurality of high speed data transfer units incorporating a unit; It is characterized by controlling the plurality of high-speed data transmission units corresponding to each port, and having a real-time processing unit for collecting information to process high-speed data in real time.

The present invention has a built-in processor in each port of the high-speed communication system, and performs the function of processing and managing data transmitted and received. At the system level, items to be delivered to or received from the main processor are handled by interprocessor communication. In addition, an interrupt-based local interface is provided for communication between an embedded processor and a device, and an interrupt method is proposed for when multiple devices are connected to one processor. In addition, one interrupt request signal line allows two or more interrupt sources to provide interrupt service without using the daisy chain method.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is a structure diagram of a distributed control system for high speed communication, wherein the high speed data transmission unit 1 is a port and the real time processing unit 2 is a main control device.

The high speed data transfer unit 1 is composed of a built-in control unit 3 and devices.

The device includes an external reception line 5 and a transmission line 6 connected to each other, and processes data frames. These devices process communication data frames in hardware.

The built-in control unit 3 collects and processes information such as a network management frame, a call setup frame, or an error in data, which are not processed by communication devices, and transmits the information to a real-time processing unit as necessary.

The real time processing unit 2 controls a high speed data transmission unit corresponding to each port and collects information.

The high-speed data transmission units 1 and the real-time control unit 2 are connected to a block transmission-based data transmission bus 4, which provides information at each port that requires real-time processing during service. It provides the function to transmit the data block to the real time processing unit or vice versa.

2 shows the configuration of the built-in control unit 3 of FIG.

The control processor 26 is connected to the local memory 22, the dual port RAM 23, the shared bus interface 24, and the local interface 25 through the processor bus 21.

The local memory 22 is composed of an SRAM used by the control processor 26, and the dual port RAM 23 includes a control processor 26 and a real time processing unit (3) of the built-in control unit (Fig. 1). It is used to communicate real-time processing data between 2) of FIG.

The local interface 25 provides the control processor 26 with access to the devices in the embedded control unit (3 in FIG. 1) and also with the high speed data transfer unit device.

3 shows a communication protocol between the embedded control unit 36 and the device 31 in the high speed data transfer unit.

When an event such as reception or transmission of data or an error occurs in any device, the device activates the IRQx signal 32, which is an interrupt request signal, in the embedded control unit 36.

The built-in control unit 36 responds to the interrupt request input via the bus 33 whether the IRQx signal is activated or not. When a signal indicating that an interrupt is processed is transmitted to the local interface 37, the local interface transmits an interrupt response signal corresponding to the interrupt by activating the IACKx 34. At the same time, the local interface 37 sends a signal via the interrupt acknowledgment bus 33 to the built-in control unit 36 to start an interrupt service. The device 31 receiving the interrupt response signal deactivates the IRQx signal, which is an interrupt request signal. The built-in control unit 36 having received the interrupt service start signal reads the interrupt register through the register read / write 35 to determine the cause of the interrupt and then start the corresponding service.

4 shows how two interrupt sources share one interrupt request signal in the embedded control unit 43.

This is necessary when the number of devices 41 and 42 is larger than the interrupt signal line. In this case, there is a daisy chain method, but this method requires a lot of additional elements and signal lines in hardware and has a long processing time.

The device 1 41 and the device 2 42 are interrupt sources sharing one interrupt signal line, and the built-in control unit 43 is a main agent for interrupt service.

The address decoder 44 decodes the ADDR [p: 0] 45 coming from the embedded control unit 43 to generate a CS signal 46 that determines chip selection. DATA [n-1: 0] (47) occurs in the built-in control unit 43 so that the upper DATA [n-1: m + 1] (48) is connected to the device 1 (41) and the lower DATA [m: 0 49 is connected to device 2 42.

The operation description of the system having the above configuration is as follows.

First, when the device 1 41 requests an interrupt, the built-in control unit 43 issues an interrupt response by the mechanism described in FIG. When the interrupt register is read, the interrupt cause register of the device 1 41 is read by DATA [n-1: m], and the interrupt cause register of the device 2 42 is read by DATA [m-1: 0]. The embedded control processor (26 in FIG. 2) recognizes through this value that an interrupt has been requested by the device 1 (41). When the device 2 42 requests an interrupt, the interrupt is processed in the same manner.

The present invention as described above can be applied to a communication system that can be adapted to the bottleneck of the processor and the complicated network structure by configuring a distributed processing system to facilitate the processing of the communication data is accelerated, it is applied to the general control system as well as communication There is an effect that can be improved productivity.

Claims (3)

In a high-speed communication system, a control unit (3) which collects and processes information such as a network management frame, a call setup frame or a data error that are not processed by the communication devices, and transmits the information as necessary is provided. A plurality of (n) high speed data transfer units 1; And a real-time processing unit (2) for controlling the plurality of high-speed data transmission units (1) corresponding to each port and collecting information, so as to process high-speed data in real time. The control unit (3) of claim 1, further comprising: a control processor (26) connected to other devices through a processor bus (21); A local memory 22 connected to the control processor 26 via a processor bus; A dual port RAM 23 for communicating real time processing data between the control processor 26 and the real time processing unit 2; A local interface 25 enabling communication between the control processor 26 and the fast data transfer unit device; And a block transmission-based shared bus which processes the state change of the port in real time in a block transmission manner with the control processor (26). The method of claim 1, wherein when two or more interrupt sources are connected to one interrupt request signal line, a register value in which different bit fields are allocated from two or more interrupt sources at the same time without using a conventional daisy chain method. Distributed control system, characterized in that configured to become an interrupt service by reading.