KR20020049331A - Matching Apparatus between Peripheral Processor and Device Controller - Google Patents

Abstract

PURPOSE: A device for matching a peripheral processor and a device controller is provided to prevent the loss of data by separately storing data and addresses in a buffer, by transmitting an alarm signal to a peripheral processor and transmitting an interrupt signal to a control unit in case that the peripheral processor and the control unit access the same area in a memory unit at the same time. CONSTITUTION: A DC(Device Controller, 200) is equipped with a bus mediation unit(210), an address buffer unit(240), a data buffer unit(250), a control unit(220) and a memory unit(130). An address comparison unit(212) receives an address in a memory to be accessed by a peripheral processor(20) and the control unit(220). The address comparison unit(212) compares the address. After that the address is corresponded, the comparison unit(212) transmits and stores the address to the address buffer unit(240). In addition, the comparison unit(212) transmits an alarm signal to the peripheral processor(20) and an interrupt signal to the control unit(220). The address buffer unit(240) stores the address transmitted under the control of the comparison unit(212). The data buffer unit(250) stores data transmitted to the memory unit(130) from the peripheral processor(20) in the first buffer and data transmitted to the memory unit(130) from the control unit(220) in the second buffer.

Description

Matching Apparatus between Peripheral Processor and Device Controller}

The present invention relates to a matching device between a peripheral processor and a device control device, and more particularly, to a matching device between a peripheral processor and a device control device to prevent data loss that may occur when the peripheral processor and the control unit simultaneously access the same area on the memory unit. It is about.

1 is a block diagram showing a conventional device control apparatus.

In general, the peripheral processor 20 provided in the exchanger is a device controller according to the control of the main processor 10 or an algorithm set to F / W (Firm Ware). 100 is used to transmit and receive the general data processed by the devices 30a to 32n, which are data processing apparatuses, and to transmit and receive status information and control information. However, data transmitted by the devices 30a to 32n may not be directly transmitted to the peripheral processor 20, but may be stored in the memory unit 130 and then transferred to the peripheral processor 20 according to a command of the peripheral processor 20. .

The DC 100 of the conventional exchanger includes a bus arbitration unit 110, a control unit 120, and a memory unit 130.

Here, the bus arbitration unit 110 is directly connected to the peripheral processor 20 through the TD-BUS, converts the serial signal transmitted from the peripheral processor 20 into a parallel signal, and then stores the memory unit through the address / data bus. On the contrary, the data is transmitted to the peripheral processor 20 by converting the parallel signal into a serial signal. In addition, the bus arbitration unit 110 arbitrates bus occupancy authority between processors by signals such as / CS (Chip Select), / OE (Out Enable), / WR (Write / Read), and the peripheral processor 20. ) Is analyzed to determine whether to write to or read from the memory unit 130.

The memory unit 130 has two ports, one of which is connected to the bus arbitration unit 110 and an address / data bus, and the other of which is connected to the control unit 120 and the address / data bus. The memory unit 130 stores data and control signals transmitted and received between the devices 30a to 30b and the peripheral processor 20. The memory unit 130 is generally implemented using DPRAM (Dual Ported Random Access Memory).

The controller 120 performs IPC communication with the devices 30a to 30b and reads and processes the instructions of the peripheral processor 20 stored in the memory 130, or the data transmitted from the devices 30a to 30b. Receives the data to the memory unit 130 via the address / data bus to be stored.

As described above, communication between the peripheral processor 20 and the DC 100 is performed through the memory unit 130 in the DC 100. That is, the peripheral processor 20 and the control unit 120 write or read data or control signals to the memory unit 130 in accordance with the arbitration of the bus arbitration unit 110. The peripheral processor 20 and the control unit 120 May simultaneously access the same region of the memory unit 130, and data loss may occur due to an address conflict between the peripheral processor 20 and the controller 120, and may cause a problem in data transmission in real time.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object thereof is to provide an alarm signal to a peripheral processor while storing the data and address separately in a buffer when the peripheral processor and the controller simultaneously access the same area on the memory unit. By transmitting the interrupt signal to the controller, the peripheral processor and the controller can write or read the correct data on the memory unit again using the address and data stored in the buffer to prevent data loss due to an address conflict. Is to help prevent that.

1 is a block diagram showing a conventional device control apparatus.

2 is a block diagram showing the configuration of a device controller matching with a peripheral processor in accordance with the present invention.

* Description of the symbols for the main parts of the drawings *

20: peripheral processor 200: device controller

210: bus arbitration unit 212: address comparison unit

220: control unit 130: memory unit

240: address buffer section 250: data buffer section

A feature of the present invention for achieving the above object is a data buffer unit for storing data to be stored in a specific storage area on the memory unit; An address buffer section for storing an address for a storage area on the memory section; A control unit for storing the data received from the device in a storage area on the memory unit and simultaneously transmitting the data to the data buffer unit and transmitting an address for the storage area on the memory unit in which the data is stored to the address buffer unit; And an address comparison unit configured to determine whether the addresses received from the peripheral processor and the controller are the same and to store the same if the addresses are the same. To provide.

When the controller reads data stored in the memory unit, the controller stores an address for a storage area on the memory unit in which the data is stored and stores the data at the same time as the address buffer unit. The address comparison unit may be configured to transmit an alarm signal to a neighboring processor and an interrupt signal to the controller when the address accessed by the neighboring processor and the address accessed by the controller are the same.

The data buffer unit may store data transmitted from the peripheral processor and data transmitted from the controller in different areas.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram showing a configuration of a device controller matching with a peripheral processor according to the present invention.

The DC 200 according to the present invention includes a bus arbitration unit 210 including an address comparison unit 212, an address buffer unit 240, a data buffer unit 250, a control unit 220, and a memory unit. 130 is provided.

The address comparison unit 212 receives an address on the memory unit 130 to be accessed from the peripheral processor 20 and the control unit 220, and compares the received addresses to determine whether they are the same. In this case, the address is transmitted to and stored in the address buffer unit 240, an alarm signal is transmitted to the peripheral processor 20, and an interrupt signal is transmitted to the controller 220.

The address buffer unit 240 stores the address transmitted under the control of the address comparison unit 212.

In addition, the data buffer unit 250 is composed of two buffers, the bus arbitration unit 210 stores the data 1 received from the peripheral processor 20 and transmitted to the memory unit 130 in the first buffer and the control unit. Data 2 transmitted from the 220 to the memory unit 130 is stored in the second buffer.

Hereinafter, the operation relationship of the DC 200 according to the present invention described above.

When the peripheral processor 20 accesses the memory unit 130 to store data or to read the stored data, when the peripheral processor 20 transmits a command to the bus arbitration unit 210, the bus arbitration unit 210 sends a command. It is determined whether the received command is for writing data on the memory unit 130 or for reading data stored on the memory unit 130. Accordingly, the bus arbitration unit 210 transmits the address or data to the memory unit 130 and simultaneously transmits the address to the address comparison unit 212 and transmits the data to the data buffer unit 250.

Similarly, the control unit 220 also accesses the memory unit 130 to store data or read data stored therein, while simultaneously transmitting an address or data to the memory unit 130 and performing an address comparison unit ( The address is transmitted to 212, and the data is transmitted to the data buffer 250.

Thus, the address comparison unit 212 compares the address 1 transmitted from the peripheral processor 20 with the address 2 transmitted from the controller 220 to determine whether the address is the same. As a result of the determination, when the address 1 and the address 2 are identical to each other, an address conflict is generated by transmitting the alarm signal to the peripheral processor 20 and transmitting the interrupt signal to the control unit 220 at the same time. It tells you that this has happened.

For example, while the peripheral processor 20 accesses the memory unit 130 to read data stored in a specific area of the memory unit 130, the control unit 220 stores data 2 in the same area on the memory unit 130. When an address conflict occurs as a result of accessing the data, the controller 220 receives the interrupt signal transmitted from the address comparison unit 212 to recognize the address collision, and the peripheral processor 20 determines the address comparison unit 212. Receive the alarm signal transmitted by) to recognize the address conflict. Recognizing the address conflict, the controller 220 subsequently reads the address stored in the address buffer 240 and the data 2 stored in the buffer 2 in the data buffer 250, and then stores the corresponding data on the memory 130. The data is stored again in the address area.

Although the invention has been described in detail only with respect to the above-described embodiments, it will be apparent to those skilled in the art that modifications or variations can be made within the spirit and scope of the invention, and such modifications or changes fall within the claims of the invention. something to do.

As described above, in the present invention, when the peripheral processor and the control unit simultaneously access the same area on the memory unit, the data and address are separately stored in the buffer, the alarm signal is transmitted to the peripheral processor, and the interrupt signal is transmitted to the control unit. As a result, the peripheral processor and the control unit may write or read the correct data on the memory unit using the address and data stored in the buffer again, thereby preventing data loss due to an address conflict.

Claims (4)

A data buffer unit for storing the same data as the data stored in the specific storage area on the memory unit; An address buffer section for storing an address for a storage area on the memory section; A control unit for storing the data received from the device in a storage area on the memory unit and simultaneously transmitting the data to a data buffer unit and an address for the storage area on the memory unit in which the data is stored; And an address comparator configured to determine whether the address received from the peripheral processor and the control unit is the same and store the address if the address is the same. The method of claim 1, When the controller reads data stored in the memory unit, the controller stores an address for a storage area on the memory unit in which the data is stored, in the address buffer unit, and simultaneously stores the data in the data buffer unit. And a matching device between the peripheral processor and the device control device. The method of claim 1, And the address comparison unit transmits an alarm signal to the peripheral processor and an interrupt signal to the controller when the address accessed by the peripheral processor and the address accessed by the controller are the same. The method of claim 1, And the data buffer unit stores the data transmitted from the peripheral processor and the data transmitted from the controller in different areas.