KR19980061852A - Packet handler arbitration device of electronic switchboard - Google Patents

Abstract

The present invention provides the TDX-100 switchboard so that the link level control unit, the central processing unit, and the device control board may access the packet storage unit to arbitrate the flow of the data when the desired data is written or read. The present invention relates to a packet handler arbitration apparatus of an electronic switch, which is suitable for the following. In the prior art, when a plurality of functional blocks attempt to access packet memory at the same time, the memory arbitration unit grants memory access rights to the highest priority functional blocks by arbitration. Since only one of them enables the buffer to send an address so that data can be written to or read from the address, data processing takes a long time. However, in the present invention, a plurality of functional blocks bi-directionally data without a separate arbitration circuit. In So to be able to read and to help reduce the time of the writing / reading of data is to improve the above-mentioned drawbacks.

Description

Packet handler arbitration device of electronic switchboard

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for arbitrating a packet handler of an electronic switchboard, and more particularly, to a link level controller, a central processing unit, in a packet handler board in a TDX-100 electronic switchboard; CPU, 16-bit local bus device control board to access the packet memory to write or read the desired data to flow smoothly Relates to a packet handler arbitration device of an electronic switchboard suitable for arbitration.

In this regard, in the electronic switch according to the related art, a LAN chip is used to exchange packet data between packet handler boards without a higher control board, and a LAN chip and a packet link level controller (X.25 processing). Chip) and the central processing unit to access the packet memory.

In order to access the packet memory in the packet handler board as described above, an arbitration function was performed for the access order by using the bus request signal line between the central processing unit, the packet level controller, and the LAN chip.

In other words, the central processing unit requesting access rights to the packet memory centered on one packet memory, eight link level controllers, and the bus request signal lines for arbitration when the LAN chip attempts to simultaneously write or read data in the packet memory. There is a packet memory arbitration unit that arbitrates and generates an access grant signal, which is a signal for transferring memory access rights to one of them.

The above-mentioned packet memory arbitration unit gives priority to a specific function block when the bus use request is simultaneously requested by multiple function blocks, and gives a bus permission right. This is to give the function block bus permission.

At this time, the link level control has the highest priority among them, followed by the LAN chip and the central processing unit.

In this case, the bus block has a function block that enables the corresponding buffer to allow the address and data bus to operate normally so that data can be written to or read from the packet memory.

However, in such conventional techniques, when multiple functional blocks attempt to access packet memory at the same time, memory access rights are given to the highest priority functional block by arbitration of the memory arbitration unit so that only one of them enables the buffer. The problem is that data processing takes a long time because data can be written to or read from the corresponding address.

The present invention has been made to solve the above-mentioned drawbacks of the prior art, and a plurality of functional blocks can write and read data in both directions without a separate arbitration circuit, thereby reducing the time required to write / read data. It is an object of the present invention to provide a packet handler arbitration apparatus of an electronic exchange.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing an embodiment of a TDX-100 electronic switch for explaining a packet handler arbitration apparatus of an electronic switch according to the present invention.

FIG. 2 is a block diagram illustrating an embodiment of the packet handler board of FIG. 1 and illustrates an embodiment of a packet handler arbitration apparatus of an electronic switch according to the present invention. FIG.

* Description of the symbols for the main parts of the drawings *

10: Packet block 20: Device control board

30, 40: 1st, 16th packet handler board 60: Upper processor

60: time switch 110: central processing unit

120,140: first and second packet storage unit 130: link level control unit

150: local bus matching unit

The above and other objects and various advantages of the present invention will become more apparent from the preferred embodiments of the invention described below with reference to the accompanying drawings by those skilled in the art.

Hereinafter, an embodiment of the present invention for achieving the above object in detail.

Referring to FIG. 1, FIG. 1 is a block diagram illustrating an embodiment of a TDX-100 electronic switchboard for explaining a packet handler arbitration apparatus of an electronic switch according to the present invention. In the electronic switchboard including the 50 and the time switch 60, the above-described packet block 10 processes the packet data received through the above-described time switch 60 under the control of the device control board. Lower 16 packet handler boards to set up or tear down the packet link by transmitting to another packet handler board through the device control board or by transmitting control packets for a call connection request and a call disconnection request to the upper processor 50 described above. 30 and 40 and the lower 16 packet handler boards 30 and 40 described above are controlled through a 16-bit local bus through communication with the upper processor 50 to provide a packet handler board. The packet data processed by the above-described 16 packet handler boards 30 and 40 or by analyzing the control data processed from the 16 packet handler boards 30 and 40 described above. 50) a device control board 20 for processing requests and reporting.

The present invention thus made will be described in detail with reference to FIG. 2 as follows.

First, the 16 packet handler boards 30 and 40 in the packet block 10 process the packet data received through the time switch 60 under the control of the device control board 20 to process the device control board 20. The packet link is set up or disconnected by transmitting to another packet handler board or by transmitting control packets such as a call connection request and a call disconnection request to the higher processor 50.

Next, the device control board 20 controls the lower 16 packet handler boards 30 and 40 described above through a 16-bit local bus through communication with the upper processor 50 described above, and is processed by the packet handler board. The packet data is exchanged between the above-described 16 packet handler boards 30 and 40, or the control data processed from the above-described 16 packet handler boards 30 and 40 is analyzed and transmitted to the upper processor 50 described above. Processing requests and reports.

FIG. 2 is a block diagram illustrating an embodiment of the packet handler boards 30 and 40 of FIG. 1 and illustrates an embodiment of a packet handler arbitration apparatus of an electronic switch according to the present invention.

First, the packet handler boards 30 and 40 process control packets such as call requests and call truncation packets received from ISDN packet subscribers, and transmit them to the upper processor 50 through the device control board 20 or data of subscribers. A basic procedure of processing a packet and exchanging between the packet handler boards 30 and 40 is performed.

Accordingly, the link level control unit (X.25 processing chip) 130 in the packet handler boards 30 and 40 receives the control packet and the data packet sent by the subscriber at the time of packet call reception and receives the first packet storage unit for the X.25 processing chip. The central processing unit 110 processes the data stored in the first packet storage unit 120 by storing the data in the 120, and then exchanges data between the packet handler boards 30 and 40 or transmits the data to the upper processor 50. In order to write data into the second packet storage unit 140 for the device control board, the device control board 20 is read through the local bus matching unit 150.

In addition, when the device control board 20 receives a call connection response from the upper processor 50, the device control board 20 sends a control packet to the device control board through the 16-bit local bus and the local bus matching unit 150. Write to the second packet storage unit 140, the central processing unit 110 reads and processes it, and then writes the first packet storage unit 120 again, the packet link level control unit 130 is the first packet storage unit The data of 120 is read and transmitted to the ISDN subscriber through the time switch 60.

Here, the first packet storage unit 120 receives an address signal from the central processing unit 110 and the link level control unit 130 respectively to exchange data, and the first packet storage unit 140 is the central processing unit 110. And the local bus matching unit 150 receives an address signal, respectively, and transmits and receives data, and the first and second packet storage units 120 and 140 use dual port random access memory (DPRAM) to simultaneously write and read data in both directions. Use each.

As described above, the present invention enables a plurality of functional blocks to write and read data in both directions without a separate arbitration circuit, thereby reducing the time required to write / read data, thereby simplifying the overall structure and speeding up data processing. Has the effect of improving.

Claims (2)

A link level control unit connected to the ISDN subscriber through a preset time switch to receive a control packet and a data packet sent by the packet subscriber or to transmit a predetermined packet to the ISDN subscriber; A first packet storage unit storing data from the link level controller or applying pre-stored data to the link level controller according to an address designation of the link level controller; A local bus matching unit matching with a preset device control board through a preset local bus; A second storing the data from the device control board through the local bus matching unit or applying the pre-stored data to the device control board through the local bus matching unit according to the addressing of the device control board through the local bus matching unit; A packet storage unit; After assigning an address to the first and second packet storage units to receive data of the first packet storage unit and processing the corresponding data, the data is applied to the second packet storage unit or the data of the second packet storage unit. And a central processing unit for applying data to the first packet storage unit after the data processing is performed. The method of claim 1, And the first and second packet storage units are each composed of DPRAM to simultaneously write and read data in both directions.