KR100242708B1 - The integrated packet handling apparatus in a switching system and method thereof - Google Patents

Abstract

The present invention provides an apparatus and method for an integrated packet handler in an exchange configured to selectively transmit and receive packet data by selectively matching a modem, a DSU, or a time switch according to matching mode information defined in a higher processor. To this end, the apparatus according to the present invention comprises: a packet processing control unit 218 for controlling packet data to be transmitted and received in a matching mode set in the upper processor 120; A first matching unit 200 performing a modem matching function; A second matching unit 202 which performs a matching function with the indoor data line termination unit (DSU); A third matching unit 204 for performing a matching function with a time switch in the exchange; A link level processor 212 performing a link level connection function with each of the first to third matching units; A matching selector 210 controlled by the packet processing control unit to connect one of the first to second matching units and the link level processing unit; A fourth matching unit 222 performing matching processing with an upper processor; A common packet memory 214 for storing packet data transmitted in the packet handler apparatus; a communication memory 216 for storing control data or a program transmitted in the packet handler apparatus; The packet memory arbitration unit 220 arbitrates each common packet memory and the communication memory so that an access phenomenon does not occur at the same time. Therefore, the operator does not need to know the matching mode information set in the upper processor.

Description

Integrated packet handler device and method in exchange {THE INTEGRATED PACKET HANDLING APPARATUS IN A SWITCHING SYSTEM AND METHOD THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a packet handler that connects to a public data packet network and processes packet call processing events such as link level connection and data packet exchange when providing a packet service. In particular, a modem, Integrated matching circuits for indoor data line termination units (DSUs, hereinafter abbreviated as DSUs) and time switches, and matching to drive only specific matching circuits according to mode information provided from the upper processor. A packet handler apparatus and method are described.

Conventional packet handlers have a fixed matching configuration that can only match time switches or only modems or DSUs. Therefore, when a packet handler board different from the packet handler implementation information defined in the upper processor is mounted, packet data cannot be transmitted or received at all.

Therefore, conventionally, after accurately grasping the information on the packet handler board defined in the upper processor, there is a need to install a packet handler board having a corresponding matching configuration. For example, if the upper processor information about the packet handler to be mounted at the first position of the system is for time switch matching, the packet handler board for time switch matching must be mounted at the first position of the system and mounted at the second position. In case the upper processor information about the packet handler to be used is for DSU matching, the DSU matching packet handler board must be mounted in the second position of the system.

The present invention has been made to solve the above-mentioned hassle, and in the switch implemented to transmit and receive packet data by selectively matching to the modem, DSU or time switch according to the matching mode information defined in the upper processor Its purpose is to provide an integrated packet handler apparatus and method.

In order to achieve the above object, an apparatus according to the present invention is an integrated packet handler device provided in an exchange to provide a packet service by connecting to a public packet data network, and analyzes board information provided from an upper processor and provides the higher processor. A packet processing control unit for controlling packet data to be transmitted and received in a set matching mode; A first matching unit performing a modem matching function; A second matching unit performing a matching function with an indoor data line termination unit (DSU); A third matching unit performing a matching function with a time switch in the exchange; A link level processor for transmitting and receiving bit stream data to and from the first to third matching units, respectively, to perform a link level connection function and a link level processing; A matching selector controlled by the packet processing control unit to connect one of the first to second matching units to the link level processing unit; A fourth matching unit performing matching processing with an upper processor; A common packet memory for storing data transmitted from the link level processing section, data processed by the packet data processing section in the packet processing control section, and data transmitted from the fourth matching section, respectively; A communication memory for storing control data or a program transmitted and received between an upper processor and a packet processing controller; And a packet memory arbitration unit for arbitrating an access mode such that an access phenomenon is not simultaneously generated for each of the common packet memory and the communication memory.

In order to achieve the above object, the method according to the present invention is a method for operating a packet handler device mounted in an exchange to provide a packet service by connecting to a public packet data network. Initializing all devices in the device; Receiving matched mode information on a location where the packet handler device is mounted from an upper processor in the exchange for the packet handler device; Setting a matching mode for packet data transmitted and received between the public packet data network and the packet handler device according to the result of analyzing the received matching mode information; Requesting, by the upper processor, the transmission for the packet processing application software corresponding to the set matching mode, and receiving from the upper processor; And transmitting / receiving the data transmitted / received in the set matching mode by packet data processing by the packet processing application software.

1 is a functional block diagram of a packet service apparatus having a packet handler apparatus according to the present invention,

2 is a detailed block diagram of the packet handling control board shown in FIG. 1;

3 is an operation flowchart of a method of operating a packet handler apparatus according to the present invention.

<Description of the code | symbol about the principal part of drawing>

100: packet host processor connector

120: packet call control processor

110 to 113: 1st to Nth packet handling control board

200: modem matching unit

202: DSU matching unit

204: time switch matching unit

210: matching selector

212: link level processing unit

214: common packet memory

216: communication memory

218: packet processing control unit

220: packet memory arbitration unit

222: upper processor connector matching unit

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention.

First, FIG. 1 is a functional block diagram of a packet service apparatus having a packet handler apparatus according to the present invention, and includes a packet call control processor 120 for performing a packet call control function, a first for performing packet link connection and packet data processing. Packets between the N packet handling control boards 110 to 113, the first N packet handling control boards 110 to 113, and the packet call control processor 120 or the first N packet handling control boards 110 to 113. It consists of a packet higher processor connector 100 for matching processing for data transmission.

The packet call control processor 120 and the packet higher processor connector 100 are connected by a serial bus and are configured to be connected by a parallel bus between the packet higher processor connector 100 and the first to N packet handling control boards 110 to 113. do. Parallel buses include data buses, address buses, interrupt request signal transmission buses, alarm signal transmission buses indicating abnormal conditions for packet handling control boards, reset signal transmission buses for initializing packet handling control boards, control signal transmission buses, and addressing. A strobe signal transmission bus, a data strobe signal transmission bus, a LWORD signal transmission bus indicating long word transmission, a signal indicating a data transmission direction, and a bus for transmitting an acknowledgment signal DTACK.

FIG. 2 is a detailed block diagram of each of the first to Nth packet handling control boards 110 to 113 shown in FIG. 1, and includes a modem matching unit 200, a DSU matching unit 202, and a time switch matching unit 204. ), Matching selector 210, link level processing unit 212, common packet memory 214, communication memory 216, packet processing control unit 218, packet memory arbitration unit 220, and upper processor connector matching unit 222.

The modem matching unit 200 is controlled by the packet processing control unit 218 and is responsible for the physical modem matching function according to the V.28 recommendation for accessing the public packet data network. The DSU matching unit 202 is in charge of accessing the packet switched network and physical DSU matching function according to the V.35 recommendation, and the time switch matching unit 204 is matched with a time switch serving to connect a call between subscribers. In charge of.

The matching selector 210 selects one of the modem matching unit 200, the DSU matching unit 202, and the time switch matching unit 204. The link level processor 212 is connected to a matching circuit such as the modem matching unit 200, the DSU matching unit 202, and the time switch matching unit 204, and corresponds to a link level connection (Layer 2) for transmitting and receiving bit stream data. Function) and link level LAPB (Link Access Procedure Balanced) processing. LAPB adopts Bit-Oriented Synchronous Protocol, which is used to control and manage the data link layer between two points in the switching network.

The upper processor connector matching unit 222 performs matching processing to transmit and receive data with the packet upper processor connector 100 through the parallel bus. The communication memory 216 stores control data transmitted and received between the upper processor connector matching unit 222 and the packet processing control unit 218. The common packet memory 214 is used to store the packet data transferred to or from the other packet handling control board through the upper processor connector matching unit 222, and the packet at the packet processing control unit 218. Used to perform level processing. The packet processing control unit 218 performs a packet processing (process corresponding to Layer 3) on packet data transmitted and received.

The packet memory arbitration unit 220 arbitrates the link level processing unit 212, the higher processor connector matching unit 222, and the packet processing control unit 218 to share the common packet memory 214 without collision, and the packet processing control unit 218 and the upper processor connector matching unit 222 are responsible for arbitrating to share the communication memory 216 without conflict.

3 is an operation flowchart of a method of operating a packet handler apparatus according to the present invention.

1 to 3, the operation of the embodiment according to the present invention will be described.

First, when the packet handling control boards 110-113 are mounted in the system, each device in the board is initialized (step 300).

When each device in the board is initialized, one of the corresponding packet handling control boards 110 to 113 receives mode information of its printed board assembly (PBA) from the packet call control processor 120 (step 302). . The received mode information is recorded in the communication memory 216 through the upper processor connector matching unit 222 of FIG. 2, and the packet processing control unit 218 reads and analyzes the mode information recorded in the communication memory 216 (step). 304). At this time, the packet memory arbitration unit 220 performs an arbitration process so that the recording mode and the read mode for the communication memory 216 do not collide. For example, the packet memory arbitration unit 220 may enable an unshown buffer existing between the upper processor connector matching unit 222 and the communication memory 216 and may be configured between the communication memory 216 and the packet processing control unit 218. Existing buffers that are present may be mediated in a manner that disables them.

The packet processing controller 218 controls the operation of the matching selector 210 according to a result of analyzing the mode information of the magnetic board read from the communication memory 216. That is, if the read mode information of the magnetic board is for modem matching, the modem matching unit 200 and the link level processing unit 212 are controlled to be connected, and if the read mode information of the magnetic board is for DSU matching, the DSU matching unit 202 and the link level processing unit 212 are controlled to be connected, and when the read mode information of the magnetic board is for time switch matching, the time switch matching unit 204 and the link level processing unit 212 are controlled to be connected.

The packet processing control unit 218 then records the packet processing application software request signal to be used by the board in the communication memory 216, and the upper processor connector matching unit 222 records the application software recorded in the communication memory 216. The request signal is read and sent to the packet call control processor 120 through the packet higher processor connector 100 (step 308). Accordingly, when the corresponding application software is sent from the packet call control processor 120, the packet is transmitted to the corresponding packet handling control board through the packet upper processor connector 100. At this time, an example of application software to be transmitted may be X.25 processing software for subscriber access or software for ISDN trunk line connection in case of time switch matching, and directly with public packet data network in case of modem or DSU. X.75 processing application software for connecting. Such application software is loaded and used by the packet processing control unit 218 in the process of transmitting and receiving packet data.

As described above, if an interrupt indicating that a board alert is generated from the packet call control processor 120, which is an upper processor, is transmitted and received, the packet processing control unit 218 returns to step 302 to communicate memory 216. Receive processing of the mode information of the board again sent from the packet call control processor 120, which is the upper processor through the), and controls the operation of the matching selector 210 according to the analysis result. At this time, it may be controlled so that a matching mode different from that previously set in the matching selecting unit 210 is set. For example, when the matching mode previously set in the matching selection unit 210 is for the DSU, the DSU matching unit 202 and the link level processing unit 212 are connected. However, when the received mode information is analyzed, it is for the time switch. The match selector 210 is driven to connect the time switch matcher 204 and the link level processor 212.

As described above, the present invention implements a packet handling control board mounted in a system so that an upper processor can adaptively perform a matching process for a desired use, so that the upper processor for the corresponding slot when the packet handling control board is mounted. Not only solve the trouble of the operator to grasp the matching mode information, but also the matching mode for the packet handling control board is automatically set, there is an advantage that it is easy to change the set matching mode.

Claims (2)

An integrated packet handler device provided in an exchange for providing a packet service by connecting to a public packet data network, A packet processing controller configured to analyze the board information provided from the upper processor and to transmit and receive packet data in a matching mode set in the upper processor; A first matching unit performing a modem matching function; A second matching unit performing a matching function with an indoor data line termination unit (DSU); A third matching unit performing a matching function with a time switch in the exchange; A link level processor for transmitting and receiving bit stream data to and from the first to third matching units, respectively, to perform a link level connection function and a link level processing; A matching selector controlled by the packet processing control unit to connect one of the first to second matching units to the link level processor; A fourth matching unit performing a matching process with the upper processor; A common packet memory for storing data transmitted from said link level processor, data processed by packet data by said packet processing controller, and data transmitted from said fourth matching unit; A communication memory for storing control data or a program transmitted and received between the upper processor and the packet processing controller; And a packet memory arbiter for arbitrating an access mode such that an access phenomenon is not simultaneously generated for each of the common packet memory and the communication memory. A method of operating a packet handler device mounted in an exchange to provide a packet service by connecting to a public packet data network, Initializing all devices in the packet handler device when the packet handler device is mounted; Receiving matched mode information on a location where the packet handler device is mounted from an upper processor in the switch for the packet handler device; Setting a matching mode for packet data transmitted and received between the public packet data network and the packet handler device according to a result of analyzing the received matching mode information; Requesting, by the upper processor, the transmission for the packet processing application software corresponding to the set matching mode, and receiving from the upper processor; And transmitting and receiving the data transmitted and received in the set matching mode by processing the packet data by the packet processing application software.

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