KR100255421B1 - Method and appatatus for integrating terminal using for disposing data in an electronic switching system - Google Patents

Abstract

PURPOSE: An integrated terminal for data processing in a full electronic telephone exchange and a method thereby are provided to process a packet processing block and a No.7 processing block at the same time. CONSTITUTION: A time switch interface unit(208) covers interfacing with a time switch. A link level processing unit(210) discriminates whether a processor is a packet board or a signal terminal board and processes a corresponding protocol. An interface selection unit(212) receives information from the link level processing unit(210), determines whether a signal is a No.7 signal or packet data and sets up a corresponding interface circuit. An upper-level device control board interface unit(222) carries out interfacing so that data can be transmitted and received between a device control board and terminal boards. A communication memory(216) stores selection signals to indicate the receiving status of packet data and a No.7 message signal. A data memory(214) stores the packet data and the No.7 message signal. A memory arbitration unit(220) executes a memory arbitration function to prevent collision between blocks sharing a memory.

Description

Integrated terminal device and method for data processing in electronic switchboard {METHOD AND APPATATUS FOR INTEGRATING TERMINAL USING FOR DISPOSING DATA IN AN ELECTRONIC SWITCHING SYSTEM}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated terminal for signaling packet data and a NO.7 message, and more particularly, to a signal terminal for performing packet call processing by connecting to a public data packet network in an electronic switchboard or processing a signaling message by connecting to a signaling network. It's about blocks.

In the prior art, since the packet processing block and the NO.7 signal message processing block exist separately, the signal processing block must be classified into two blocks as well as the signals must be classified and processed. When the data signal is received, there is a drawback that the terminal board processes the NO.7 message signal and the packet data signal.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned drawbacks of the prior art, and an object thereof is to provide an integrated terminal apparatus and method for data processing in an all-electronic switching center capable of simultaneously processing a packet processing block and a NO.7 processing block.

In order to achieve this object, the present invention provides an apparatus comprising: a time switch for providing a path of data in a time division manner; A terminal block for processing the received packet data or the NO.7 signal message using the data path provision of the time switch; A message switch providing a data path between the terminal block and the terminal block of another subsystem; Receiving the information from the terminal block and including an upper processor for controlling the data path providing function of the time switch and the message path providing function through the terminal block, the terminal block, each packet data or NO received through the time switch; .7 a plurality of terminal boards each processing a signaling message; A device control board communicates with an upper processor to control driving of the plurality of terminal boards and connects the terminal boards and a message switch.

The present invention also provides a terminal block suitable for packet processing and NO.7 processing, an upper processor for controlling the terminal block, a time switch for driving and switching a corresponding program when a signal message or packet data is received in the terminal block, and a subscriber. And a message switch for spatial division switching when transmitting / receiving data to a network, wherein the above-described terminal block comprises a device control board for controlling the terminal block and a plurality of terminal boards for signal processing. A first determination step of determining a type of a corresponding terminal board by searching a register; Running a packet processing application program to process packet data; Determining whether the packet data processing is completed or not, if the packet data processing is terminated, ending the processing procedure for the corresponding link, and if not, repeatedly executing the packet data processing; Processing the NO.7 message signal by driving the NO.7 processing application program when the NO.7 signal processing board is determined in the first determination step; If it is determined that NO.7 message signal processing is finished, and the NO.7 message signal processing is finished, terminate the NO.7 message signal processing program, and if not, repeat the NO.7 message signal processing repeatedly. Performing the steps.

1 is a block diagram illustrating an integrated terminal block of an electronic switchboard suitable for packet data processing and NO.7 signal processing according to the present invention;

2 is a detailed block diagram of a terminal block according to FIG. 1;

3 is a flow chart illustrating a method of processing packet data and NO.7 messages in an electronic switchgear according to the present invention.

<Description of the code | symbol about the principal part of drawing>

110: terminal block 120: device control board

130 and 140: first and N-th terminal board 142: message switch

150: upper processor 160: time switch

208: time switch matching unit 210: link level processing unit

212: matching selector 214: data memory

216: communication memory 218: processing control unit

220: memory arbitration unit

222: host device control board matching unit

1 is a block diagram illustrating an integrated terminal block of an electronic switch according to the present invention, which is suitable for processing packet data and NO.7 message signals of an electronic switch, and includes a terminal block 110 suitable for packet processing and NO.7 processing. ), The upper processor 150 for controlling the terminal block 110, the time switch 160 for driving and switching a corresponding program when a signal message or packet data is received by the terminal block 110, and a subscriber. In the case of transmitting / receiving data, the message switch 142 is configured to switch space division. The terminal block 110 described above includes the device control board 120 and the plurality of terminal boards 130,..., 140. )

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention.

Referring to FIG. 1, the device control board 120 controls devices belonging to the terminal block 110 through communication with the upper processor 150 in the terminal block 110.

The terminal boards 130,..., 140 are devices in the terminal block 110, and packet data or NO received through a passage connected through the time switch 160 described above by the control of the device control board 120. .7 process the message signal;

The terminal boards 130,..., 140 transmit data or messages to the terminal boards of other sub-systems (not shown) via the message switch 142 through the device control board 120 or the above-described upper processor ( Set up or tear down the packet link by sending a control message for the call connection request and the call disconnection request to 150).

In the case of data transmitted and received to other sub-systems, it is directly transmitted / received through a message switch, and processed and analyzed by analyzing the control data processed from the plurality of terminal boards 130, ..., 140 described above. The information is reported to the upper processor 150 described above.

And, if the terminal board (130, ..., 140) is a signal processing in the same subsystem, the device control board 120 is a plurality of the terminal board 130, described above through communication with the upper processor 150. .., 140 and exchange the packet data processed by the plurality of terminal boards 130, ..., 140 and the NO.7 signal message between the terminal boards 130, ..., 140 described above. .

The upper processor 150 controls the device control board 120 in the terminal block 110 to connect to the time switch 160 from each terminal board 130,..., 140, and the device control board 120. Controls the connection to the message switch 142 via.

When the signal message or the packet data is received by the terminal block 110, the time switch 160 drives the packet processing program or the NO.7 message signal processing program to switch to the corresponding area.

When the message switch 142 transmits / receives a message signal to a subscriber of another station, the message switch 142 performs space division switching to connect a call to a time division switch of another station.

2 is a block diagram of the terminal board 130, ..., 140, the time switch matching unit 208 is responsible for matching with the time switch 160, which serves to connect the message signal or data between subscribers. .

The link level processing unit 210 exists in a board for processing packet data and NO.7 message signals in the terminal board, and sets a register for distinguishing the specific terminal boards 130,..., 140. Whether (130, ..., 140) is the terminal board (103, ..., 140) to process the packet data signal or the terminal board (130, ..., 140) to process the NO.7 board. Can be distinguished.

As an example, when an address is used for packet signal processing, an address is set to "1", and in the case of a NO.7 signal message, an address is set to "0" to match an NO.7 message signal or a packet data signal.

The ROM (Read Only Memory) in the link level processing unit 210 is a packet link processing unit program so as to select and run one of two types of basic processor peripheral device initialization programs and packet processing programs and NO.7 processing programs as needed. NO.7 Signal A message processing unit program is built in. The received data and message signals are stored in the data memory.

The matching selector 212 refers to the address read by the link level processing unit, and when the corresponding data and message are the NO.7 message signal, recognizes it as a NO.7 terminal board, sets the NO.7 terminal board, If it is set to a packet terminal board.

The processing control unit 218 drives the corresponding matching circuit in the time switch matching unit 208 or the upper device control board 222 with the packet data or the NO.7 signal according to the program of the terminal set in the matching selecting unit 212. NO.7 Controls the matching circuit or the connection of packet data signals.

The upper device control board matching unit 222 performs a matching process to transmit and receive data between the device control board 120 and the terminal boards 130,..., 140 through a parallel bus.

The communication memory 216 stores a selection signal indicating whether the packet data and the NO.7 message signal are received and is smoothly received and transmitted under the control of the memory arbitration unit 220.

The data memory 214 stores the packet data or the NO.7 message signal, or the other terminal boards 130,..., 140, and the packet handling control board (not shown) in the upper device control board matching unit 222. Or send a message or data to another station.

It also receives data from other packet handling control boards or other stations and stores packet data or NO.7 message signals.

The data memory 214 temporarily stores the packet data and the NO.7 message signal for packet processing and the NO.7 message signal processing.

As described above, the memory arbitration unit 220 configured as the arbitration logic may match four different blocks, namely, the matching selection unit 212, the link level processing unit 210, the processing control unit 218, and the upper device control board. When the units 222 perform repetitive operations of storing and reading packet data using the communication memory 216 and the data memory 214, the units 222 arbitrate the memory to prevent mutual collisions between the shared blocks. Play a role.

Referring to FIG. 3, a method of processing packet data and NO.7 message signals in an electronic switchgear is performed. When power is turned on, each block around the processing control unit 218 is initialized (step 302). Initialization of blocks on board is the process of setting variables for each block to operate.

In this way, when the neighboring blocks of the processing control unit 218 are initialized, the processing control unit 218 registers the corresponding register to determine whether the current terminal boards 130, ..., 140 are NO.7 terminal boards or packet processing terminal boards. The search determines the type of the terminal board (step 304).

For example, a register for determining the type of the terminal boards 130, ..., 140 sets the register bit to "0" when the packet link processor is mounted, and sets the register bit to "1" when the NO.7 signal processor is mounted. Set to ".

The processing control unit 218 determines what kind of terminal boards 130, ..., 140 are matched in this way, and if it is determined that the packet processing signal is the case, drives the packet processing device initialization program embedded in the ROM ( Step 306).

In the case of the packet board, the link processing unit device initialization program initializes the link processing device to process the packet layer 2, and runs the packet layer 3 processing application program to perform packet data processing of layer 2 and layer 3 of the packet protocol.

Thereafter, the packet processing application is driven (step 308) to process the packet data (step 310). In step 312, it is determined whether the processing of the packet data has ended (step 312), and as a result of the determination of step 312, the packet data processing program is terminated if the packet data processing has ended; Run it repeatedly.

On the other hand, if it is determined in step 304 that the NO.7 signal processing board is used, the NO.7 processing device initialization program is driven (step 314). In the case of the NO.7 board, the link processing unit device initialization program initializes the link device to process the NO.7 signal message.

Thereafter, the NO.7 processing application program is driven (step 316) to process the NO.7 message signal (step 318). In step 318, the NO.7 message signal is processed, and it is determined whether the NO.7 message signal processing is terminated (step 320), and when the NO.7 message signal processing is terminated, the NO.7 message signal processing program is executed. If it is not completed, if it is not terminated, NO.7 message signal processing is repeatedly executed.

As described above, the present invention uses the NO.7 message processing block and the packet data processing block as a common circuit, and modulates different layer 2 processing parts due to protocol processing characteristics to process signal messages during NO.7 processing, and to process packet data. In this case, the packet processing block and the NO.7 processing block existed separately so that a separate protocol was processed.

The principles of the invention have been described above in connection with specific devices, which are described by way of example only, and are not limited to the spirit of the invention as described in the appended claims.

Claims (5)

A time switch 160 for providing a path of data in a time division manner; A terminal block (110) for processing the received packet data or the NO.7 signal message using the data path provision of the time switch (160); A message switch 142 for providing a data path between the terminal block 110 and the terminal block of another subsystem; The upper processor 150 that receives the information from the terminal block 110 and controls the data path providing function of the time switch 160 and the data path providing function of the message switch 142 through the terminal block 110. Including; The terminal block 110 includes: a plurality of terminal boards 130 and 140 for processing each packet data or NO.7 signal message received through the time switch 160; The device control board 120 communicates with the upper processor 150 to control driving of the plurality of terminal boards 130 and 140, and connects the terminal boards 130 and 140 to the message switch 142. Integrated terminal device for data processing in the electronic switch having a. The method of claim 1, Each of the terminal boards 130, ..., 140 is: A time switch matching unit 208 in charge of matching with the time switch 160; A link level processor (210) for processing a corresponding protocol by distinguishing whether a processor is a packet board or a signal terminal board in the terminal boards (130, ..., 140); A matching selector 212 configured to receive information from the link level processor 210, determine whether a corresponding signal is a NO.7 signal or packet data, and set a corresponding matching circuit; An upper device control board matching unit 222 matching to transmit and receive data between the device control board 120 and the terminal boards 130,..., 140; A communication memory 216 for storing a selection signal indicating whether packet data or a NO.7 message signal is received; A data memory 214 for storing packet data or a NO.7 message signal; A memory arbitration unit 220 that performs a memory arbitration role to prevent mutual collision between blocks sharing a memory; According to the program of the terminal set in the matching selector 212, the corresponding data matching circuit is driven by the time switch matching unit 208 or the upper device control board 222 by using the packet data or the NO.7 signal. An integrated terminal device for data processing in an electronic switchgear, characterized by comprising a processing control unit (218) for controlling the connection of packet data signals. The method of claim 2, The blocks sharing the memory are the link level processing unit (210), the processing control unit (218), and the upper device control board matching unit (222). The method of claim 2, Distinguishing whether the processor is a packet board or a signal terminal board in the terminal board (130, ..., 140) is characterized by setting a register to distinguish the integrated terminal device for data processing in the electronic switchboard. A terminal block 110 suitable for packet processing and NO.7 processing, a higher processor 150 controlling the terminal block 110, and a corresponding program message are received when the terminal block 110 receives a signal message or packet data. And a time switch 160 for switching, and a message switch 142 for space division switching in case of transmitting / receiving data to a subscriber. The above-described terminal block 110 is a device for controlling a terminal block. In the all-electronic exchanger which consists of the control board 120 and the several terminal boards 130, ..., 140 which perform signal processing, A first determination step of determining a type of a corresponding terminal board 130 by searching for a register; Running a packet processing application program to process packet data; Determining whether the packet data processing is completed or not, if the packet data processing is terminated, ending the processing procedure for the corresponding link, and if not, repeatedly executing the packet data processing; Processing the NO.7 message signal by driving the NO.7 processing application program when the NO.7 signal processing board is determined in the first determination step; If it is determined that NO.7 message signal processing is finished, and the NO.7 message signal processing is finished, terminate the NO.7 message signal processing program, and if not, repeat the NO.7 message signal processing repeatedly. Integrated terminal method for data processing in the electronic switch, characterized in that it comprises the step of executing.

Images