KR20030009812A - Apparatus and method for controlling DPRAM - Google Patents

Abstract

PURPOSE: A device for controlling a DPRAM(Dual Port Random Access Memory) and a method thereof are provided to detect and prevent an error which may be generated when the same addresses are accessed by two processors in accessing a DPRAM. CONSTITUTION: A DPRAM(60) is connected to a plurality of processors(30,40), transmits/receives data and an address, receives a control signal from a control unit(50), and receives a control of an access operation. The control unit(50) transmits/receives an address signal and a control signal from the processors(30,40). When the processors(30,40) access the external DPRAM(60), if the processors(30,40) access the same address, respectively, the control unit(50) detects the same accessing operations and controls an access of the DPRAM(60) for making the processors(30,40) additionally perform reading/writing operations with respect to the DPRAM(60). The processors(30,40) transmit/receive an address control signal to the control unit(50) and transmit/receive data/address to the DPRAM(60) located in the exterior of the control unit(50).

Description

Apparatus and method for controlling DPRAM of common input / output RAM

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a control apparatus of a common input / output RAM (DPRAM) and a method thereof, and more particularly, to detect and prevent errors that may occur when two processors access the same address when the DPRAM is accessed. The present invention relates to a control device for a common input / output RAM and a method thereof.

In general, a common input / output RAM (DPRAM) is a RAM having a structure in which one RAM can be accessed from two systems. Therefore, it is roughly classified into two systems having parallel input / output and one system having parallel input / output and serial input / output. The latter is used as an image memory device.

And when accessing the same address from two processors when accessing DPRAM, bad data can be read or written.

This situation does not occur frequently, but if it does, then each processor will not know, and in some cases a fatal error may occur.

Conventionally, in the case of using DPRAM, there have been cases in which a processor is directly connected to a commercial DPRAM and a DPRAM is implemented in a field programmable gate array (FPGA).

1 is a block diagram of a conventional common input / output RAM, showing a block configuration of a DPRAM that can be directly connected to a processor.

This is the IDT7130S / L model from IDT Inc., where reference numeral 11 is an arbitration and interrupt logic, 12 is a memory array, and 13 and 14 are first and second address decoders. 15 and 16 are first and second I / O control units.

Also here are the pins:

OE #, CE #, R / W #, I / O (7: 0), BUSY #, A (9: 0), INT #

Thus, there are first and second controllers 15 and 16, which are logic to monitor the addresses and CE # of both ports. If both CE # s are active and have the same address, the BUSY # signal is activated at this time. At this time, the write address is prohibited. In other words, neither side can write to the address until either side clears this situation, and only read access is possible.

The IDT7130S / L model of IDT is a representative DPRAM. In this case, the first and second controllers 15 and 16, which are independent verification circuits, inform the user that the address and the matching have occurred through the busy # pin. Have This can prevent errors from happening, but it simply prevents this by slowing down either access.

In this case, stable operation of the DPRAM is guaranteed.

However, such a conventional DPRAM has a problem that a time delay is inevitably generated since address matching simply prevents it by delaying one of the accesses.

In the case of using the BUSY pin, when two processors access simultaneously, the other fast processor delays the access until the access from the slower processor is completed. There was a problem that must always be guaranteed when accessing DPRAM.

In this case, it is not a problem between low speed processors, but as the speed of the processor increases, a problem occurs. If the speed difference between the two processors using the DPRAM becomes large, the loss of processor resources caused here increases greatly. There is a problem.

Meanwhile, FIG. 2 is a diagram of a common input / output RAM implemented in a conventional FPGA, and illustrates a case in which DPRAM is implemented in an FPGA.

Here, reference numeral 21 denotes BlockRam, which is a DPRAM implemented in the FPGA, and shows an example of the internal block RAM of Xilinx FPGA Spartan2.

There are the following pins.

ADDR (m: 0), DI (n: 0), WE, EN, RST, CLK, DO (n: 0)

In this case too, there is a pair of DPRAM.

When using this block RAM as a DPRAM, only signals such as address / data and chip select signals (CS) exist without any other control logic.

However, the block RAM implemented in the conventional FPGA has a disadvantage in that there is no logic for a correction circuit capable of correcting an error that occurs when a processor reads the same address when performing an access. That is, there is a problem in that it provides only a function of a simple DPRAM and does not have any circuit which can solve the error occurrence itself by address matching.

Accordingly, the present invention has been proposed to solve the conventional problems as described above, and an object of the present invention is to detect and prevent an error that may occur when two processors access the same address when the DPRAM is accessed. The present invention provides a control device for a common input / output RAM and a method thereof.

In order to achieve the above object, a control device of a common input / output RAM according to an embodiment of the present invention,

A DPRAM connected to a plurality of processors to transmit / receive data and addresses, and receive a control signal from a controller to control an access operation; Sending / receiving an address signal and a control signal from the plurality of processors, detecting when the plurality of processors access the same address when accessing the external DPRAM so that the plurality of processors read / write the DPRAM. A control unit controlling access of the DPRAM to separately perform the operation; The technical configuration is characterized by including a plurality of processors for transmitting and receiving the control unit and the address / control signal, and the transmission / reception of the DPRAM and data / address outside the control unit.

In order to achieve the above object, a control method of a common input / output RAM according to an embodiment of the present invention,

A first step of determining whether a situation that meets a preset condition occurs so as to determine whether an access collision occurs when accessing the DPRAM in a plurality of processors; The technical configuration may include performing a second step of causing one processor to perform a write operation and another processor to perform a read operation when a situation that meets the preset condition occurs.

1 is a block diagram of a conventional common input / output RAM;

2 is a diagram of a common input / output RAM implemented in a conventional FPGA.

3 is a block diagram of a control device of a common input / output RAM in the case of using the common input / output RAM externally according to an embodiment of the present invention;

4 is a block diagram of a control device of a common input / output RAM in the case of using the common input / output RAM in accordance with an embodiment of the present invention.

5 is a detailed block diagram of adding a controller in FIG.

6 is a block diagram illustrating a method of controlling a common input / output RAM in a mode according to an embodiment of the present invention.

7 is a block diagram illustrating a method of controlling a common input / output RAM by a storage table according to an embodiment of the present invention.

FIG. 8 is a table showing an example of the configuration of a table used in FIG. 7.

Explanation of symbols on the main parts of the drawings

30: first processor 40: second processor

50: control unit 60: DPRAM

70: controller

Hereinafter, an embodiment according to the present invention configured as described above, a control apparatus of a common input / output RAM, and a method thereof will be described in detail with reference to the accompanying drawings.

FIG. 3 is a block diagram of a control device of a common input / output ram when the common input / output ram is externally used according to an embodiment of the present invention.

As shown therein, a DPRAM 60 is connected to the plurality of processors 30 and 40 to transmit / receive data and addresses, and receives a control signal from the controller 50 to control an access operation; Sending / receiving an address signal and a control signal from the plurality of processors 30 and 40, and accessing the same address when the plurality of processors 30 and 40 access the external DPRAM 60. A control unit (50) for detecting and controlling access of the DPRAM (60) so that the plurality of processors (30) (40) separately perform read / write operations to the DPRAM (60); And a plurality of processors 30 and 40 which transmit / receive an address / control signal with the controller 50 and transmit / receive data / address with the DPRAM 60 outside of the controller 50. It is configured by.

4 is a block diagram of a control device of a common input / output RAM in the case of using the common input / output RAM in accordance with an embodiment of the present invention.

As shown in the drawing, a plurality of processors 30 and 40 are connected to transmit / receive data and addresses, receive a control signal from the controller 50, and include a DPRAM 60 to control an access operation therein. And transmit / receive an address signal and a control signal from the plurality of processors 30 and 40, and access the same address when the plurality of processors 30 and 40 access the DPRAM 60 therein. A controller (50) which detects this and controls access of the DPRAM (60) so that the plurality of processors (30) (40) separately perform read / write operations on the DPRAM (60); And a plurality of processors 30 and 40 which transmit / receive an address / control signal with the controller 50 and transmit / receive data / address with the DPRAM 60 inside the controller 50. It is configured by.

FIG. 5 is a detailed block diagram to which a controller is added in FIG. 4.

Here, reference numeral 70 denotes a controller that performs access control on the DPRAM 60 in the controller 50 which is an FPGA when the controller 50 is configured as an FPGA.

6 is a block diagram illustrating a method of controlling a common input / output RAM in a mode according to an embodiment of the present invention.

As shown in FIG. 1, when the DPRAM 60 is accessed by the plurality of processors 30 and 40, a first condition for determining whether a condition that meets a preset condition occurs so as to determine whether an access collision occurs. Step ST11; If a condition that meets the preset condition occurs, one processor includes a second step (ST12 to ST16) to perform a write operation and the other processor to perform a read operation.

In the first step, it is determined whether the plurality of address signals generated when the plurality of processors 30 and 40 access the DPRAM 60 match.

In the first step, it is determined whether each of the plurality of chip select signals (Chip Select, CS) generated when the plurality of processors 30 and 40 access the DPRAM 60 is active.

In the first step, the plurality of address signals generated when the plurality of processors 30 and 40 access the DPRAM 60 are matched, and each of the plurality of chip select signals CS is active. Judge the awareness together.

FIG. 7 is a block diagram illustrating a method of controlling a common input / output RAM using a storage table according to an embodiment of the present invention, and FIG. 8 is a table illustrating an example of a table used in FIG. 7.

As shown therein, a step (ST21) of determining whether an error occurs when the DPRAM 60 is accessed by the plurality of processors 30 and 40; If the error has not occurred, allowing a normal DPRAM (60) access operation to be performed (ST22 to ST24); If the error has occurred, the address and data to be read / write to the DPRAM 60 in one processor are stored in a storage table that can temporarily store the address and data, and the DPRAM 60 of the one processor is accessed. After the process, the other processor performs the step of performing the access to the DPRAM 60 (ST25 to ST33).

Referring to the accompanying drawings, the operation of the control device and method of the common input / output RAM according to the present invention configured as described above will be described in detail as follows.

First, the present invention seeks to prevent an error that may occur when two processors access the same address when the DPRAM is accessed. A circuit for preventing this may be implemented in a programmable gate array (PGA).

To this end, it can be implemented in two devices.

That is, one is when the DPRAM 60 exists outside the control unit 50 that can be implemented in PGA (see FIG. 3), and the other is inside of the control unit 50 that the DPRAM 60 can implement in PGA. If present in (see Figure 4).

5 is a detailed block diagram to which a controller is added in FIG. 4.

Here, the first processor 30 and the second processor 40 are boards that are responsible for each part of the system. If there is a need for communication between the two, serial communication may be used a lot but communication using DPRAM may be required. Conventionally, a DPRAM configured separately is implemented, but a DPRAM 60 block is implemented inside the controller 50 that is an FPGA.

When two boards communicate with each other, the controller 70, which is a simple control circuit, can be used inside the FPGA to achieve a more efficient and safe circuit implementation.

For example, when two MPC860s, the first and second processors 30 and 40, communicate with each other, the DPRAM 60 may be restricted from being accessed inside the FPGA when the DPRAM 60 using the FPGA is used in the middle. This is the case when the controller 70 is used.

In this case, the address, data and control signals are often connected to the FPGA, so no additional pin setting is necessary. Then, the control signal and the address of both sides are analyzed and the new control signal is generated and input to the DPRAM 60 to control access to the DPRAM 60.

In addition, the present invention can be implemented in two ways.

1) When each processor receives a TA (Transfer Acknowledgement) signal from DPRAM 60, then proceeds to the next.

2) each processor proceeds to the next performance after one clock period without TA signal from DPRAM 60.

In the case of 1) above, since the operation of the processor can be controlled by the TA signal, it can be more simply implemented using this (see FIG. 6).

Therefore, when the address signal from each processor is the same, the CS signal is active, and the read address is read on one side and the write address on the other, the CS signal of the DPRAM 60 is controlled. ) To allow real access sequentially.

At this time, there may be two situations in which the access clocks of the two processors 30 and 40 are the same and one of which is fast, and stable operation may be exhibited in both cases.

In addition, FIG. 6 illustrates a case in which one of a read and a write operation is first selected using the I_mode pin. If the clock speed difference between the two processors 30 and 40 is large, the execution of the processor having the fast clock first may benefit in terms of latency. In this case, instead of selecting read / write as I_mode, the fast clock port is always set to 1 or 2, and then connected, and when a collision condition occurs, a fast port can be performed unconditionally.

In this case, the agreement of the collision conditions can be assumed as follows.

A) Address 1 = Address 2

B) CS1 # = CS2 # = Active

C) In both cases, when it is not read operation

Then compare the collision conditions to see if the access by the two processors is in conflict. If it crashes, it is active. That is, if Address 1 and Address 2 are the same, and the same address is accessed simultaneously, when two CS1 and CS2 are turned on and RHWL1 and RHWL2 are different, that is, one is read and one is write, two processors collide. to be.

Here, cnt1 and cnt2 are signals for controlling the CS signal, which is a chip select signal of each DPRAM. This was made to wait for the processor to access another DPRAM 60. Therefore, the processor that accesses first in case of collision is determined according to the mode value. At this time, the CS signal of the accessing processor becomes active as the cnt value becomes active, thereby allowing access.

If the MODE value is 1, the read operation is given priority. At this time, the value of cnt1 is set to 0 to activate the value of CS1, which indicates that an access operation to the DPRAM 60 is currently in progress.

When one clock advances after the DPRAM 60 is accessed, cnt1 is set to a value of 1 to finish accessing the DPRAM 60 from one processor. When the access to the next clock is maintained, the access operation to the DPRAM 60 in one processor is completely completed.

This operation occurs when one processor first accesses the DPRAM 60. If the situation in which one processor is to be waited by the selection of the MODE value, the conflict condition set in advance will not be satisfied. If another processor is waiting for access and another processor is accessing it, cnt1 is given a value of 0 to make it active and start access. After that, it returns to the initial state after performing the access.

The MODE is where the constructor decides which action to prioritize. When MODE is set to 1, if RHWL1 is a read operation with a value of 1, one processor executes the operation first. If the value of RHWL1 is 0, one processor waits because it is a write operation. In other words, if the value of MODE is 1, it is read first, and if it is 0, it is write first.

On the other hand, in the case where each processor of 2) proceeds to the next performance after one clock period without the TA signal from the DPRAM 60, it is important to continuously transmit the next data regardless of whether the processor has received the TA signal (Fig. 7).

In this case, it can't be handled by an implementation like 1). In this case, a table of addresses and data can be implemented to process the data. In other words, when both Read and Write enter the same address, it decides which of Read and Write should be processed first. This is what the user must decide first.

If you read first and then write, you save the address and data to be written to the storage table that temporarily stores the address-data, and wait for the read access to complete. In this case, if the control unit 50 continuously accesses the DPRAM 60, all of the continuous operations must be stored in the storage table.

After the controller 50 detects that the read access of the duplicate address is completed with the stored table, the controller 50 immediately enters an operation of processing the table.

The same principle can be used to determine writing as a preprocessing operation.

FIG. 8 is a table showing an example of the configuration of a table used in FIG. 7.

The first line here is for example. The data as shown in FIG. 8 may be tabulated by holding fixed bits in the memory. For example, if a total of 23 bits is required, the 32-bit memory is captured and used as a temporary storage space, and then the values are re-stored in the DPRAM 60 when the processor is not accessed, and then used. do.

Therefore, the advantage of the method as in the case of 2) is that the read and write operations are completed in one clock, and thus the time required for the processor to perform the read and write operations is shortened. On the other hand, in case of 2), the data and address must be stored using a table, thus occupying resources, and the algorithm for implementing this is complicated compared to the case of 1). That is, in the case of 2), fast operation can be guaranteed using resources.

Also, in case of 1), if there is an address conflict when trying to read / write, wait unconditionally and decide whether to give priority to Read or Write according to a predetermined mode. Therefore, compared to the case 2), the waiting time is longer but resources are less.

As such, the present invention detects and prevents errors that may occur when two processors access the same address when the DPRAM is accessed.

Although the preferred embodiment of the present invention has been described above, the present invention may use various changes, modifications, and equivalents. It is clear that the present invention can be applied in the same manner by appropriately modifying the above embodiments. That is, the present invention can be applied not only to DPRAM but also to other multiport equipment. Accordingly, the above description does not limit the scope of the invention as defined by the limitations of the following claims.

As described above, the apparatus and method for controlling the common input / output RAM according to the present invention have an effect of detecting and preventing an error that may occur when two processors access the same address when the DPRAM is accessed. .

In addition, the present invention may implement an internal logic without allocating an IO pin of the PGA, thereby preventing an error that may occur due to simultaneous access.

Claims (7)

A DPRAM connected to a plurality of processors to transmit / receive data and addresses, and receive a control signal from a controller to control an access operation; Sending / receiving an address signal and a control signal from the plurality of processors, detecting when the plurality of processors access the same address when accessing the external DPRAM so that the plurality of processors read / write the DPRAM. A control unit controlling access of the DPRAM to separately perform the operation; And a plurality of processors for transmitting / receiving the control unit and an address / control signal, and transmitting / receiving the DPRAM and data / addresses outside of the control unit. A DPRAM connected to a plurality of processors to transmit / receive data and addresses, receive a control signal from a controller, and control an access operation therein; transmit / receive an address signal and a control signal from the plurality of processors; A control unit which detects when a plurality of processors access the same address when the plurality of processors access the internal DPRAM, and controls access of the DPRAM so that the plurality of processors separately perform read / write operations to the DPRAM; And a plurality of processors for transmitting / receiving the control unit and the address / control signal, and transmitting / receiving the DPRAM and data / address inside the control unit. A first step of determining whether a situation that meets a preset condition occurs so as to determine whether an access collision occurs when accessing the DPRAM in a plurality of processors; And a second step of causing one processor to perform a write operation and another processor to perform a read operation when a situation that meets the preset condition occurs. The method of claim 3, wherein the first step, And determining whether each of the plurality of address signals generated when the plurality of processors accesses the DPRAM matches. The method of claim 3, wherein the first step, And determining whether each of the plurality of chip select signals generated when the plurality of processors accesses the DPRAM is active. The method of claim 3, wherein the first step, And determining whether each of the plurality of address signals generated when the plurality of processors accesses the DPRAM matches, and whether each of the plurality of chip selection signals is active. Determining whether an error has occurred when accessing the DPRAM in the plurality of processors; If the error has not occurred, causing a normal DPRAM access operation to be performed; If the error has occurred, the processor and the processor store the address and data to be read / write with respect to the DPRAM in a storage table that can temporarily store the address and data. And performing access to the DPRAM in a common input / output RAM.