KR100659082B1 - Plasma display panel - Google Patents

Abstract

The present invention is a rear substrate and a front substrate spaced apart to face each other; A partition wall disposed between the front substrate and the rear substrate and partitioning discharge cells in which gas discharge occurs; Discharge electrode pairs extending across the discharge cells and including an X electrode and a Y electrode spaced apart from each other in the discharge cell to interact with each other to generate a gas discharge; A first dielectric layer formed to cover the discharge electrode pairs; Fence-shaped M electrodes formed on the first dielectric layer, extending along the discharge electrode pairs, and having a space therein; A second dielectric layer formed to cover the M electrodes; Address electrodes extending across the discharge cells to intersect the pair of discharge electrodes and the M electrodes in each discharge cell; A third dielectric layer formed to cover the address electrodes; A phosphor layer disposed in the discharge cells; And a discharge gas in the discharge cell. The present invention provides a plasma display panel which induces a weak discharge during a reset operation and has a low back ground brightness to improve dark room contrast.

Description

Plasma display panel {Plasma display panel}

1 is a partially cutaway perspective view of a conventional plasma display panel of the M electrode form.

FIG. 2 is a plan view illustrating only the shapes of an electrode and a partition wall of the front substrate illustrated in FIG. 1.

3 is a partially cutaway perspective view of a plasma display panel according to an exemplary embodiment of the present invention.

FIG. 4 is a plan view illustrating only the shapes of an electrode and a partition of the front substrate illustrated in FIG. 3.

FIG. 5 is a cross-sectional view taken along the line A-A of FIG. 3, showing a state in which the upper plate is rotated 90 degrees.

FIG. 6 is a cross-sectional view illustrating a modified example of the plasma display panel illustrated in FIG. 5.

FIG. 7 is a plan view illustrating only a front substrate and electrodes formed thereon, and illustrates a state in which the first and second dielectric layers are removed.

FIG. 8 is a plan view illustrating two X electrode terminal portions formed in FIG. 7.

FIG. 9 is a block diagram illustrating a plasma display device including the plasma display panel of FIG. 3.

FIG. 10 is a waveform diagram of signals applied to electrodes disposed in one discharge cell of the plasma display panel of FIG. 3 in a unit sub-field.

Explanation of symbols on the main parts of the drawings

200: plasma display panel 211: front substrate

212 sustain electrode pair 213 M electrode

214: first dielectric layer 215: second dielectric layer

216: protective film 221: rear substrate

222: address electrode 225: third dielectric layer

226 fluorescent material 230 partition wall

231: X electrode 232: Y electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a plasma display panel in which the luminous efficiency is increased and the discharge start voltage is reduced.

Recently, a plasma display panel, which is drawing attention as a replacement for a conventional cathode ray tube display device, is discharged after a discharge gas is filled between two substrates on which a plurality of electrodes are formed. Is an apparatus in which a phosphor formed in a predetermined pattern by ultraviolet rays is excited to obtain a desired image.

The plasma display panel may be classified into a direct current type and an alternating current type according to a discharge type. In the DC plasma display panel, the electrodes are exposed to the discharge space so that the movement of charged particles is directly performed between the corresponding electrodes. In the AC plasma display panel, at least one electrode is covered with a dielectric layer, so that the direct charges of the corresponding electrodes are mutually reduced. The discharge is performed by the electric field of the wall charge instead of the movement of.

In the DC plasma display panel, since the charge is directly transferred between the corresponding electrodes, there is a problem in that the electrode is severely damaged. In recent years, an AC plasma display panel having an AC type, in particular, a three-electrode surface discharge structure is present. This has been generally employed.

However, when the distance between the X electrode and the Y electrode is increased in order to increase the discharge area, there is a problem that the power consumption increases because the discharge start voltage increases.

In order to improve the above problem, as shown in FIG. 1, a new electrode type plasma display panel has been introduced. The plasma display panel 100 includes an upper plate 150 and a lower plate 160, and in detail, a rear substrate 121 and a front substrate 111 spaced apart from and parallel to the rear substrate 121. A partition wall 130 disposed between the front substrate 111 and the rear substrate 121 and extending across the discharge cells 170, and extending across the discharge cells 170, and having an X electrode 131 and a Y electrode ( Discharge electrode pairs 112 having respective ones 132, a first dielectric layer 114 formed to cover the discharge electrode pairs 112, and a rear surface of the first dielectric layer 114. M electrodes 113 extending in parallel with the lines 112, a second dielectric layer 115 formed to cover the M electrodes 113, discharge electrode pairs 112 and M electrodes in each discharge cell 170. Address electrodes 122 extending across the discharge cells 170 to intersect the 113, a third dielectric layer 115 formed to cover the address electrodes 122, and disposed in the discharge cells 170. Fluorescent The body layer 126 and the discharge gas in the discharge cell 170 are provided.

In the structure of the M electrode type, the discharge space can be enlarged and the discharge voltage can be lowered. However, since the bus electrodes in the M electrode occupy a large area during the reset operation, the clear contrast is not good and an error may occur during the reset operation. There was a problem.

SUMMARY OF THE INVENTION In order to solve the above problems, an object of the present invention is to provide a plasma display panel in which a new structure is introduced on an M electrode, so that the wall charges are easily adjusted during the reset operation and discharge is easily generated so that no error occurs. .

In order to achieve the above object, the present invention

A rear substrate and a front substrate spaced apart to face each other;

A partition wall disposed between the front substrate and the rear substrate and partitioning discharge cells in which gas discharge occurs;

Discharge electrode pairs extending across the discharge cells and including an X electrode and a Y electrode spaced apart from each other in the discharge cell to interact with each other to generate a gas discharge;

A first dielectric layer formed to cover the discharge electrode pairs;

Fence-shaped M electrodes formed on the first dielectric layer, extending along the discharge electrode pairs, and having a space therein;

A second dielectric layer formed to cover the M electrodes;

Address electrodes extending across the discharge cells to intersect the pair of discharge electrodes and the M electrodes in each discharge cell;

A third dielectric layer formed to cover the address electrodes;

A phosphor layer disposed in the discharge cells; And

It provides a plasma display panel comprising a; discharge gas in the discharge cell.

In the present invention, the X electrodes are preferably connected in common on one side of the front substrate.

In addition, in the present invention, the M electrodes are preferably provided with terminal portions connected to the flexible printed circuit board (FPCB) on one side of the front substrate.

In the present invention, the M electrode is preferably disposed between the paired X electrode and Y electrode.

According to another aspect of the present invention, the present invention provides a rear substrate and a front substrate spaced apart to face each other; A partition wall disposed between the front substrate and the rear substrate and partitioning discharge cells in which gas discharge occurs; Fence-shaped M electrodes extending along the discharge cells and having a space formed therein; A first dielectric layer formed to cover the M electrodes; An X electrode and a Y electrode formed on the first dielectric layer so as to extend in parallel to the M electrode, extending across the discharge cells, and spaced apart from each other in the discharge cells to interact with each other to generate a gas discharge. Discharge electrode pairs provided; A second dielectric layer formed to cover the discharge electrode pairs; Address electrodes extending across the discharge cells to intersect the pair of discharge electrodes and the M electrodes in each discharge cell; A third dielectric layer formed to cover the address electrodes; A phosphor layer disposed in the discharge cells; And a discharge gas in the discharge cell.

The X electrodes are preferably plasma display panels, which are commonly connected to one side of the front substrate.

The M electrodes are preferably plasma display panels, each having terminal portions connected to a flexible printed circuit board (FPCB) on one side of the front substrate.

The M electrode is disposed between the pair of the X electrode and the Y electrode to provide a plasma display panel.

Next, an embodiment of the present invention will be described in detail with reference to the drawings.

3 illustrates a plasma display panel 200 according to an exemplary embodiment of the present invention. A plurality of discharge electrode pairs 212 are disposed on the front substrate 211. At this time, the front substrate 211 is generally formed of a transparent material mainly made of glass.

The discharge electrode pair 212 refers to a pair of discharge electrodes 231 and 232 formed on the rear surface of the front substrate 211 to cause sustain discharge, and the discharge electrode pairs 212 are formed on the front substrate 211. It is arranged in parallel at predetermined intervals. One of the discharge electrode pairs 212 is the X electrode 231, and the other discharge electrode is the Y electrode 232.

Each of the X electrode 231 and the Y electrode 232 includes transparent electrodes 231a and 232a and bus electrodes 231b and 232b. The transparent electrodes 231a and 232a are formed of a transparent material that is a conductor capable of causing a discharge and does not prevent light emitted from the phosphor 226 from advancing to the front substrate 211. oxide). However, transparent conductors such as ITO generally have high resistance, and thus, when the discharge sustaining electrode is formed only by the transparent electrode, a large voltage drop in the longitudinal direction consumes a lot of driving power and slows the response speed. In order to improve, the bus electrodes 231b and 232b made of a metal material and formed in a narrow width are disposed on the transparent electrode.

The first dielectric layer 214 is formed on the front substrate 211 provided with the discharge electrode pairs 212 to fill the discharge electrode pairs 212. The first dielectric layer 214 is directly energized between the adjacent X electrode 231 and the Y electrode 232 during sustain-discharge, and positive or negative electrons collide directly with the discharge electrodes 231 and 232 so that the X electrode 231 is discharged. And the Y electrode 232, while preventing damage, are formed of a dielectric material capable of inducing charge and accumulating wall charges. Such dielectrics include PbO, B ₂ O ₃ , SiO _2, and the like.

FIG. 2 is a plan view illustrating an arrangement of electrodes formed on the front substrate 111 and a partition wall of a lower plate according to the related art, in a state in which the first dielectric layer 114 and the second dielectric layer 115 are removed. In the image display area in which an image is displayed, the X electrodes 131, the Y electrodes 132, and the M electrodes 113 are spaced apart from each other and arranged in parallel on the front substrate 111. Although the X electrodes 131, the Y electrodes 132, and the M electrodes 113 are shown as being disposed at the same level on the front substrate 211, the X electrodes 131 and the Y electrode 132 are illustrated. Are formed at the same level, and the M electrodes 113 are formed farther from the front substrate 111 than the X electrodes 131 and the Y electrodes 132. The M electrode 113 is formed in a form in which the bus electrode 113b is disposed at the center portion of the transparent electrode 113a.

FIG. 4 is a plan view illustrating only the partitions of the rear substrate and the arrangement of the electrodes formed on the front substrate 211 in a state in which the first dielectric layer 214 and the second dielectric layer 215 are removed. Referring to the drawing, in the image display area where an image is displayed, the X electrodes 231, the Y electrodes 232, and the M electrodes 213 are spaced apart from each other and arranged in parallel on the front substrate 211.

FIG. 5 is a cross-sectional view taken along the line A-A of FIG. 3, showing a state in which the upper plate is rotated 90 degrees. The M electrode 213 is disposed between the paired X electrode 231 and the Y electrode 232. The M electrode 213 is formed on the rear surface of the first dielectric layer 214 and extends in one direction to be parallel to the X electrode 231 and the Y electrode 232. The M electrode 213 of the present invention does not have a transparent electrode but only a bus electrode. In addition, the M electrode is a fence-type structure in which a space is formed inside, so that the wall charge can be easily adjusted during the reset operation and the electric field is strong and easily caught in the reset operation as compared with the electrode-filled structure. Easy to concentrate electric field

In addition, a second dielectric layer 215 is formed to fill the M electrodes 213. The second dielectric layer 215 prevents direct conduction between adjacent X electrodes 231, Y electrodes 232, and M electrodes, and cations or electrons directly collide with the M electrodes 213 to prevent M electrodes ( 213) to inhibit damage. In addition, the second dielectric layer 215 is formed of a dielectric material capable of inducing charge to accumulate wall charges. Such dielectrics include PbO, B ₂ O ₃ , SiO ₂ , and the like, and are the same as the first dielectric layer 214. It is preferable to form using a dielectric.

In addition, a protective film 216 made of MgO is formed on the lower surface of the second dielectric layer 215. The protective film 216 prevents cations and electrons from colliding with the second dielectric layer 215 during the discharge, thereby damaging the first dielectric layer 215, and has good light transmittance and emit a large amount of secondary electrons during the discharge.

The address electrode 222 is disposed on the front surface of the rear substrate 221 so as to intersect the X electrode 231 and the Y electrode 232 of the front substrate 211.

The address electrodes 222 are intended to cause an address discharge to facilitate sustain-discharge between the X electrode 231 and the Y electrode 232. More specifically, the address electrodes 222 lower the voltage for sustain-discharge. do. The address discharge is a discharge that occurs between the M electrode 232 and the address electrode 222.

The space formed by the pair of X electrodes 231, Y electrodes 232, and M electrodes arranged in this way, and the address electrodes 222 intersecting the same form one discharge unit as the unit discharge cells 270.

A third dielectric layer 225 is formed on the back substrate 221 provided with the address electrode 222 to fill the address electrode 222. The third dielectric layer 225 is formed as a dielectric that can induce charge while preventing cations or electrons from colliding with the address electrode 222 during the discharge and damaging the address electrode 222. Such dielectrics include PbO and B ₂ O ₃ , SiO ₂ and the like.

Between the second dielectric layer 215 and the third dielectric layer 225, the discharge distance is maintained and the red (R), green (G), and blue (B) discharge cells are divided, and the electrical space between the discharge cells 270 is maintained. The partition wall 230 which prevents optical crosstalk is formed. Although the partition wall 230 is illustrated in FIG. 3 as being divided into stripes, the present invention is not limited thereto. As long as a plurality of discharge spaces may be formed, partition walls of various patterns, for example, a matrix, for example, a waffle may be used. It can be a closed bulkhead, such as a matrix, a delta, or the like. In addition, the closed partition wall may be formed such that the cross section of the discharge space is a polygon, such as a triangle, a pentagon, or a circle, an ellipse, or the like, in addition to the rectangle as in the present embodiment.

Phosphor layers 226 of red, green, and blue are formed on the entire surface of the second dielectric layer 225 between the partition walls 230 partitioning the discharge cells 270. In addition, the phosphor layer 226 is formed on the side surface of the partition wall 230.

The phosphor layer 226 has a component for generating visible light by receiving ultraviolet rays, and the red phosphor layer formed in the red discharge cell includes phosphors such as Y (V, P) O ₄ : Eu, and the like. The formed red phosphor layer includes a phosphor such as Zn ₂ SiO ₄ : Mn, and the blue phosphor layer formed in the blue discharge cell includes a phosphor such as BAM: Eu.

The discharge cell 270 is filled with a discharge gas such as Ne, He, Xe, and the like and a mixed gas thereof.

6 shows a modification according to an embodiment of the present invention. 5 is different from that of the plasma display panel 300 according to the modified example, the M electrodes 313 covered by the first dielectric layer 314 are formed on the rear surface of the front substrate 311, and the X electrode ( 331 and the Y electrodes 332 are covered by the second dielectric layer 315. An MgO protective film 316 is formed on the back surface of the second dielectric layer.

FIG. 7 illustrates an arrangement of electrodes formed on the front substrate 211 with the first dielectric layer 214 and the second dielectric layer 215 removed. Referring to the drawing, in the image display area where an image is displayed, the X electrodes 231, the Y electrodes 232, and the M electrodes 213 are spaced apart from each other and arranged in parallel on the front substrate 211. Here, the X electrodes 231, the Y electrodes 232, and the M electrodes 213 are shown as being disposed at the same level on the front substrate 211, but as described above, the X electrodes 231 and Y are described. Only the electrodes 232 are formed at the same level, and the M electrodes 213 are formed farther from the front substrate 211 than the X electrodes 231 and the Y electrodes 232.

The bus electrodes 232b of the Y electrode are spaced apart from each other to one side of the front substrate 211, and are connected to each other at an edge portion. When the plasma display panel 200 is driven, since the same signal is applied to the bus electrodes 232b of the Y electrode, the bus electrodes 232b of the Y electrode are electrically connected in common. The portion 232d to which the bus electrodes 232b of the Y electrode are commonly connected is a non-image display area of the plasma display panel, in which a substantial discharge is not generated. A terminal portion 232c is formed in the connection portion 232d of the Y electrode so that the bus electrode 232b of the Y electrode can be electrically connected to the Y driving portion (not shown) and the FPCB. Although one terminal portion is illustrated in FIG. 7, two terminal portions 232c ′ may be formed as shown in FIG. 8. The number and formation positions of the terminal portions are not limited to this. Since the terminal portions 232c of the bus electrodes 232b of the Y electrode are exposed to the outside for connection with the FPCB, the first dielectric layer 214 and the second dielectric layer 215 are not formed in this portion.

Similarly to the bus electrodes 232b of the Y electrodes, the bus electrodes 231b of the X electrodes are connected in common because common signals are applied. That is, they are spaced apart from each other to the other side of the front substrate 211 and are connected to each other in a non-image display area that is an edge portion. In addition, a terminal portion 231c is formed in the connected portion 231d to be electrically connected to the X driver (not shown) and the FPCB. Since the terminal portion 231c of the bus electrodes 231b of the X electrodes is exposed to the outside for connection with the FPCB, the first dielectric layer 214 and the second dielectric layer 215 are not formed in this portion.

Since independent signals are applied to the M electrodes 213, the M electrodes 213b are spaced apart from each other, and the M electrodes 213 extend to one side of the front substrate, and the edges of the non-image display area are extended. Terminal portions 213c are formed, respectively.These terminal portions 213c are electrically connected to each other by an M electrode driver (not shown) and an FPCB. Therefore, the first dielectric layer 214 and the second dielectric layer 215 are not formed in this portion.

As shown in FIG. 9, the plasma display apparatus 400 including the plasma display panel 200 according to an exemplary embodiment of the present invention includes the above-described plasma display panel 200, an image processor 456, and a logic controller. 462, an address driver 423, an X driver 424, a Y driver 425, and an M driver 426.

The image processing unit 456 converts an external analog image signal into a digital signal to convert an internal image signal, for example, 8 bits of red (R), green (G), and blue (B) image data, a clock signal, vertical and horizontal, respectively. Generate sync signals. The logic controller 462 is configured to drive driving signals S _A , S _X , and the like according to an internal image signal from the image processor 456. S _Y , S _M ) is generated.

The address driver 423 processes the address driving signal S _A among the driving control signals S _A and S _S from the logic controller 462 to generate display data signals, and addresses the generated display data signals. To the electrodes 222. The X driver 424 may control driving control signals S _A , S _X , S _Y , S _M) processes the X driving control signal _(X S) in to be applied to the X electrode 231. In addition, the Y driver 425 may control driving control signals S _A , S _X , and _A from the logic controller 462. S _Y , The S _M driving control signal S _Y is processed and applied to the Y electrodes 232, and the M driving unit 426 drives driving control signals S _A , S _X , and S from the logic controller 462. S _Y , S _M) from among processes the M drive control signal (S _M) is applied to the M electrode 213.

The X electrodes 231 are commonly connected, common driving control signals are applied, and the Y electrodes 232 are commonly connected, and common driving control signals are applied.

FIG. 10 is a waveform diagram of signals applied to electrodes disposed in one discharge cells of the plasma display panel 200 in a unit sub-field SF. Each unit frame is divided into eight subfields SF ₁ , SF ₂ , SF ₃ , SF ₄ , SF ₅ , SF ₆ , SF ₇ , and SF ₈ to realize time division gray scale display. In addition, each subfield SF is divided into a reset time R, an addressing time A, and a sustain-discharge time S. FIG.

In FIG. 10, S _A denotes a drive signal applied to the address electrode 222, S _X denotes a drive signal applied to the X electrode 231, and S _Y denotes a drive signal applied to the X electrode 232. S _M indicates a drive signal applied to the M electrode 213.

In the reset time R of the unit subfield SF, the respective discharge cells 270 become uniform and at the same time suitable for addressing to be performed in the next step. At this time, the ground voltage, which is the first voltage V _G , is applied to the address electrode 222 and the Y electrode 232. The voltage applied to the M electrode 213 first rises to the second voltage V _SET + V _S and then decreases to the first voltage V _G. At this time, the first voltage V _G is first applied to the X electrode 231, while the M electrode 213 is reduced from the second voltage V _SET + V _S to the first voltage V _G. A sustain voltage of 3 voltages V _S is applied.

At each addressing time A, display data pulses of the address voltage V _A are applied to the address electrode 222 and M electrodes biased with the scan voltage V _SCAN lower than the third voltage V _S. The scan pulse of the first voltage V _G is applied to 213. Accordingly, when high-level display data pulses are applied while the scan pulse is applied, wall charges are formed by the address discharge. That is, as a result of the address discharge, negative wall charges are accumulated on the X electrode 231, and positive wall charges are accumulated on the M electrode 213 and the Y electrode 232. 8, the scan pulse is applied to the M electrode 213, but since the scan pulse is not applied to the discharge cells that do not require address discharge, wall charges are not formed in the discharge cell.

At each sustain-discharge time S, sustain-discharge pulses are alternately applied to all the X electrodes 231 and Y electrodes 232, so that sustain discharges are generated when wall charges are formed at the corresponding addressing time A. FIG. Cause At this time, the M electrode 231 and the address electrode 222 are biased to the third voltage V _S and the first voltage V _G , respectively.

However, when the sustain-discharge is started, the first voltage V _G is applied to the X electrode 231 in which the negative wall charges are accumulated, and the third voltage in the M electrode 213 in which the positive wall charges are accumulated. Since V _S is applied, the discharge starts between the X electrode 231 and the M electrode 213 which are relatively close in distance. Therefore, since the discharge starts between the electrodes arranged at a close distance, the discharge start voltage is reduced.

After the discharge occurs between the X electrode 231 and the M electrode 213, the discharge region is extended to the Y electrode 232, so that sustaining-discharge is actively performed between the X electrode 231 and the Y electrode 232. Occurs. In particular, when the distance between the X electrode 231 and the Y electrode 232 is disposed far, since the discharge space is increased, the discharge is actively generated, and ultimately the luminous efficiency is increased. Therefore, due to the sustain-discharge between the X electrode 231, the M electrode 213, and the Y electrode 232, the discharge start voltage can be reduced and the luminous efficiency can be increased.

The luminance of the plasma display panel is proportional to the length of the sustain-discharge time S occupied in the unit frame. The length of the sustain-discharge time S occupied in the unit frame is 255T (T is the unit time). Therefore, it can be displayed in 256 gray levels, including the case where it is not displayed once in a unit frame.

Here, the first maintenance of the sub-fields (SF ₁₎ - the discharge time, the time (1T) corresponding to ^20, the second holding of the sub-field (SF ₂₎ - Time to discharge time corresponding to the 2 ¹ (2T) The time 4T corresponding to 2 ² in the sustain-discharge time of the third subfield SF ₃ , and the time 8T corresponding to 2 ³ in the sustain-discharge time of the fourth subfield SF ₄ . In the sustain-discharge time of the fifth subfield SF ₅ , a time 16T corresponding to 2 ⁴ and a sustained-discharge time of the sixth subfield SF ₆ , 32T correspond to 2 ⁵ . This time 64T corresponds to 2 ⁶ in the sustain-discharge time of the seventh subfield SF ₇ , and the time 128T corresponds to 2 ⁷ in the sustain-discharge time of the eighth subfield SF ₈ . Are set respectively.

Accordingly, if a subfield to be displayed is appropriately selected from the eight subfields, display of 256 gray levels may be performed including all zero (zero) gray levels that are not displayed in any of the subfields.

The plasma display panel according to the present invention has the following effects.

First, since the M electrode disposed between the X electrode and the Y electrode is partially filled, the dark ground contrast can be improved by inducing a weak discharge during a reset operation and lowering the back ground luminance as compared with the whole filled structure.

Second, an electric field concentration effect can be obtained which can cause the electric field to be strong and easily caught in the reset operation.

Third, the manufacturing cost can be reduced by not using the transparent electrode used for the M electrode.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

Claims (10)

A rear substrate and a front substrate spaced apart to face each other; A partition wall disposed between the front substrate and the rear substrate and partitioning discharge cells in which gas discharge occurs; Discharge electrode pairs extending across the discharge cells and including an X electrode and a Y electrode spaced apart from each other in the discharge cell to interact with each other to generate a gas discharge; A first dielectric layer formed to cover the discharge electrode pairs; M electrodes formed on the first dielectric layer, extending along the discharge electrode pairs, and having only a bus electrode in a fence shape having a space therein; A second dielectric layer formed to cover the M electrodes; Address electrodes extending across the discharge cells to intersect the pair of discharge electrodes and the M electrodes in each discharge cell; A third dielectric layer formed to cover the address electrodes; A phosphor layer disposed in the discharge cells; And And a discharge gas in the discharge cell. The method of claim 1, And the X electrodes are commonly connected at one side of the front substrate. The method of claim 1, And the Y electrodes are commonly connected to one side of the front substrate. The method of claim 3, And at least one terminal portion connected to a flexible printed circuit board (FPCB) on one side of the front substrate at a portion where the Y electrodes are commonly connected. The method of claim 1, And the M electrode is disposed between the paired X and Y electrodes. A rear substrate and a front substrate spaced apart to face each other; A partition wall disposed between the front substrate and the rear substrate and partitioning discharge cells in which gas discharge occurs; M electrodes extending along the discharge cells and having only a bus electrode in a fence shape having a space therein; A first dielectric layer formed to cover the M electrodes; An X electrode and a Y electrode formed on the first dielectric layer so as to extend in parallel to the M electrode, extending across the discharge cells, and spaced apart from each other in the discharge cells to interact with each other to generate a gas discharge. Discharge electrode pairs provided; A second dielectric layer formed to cover the discharge electrode pairs; Address electrodes extending across the discharge cells to intersect the pair of discharge electrodes and the M electrodes in each discharge cell; A third dielectric layer formed to cover the address electrodes; A phosphor layer disposed in the discharge cells; And And a discharge gas in the discharge cell. The method of claim 6, And the X electrodes are commonly connected at one side of the front substrate. The method of claim 6, And the Y electrodes are commonly connected to one side of the front substrate. The method of claim 8, And at least one terminal portion connected to a flexible printed circuit board (FPCB) on one side of the front substrate at a portion where the Y electrodes are commonly connected. The method of claim 6, And the M electrode is disposed between the paired X and Y electrodes.

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