KR100647649B1 - Plasma display panel - Google Patents

Abstract

According to the present invention, the size of the transparent electrode (ITO electrode) of the intermediate electrode (M electrode) is made relatively smaller than that of the sustain electrode in the plasma display panel having a multi-electrode structure, thereby reducing luminance by shielding the transparent electrode of the intermediate electrode. The present invention relates to a plasma display panel that can be prevented.

The present invention for this purpose, the rear substrate; A front substrate spaced apart from and parallel to the rear substrate; A partition wall disposed between the front substrate and the rear substrate and partitioning discharge cells; Sustain electrode pairs extending across the discharge cells and having X and Y electrodes, respectively; Interposed between the paired X and Y electrodes and extending in parallel with the X and Y electrodes, wherein the sustain electrode pairs and the intermediate electrodes are respectively a bus electrode and the bus electrode. And a transparent electrode (ITO electrode) electrically connected to each other, wherein the size of each transparent electrode of the intermediate electrodes in the discharge cells is smaller than that of each of the sustain electrode pairs.

Description

Plasma display panel {Plasma display panel}

1 is a timing diagram for explaining a conventional driving signal for driving a plasma display panel having a multi-electrode structure.

2A to 2D are diagrams illustrating wall charge states of a plasma display panel in an address period when the driving signal of FIG.

3 is a cross-sectional view of an electrode structure of a plasma display panel having a multi-electrode structure according to the prior art.

Figure 4 is a partially cutaway perspective view of the plasma display panel according to an embodiment of the present invention.

FIG. 5 is a cross-sectional view taken along line III-III of FIG. 4, with the top plate rotated 90 degrees. FIG.

FIG. 6 is a plan view illustrating shapes of electrodes disposed in respective discharge cells of FIG. 4. FIG.

FIG. 7 is a plan view of another embodiment showing the shape of electrodes disposed in each discharge cell of FIG. 4; FIG.

FIG. 8 is a block diagram illustrating a plasma display device including the plasma display panel of FIG. 4. FIG.

<Description of the symbols for the main parts of the drawings>

100: plasma display panel 111: front substrate

112: sustain electrode pair 113: intermediate electrode

115: first dielectric layer 116: protective film

121: back substrate 122: address electrode

126: phosphor 130: partition wall

131: X electrode 132: Y electrode

The present invention relates to a plasma display panel, and more particularly, to form a transparent electrode (ITO electrode) of the middle electrode (M electrode) smaller than the size of the transparent electrode of the sustain electrode, thereby reducing the luminance of the intermediate electrode. A plasma display panel having a multi-electrode structure can be prevented from being reduced.

Recently, a plasma display panel, which is drawing attention as a replacement of a conventional cathode ray tube display device, is discharged after a discharge gas is filled between two substrates on which a plurality of electrodes are formed. The phosphor formed in a predetermined pattern by the ultraviolet rays is excited to obtain a desired image.

The three-electrode structure of a general plasma display panel is disclosed in Japanese Laid-Open Patent Publication No. 1999-120924. The three-electrode structure is a structure in which an address electrode is disposed so as to be orthogonal to the sustain electrode and the scan electrode with respect to the sustain electrode (or 'X electrode') and the scan electrode (or 'Y electrode') arranged in parallel. It is. In order to drive the three-electrode structure, an ADS (Address Display Separation) driving method is used. That is, the plasma display panel is driven by applying a driving signal having a reset period, an address period, and a sustain discharge period to the scan electrode, sustain electrode, and address electrode.

However, the plasma display panel having a three-electrode structure has a problem in that the discharge volume of the discharge cell, which is an area intersected by the scan electrode, the sustain electrode and the address electrode, is small, and thus the luminance is not good. In order to improve this problem, efforts have been made to develop a plasma display panel having a four-electrode structure in which an intermediate electrode (or 'M electrode') is further provided between the sustain electrode and the scan electrode to enlarge the discharge volume of the discharge cell. In the four-electrode plasma display panel, as described above, the intermediate electrode is interposed between the sustain electrode and the scan electrode to generate long gap discharge between the sustain electrode and the scan electrode to increase the luminance.

1 is a timing diagram illustrating a conventional driving signal for driving a plasma display panel having a multi-electrode structure, and FIGS. 2A to 2D are wall charge states of a plasma display panel in an address section when the driving signal of FIG. 1 is applied. Figure showing.

The driving method of the above-described multi-electrode structure, for example, a four-electrode plasma display panel will be described with reference to FIGS. 1 and 2A through 2D.

One subfield SF has a reset period PR, an address period PA, and a sustain discharge period PS, and includes address electrodes A1, ..., Am, sustain electrodes X1,... , Xn), the driving signals are applied to the intermediate electrodes M1, ..., Mn and the scan electrodes Y1, ..., Yn, respectively.

First, the reset period PR applies a reset pulse to all of the intermediate electrodes M1, ..., Mn to perform reset discharge, thereby initializing the wall charge state of all the discharge cells. The reset period PR is carried out before entering the address period PA, which is carried out over the entire screen, thus making it possible to create a fairly even and evenly distributed wall charge arrangement. To this end, in the reset period PR from time t1 to t2 in FIG. 1, the ground voltage Vg is first applied to the intermediate electrodes M1,..., Mn, and then the sustain discharge voltage Vs. Is applied, a rising ramp function is applied from the sustaining discharge voltage Vs to reach a rising maximum voltage Vset + Vs which is increased by the rising voltage Vset, and then rapidly descends to the sustaining discharge voltage Vs, A falling ramp function is applied from the sustain discharge voltage Vs to reach the lowest falling voltage, for example, the ground voltage Vg. The ground voltage Vg is applied to the address electrodes A1, ..., Am and the scan electrodes Y1, ..., Yn during the reset period PR, and the sustain electrodes X1, ... , Xn) is continuously applied to the sustain discharge voltage (Vs) when the rising ramp function is applied.

Next, in the address period PA from time t2 to t3, the sustain discharge voltage Vs is applied to the sustain electrodes X1, ..., Xn in order to select a cell to be turned on, and the intermediate electrode The scan voltages Vscan are applied to the fields M1, ..., Mn, and the scan pulses having the ground voltage Vg are sequentially applied to the intermediate electrodes M1, ..., Mn. A display data signal having an address voltage Va is applied to the address electrodes A1, ..., Am in accordance with the scan pulse. As the scan pulse and the display data signal are applied, address discharge is performed in the selected discharge cell. Meanwhile, the ground voltage Vg is applied to the scan electrodes Y1,..., And Yn.

Next, in the sustain discharge period PS from the time t3 to the time t4, the sustain electrodes X1, ..., Xn and the scan are performed so that the sustain discharge is performed in the cell to be turned on selected in the address period PA. A sustain pulse having a sustain discharge voltage Vs is alternately applied to the electrodes Y1, ..., Yn. The sustain discharge is performed by the wall charge accumulated in the discharge cell selected by the address discharge and the applied sustain discharge voltage Vs. Plasma is formed from the plasma forming gas of the discharge cells which perform the sustain discharge, and the phosphors of the discharge cells are excited by ultraviolet radiation from the plasma to generate light.

The wall charge state inside the discharge cell will be described in detail with reference to FIG. 2.

First, referring to FIG. 2A, as the rising ramp signal and the falling ramp signal are applied to the intermediate electrodes M1,..., And Mn in the reset period PR, the negative polarity is formed near the intermediate electrode M. FIG. Wall charges will accumulate. Accordingly, positive wall charges are accumulated in the vicinity of the address electrode A and the scan electrode Y, and positive wall charges are not accumulated in the vicinity of the sustain electrode X due to the sustain discharge voltage Vs applied during the falling ramp. I can't.

During the address period PA, a positive scan voltage Vscan is applied to the intermediate electrodes M1, ..., Mn, and a scan pulse having a ground voltage Vg is sequentially applied to each of the intermediate electrodes. A display data signal having a positive address voltage Va is applied to (A1, ..., Am) according to the scanning pulse, and the sustain electrode (X1, ..., Xn) has a dielectric constant voltage ( Vs) is applied, and the ground voltage Vg is applied to the scan electrodes Y1, ..., Yn.

Referring to Fig. 2B, a diagram showing a state of wall charges in the discharge cells immediately before the address discharge, in which the negative wall charges are accumulated near the intermediate electrode M, and near the scan electrode Y and the address electrode A. Figs. ), Wall charges of positive polarity continue to accumulate.

FIG. 2C is a diagram showing the state of wall charges in the discharge cells during the address discharge, and is due to the ground voltage Vg applied to the intermediate electrode M and the address voltage Va applied to the address electrode A. FIG. Address discharge starts to occur between (M) and the address electrode (A). Due to the address discharge, positive wall charges are accumulated near the intermediate electrode M, and negative wall charges are accumulated near the address electrode A. As shown in FIG. At this time, since the gap between the electrodes between the intermediate electrode M and the scan electrode Y is small, the negative wall charges accumulated near the address electrode A and the positive wall charges accumulated near the scan electrode Y are accumulated. Due to the secondary discharge occurs.

2D is a diagram showing the state of wall charges in the discharge cells after the address discharge is completed. Due to the secondary discharge, the wall charges accumulated on the electrodes in the discharge cell are mostly erased. That is, a small amount of negative wall charges are accumulated near the intermediate electrode M, and a small amount of negative wall charges are accumulated near the scan electrode Y, and a very small amount of positive polarity is accumulated in the address electrode A. Electric charges will accumulate.

 In order to generate sustain discharge in the four-electrode structure, as described above, a sustain pulse having a sustain discharge voltage Vs is alternately applied to the scan electrode Y and the sustain electrode X, and to the intermediate electrode M. A positive voltage is applied. Since the four-electrode structure has a feature that the distance between the sustain electrode X and the scan electrode Y is longer than the three-electrode structure, the four-electrode structure directly between the scan electrode Y and the sustain electrode X in the four-electrode structure. Maintenance discharges are difficult to occur. Therefore, in the sustain discharge of the four-electrode structure, a discharge (trigger discharge) between the sustain electrode X and the intermediate electrode M occurs first, and this discharge is expanded to discharge between the sustain electrode X and the scan electrode Y. It has a mechanism that extends to (long gap discharge). As described above, since the plasma display panel having the four-electrode structure generates long gap discharge between the sustain electrode X and the scan electrode Y, the plasma display panel having the four-electrode structure has higher luminance than the plasma display panel having the three-electrode structure.

However, in the conventional four-electrode structure, that is, the multi-electrode plasma display panel, as shown in FIG. 3, the size of the ITO electrode ITO_M included in the intermediate electrode M is the sustain electrode X and the scan electrode ( Since the ITO electrodes ITO_X and ITO_Y included in Y) are formed to have the same size, the luminance is slightly decreased due to the shielding of the ITO electrodes ITO_M of the intermediate electrode M. FIG. In FIG. 3, reference numerals M_X, M_M, and M_Y denote conductive bus electrodes included in the sustain electrode X, the intermediate electrode M, and the scan electrode Y, respectively.

Accordingly, the technical problem to be achieved by the present invention is to make the size of the transparent electrode (ITO electrode) of the intermediate electrode (M electrode) in the multi-electrode plasma display panel relatively smaller than that of the sustain electrode. The present invention provides a plasma display panel capable of preventing a decrease in luminance due to shielding of an electrode.

The present invention, in order to achieve the above technical problem, the back substrate; A front substrate spaced apart from and parallel to the rear substrate; A partition wall disposed between the front substrate and the rear substrate and partitioning discharge cells; Sustain electrode pairs extending across the discharge cells and having X and Y electrodes, respectively; Intermediate electrodes disposed between the paired X and Y electrodes and extending in parallel with the X and Y electrodes; A first dielectric layer formed to cover the sustain electrode pairs and the intermediate electrodes; Address electrodes extending across the discharge cells to intersect the sustain electrode pair and the intermediate electrode in the discharge cell; A second dielectric layer formed to cover the address electrodes; A phosphor layer disposed in the discharge cells; And a discharge gas in the discharge cell;

The sustain electrode pairs and the intermediate electrodes each have a bus electrode and a transparent electrode (ITO electrode) electrically connected to the bus electrode, and the size of each transparent electrode of the intermediate electrodes in the discharge cells is the sustain electrode. A plasma display panel is provided that is formed smaller than the size of each transparent electrode of the pairs.

In a preferred embodiment of the present invention, the internal size of the discharge cell corresponding to the longitudinal direction of the sustain electrode pair and the intermediate electrode is a, the transparent of the intermediate electrode corresponding to the internal size (a) of the discharge cell When the electrode size is b, the transparent electrode of the intermediate electrode is formed to conform to the formula (1.2 ≦ a / b ≦ 2.4).

Hereinafter, preferred embodiments of the plasma display panel according to the present invention will be described in detail with reference to the accompanying drawings. In the following description of the present invention, when it is determined that detailed descriptions of related well-known technologies or configurations may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted. In addition, terms to be described below are terms defined in consideration of functions in the present invention, which may vary according to the intention or custom of a user or an operator. Therefore, the definition should be made based on the contents throughout the specification.

In the following description, when the member according to the prior art and the member according to the present invention are the same, the same reference numerals used in the prior art are used as they are, and detailed description thereof will be omitted.

4 and 5, an AC plasma display panel 100 having a multi-electrode structure according to an exemplary embodiment of the present invention is shown. 5 illustrates a state in which the upper plate 150 is rotated 90 degrees for convenience of description.

As shown, the plasma display panel 100 includes a top plate 150 and a bottom plate 160 coupled in parallel therewith, and are provided on the front substrate 111 and the bottom plate 160 provided on the top plate 150. The plurality of discharge cells 170 are partitioned by the partition wall 130 between the rear substrates 121. The partition wall 130 functions to prevent optical crosstalk between the discharge cells 170. In the present embodiment, the partition wall 130 partitions the discharge cells 170 having rectangular cross sections. However, the barrier rib 130 may be a barrier rib of various patterns, for example, a closed barrier rib such as a waffle, a matrix, a delta, or the like, as long as a plurality of discharge spaces can be formed. In addition, the closed partition wall may be formed such that the cross section of the discharge space is a polygon such as a triangle, a square, a pentagon, or a circle, an ellipse, or the like.

A plurality of sustain electrode pairs 112 are disposed on the front substrate 111. In this case, the front substrate 111 is generally formed of a transparent material mainly made of glass.

The sustain electrode pair 112 refers to a pair of sustain electrodes 131 and 132 formed on the rear surface of the front substrate 111 to cause sustain discharge, and the sustain electrode pair 112 is formed on the front substrate 111. It is arranged in parallel at predetermined intervals. One of the sustain electrode pairs 112 is the X electrode 131 and the other sustain electrode is the Y electrode 132. In the present embodiment, the sustain electrode pairs 112 are disposed on the rear surface of the front substrate 111, but the arrangement position of the sustain electrode pairs is not limited thereto. For example, the sustain electrode pairs may be spaced apart from the rear surface of the front substrate at predetermined intervals. However, the sustain electrode pairs are preferably disposed at the same level from the front substrate. Each of the X electrode 131 and the Y electrode 132 includes transparent electrodes 131a and 132a and bus electrodes 131b and 132b.

The intermediate electrode 113 is disposed between the paired X electrode 131 and the Y electrode 132. The intermediate electrode 113 is formed on the rear surface of the front substrate 111 and extends in one direction across the discharge cells 170 in parallel with the X electrode 131 and the Y electrode 132. The intermediate electrode 113 also includes a transparent electrode 113a and a bus electrode 113b. The intermediate electrode 131 may be disposed at a different level from the X electrode 131 and the Y electrode 132, but the X electrode 131 and the Y electrode 132 may be disposed to perform the electrode forming process in the same process. It is preferable to be disposed at the same level from the front substrate 111.

The transparent electrodes 131a, 132a, and 113a of each electrode are formed of a transparent material that is a conductor capable of causing a discharge and does not prevent light emitted from the phosphor 126 from advancing to the front substrate 111. Examples thereof include indium tin oxide (ITO). However, transparent conductors such as ITO generally have a high resistance, and thus, when the sustain electrode is formed only of the transparent electrodes, a large voltage drop in the longitudinal direction consumes a lot of driving power and slows the response speed. To this end, bus electrodes 131b, 132b, and 113b made of a metal material and formed to have a narrow width are disposed.

Hereinafter, the shape and arrangement of the X electrode 131, the Y electrode 132, and the intermediate electrode 113 will be described in detail with reference to FIG. 6. The bus electrodes 131b, 132b, and 113b are spaced apart from the unit discharge cells 170 at predetermined intervals in parallel and extend across the discharge cells 170. Transparent electrodes 131a, 132a, and 113a are electrically connected to the bus electrodes 131b, 132b, and 113b. The transparent electrodes 131a and 132a included in the X electrode 131 and the Y electrode 132, respectively, are arranged in the same shape as the corresponding bus electrodes 131b and 132b with only different widths. The transparent electrode 113a included in the intermediate electrode 113 is discontinuously disposed for each unit discharge cell 170. The transparent electrode 113a of the intermediate electrode 113 has a shape of a rectangle (FIG. 6) or an octagon (FIG. 7; 113a ′). The rectangular transparent electrode 113a may be advantageous in the manufacturing process, but the octagonal transparent electrode 113a 'may have an advantage in the electric flow characteristic.

The transparent electrode 113a of the intermediate electrode 113 as described above is substantially disposed at the center of the bus electrode 113b and electrically connected to the bus electrode 113b of the intermediate electrode 113. In the transparent electrode 113a of the intermediate electrode 113, the size b of each transparent electrode 113a of the intermediate electrode 113 in the unit discharge cells 170 is each transparent of the pair of sustain electrodes 112. It is formed smaller than the size (c) of the electrodes (131a, 132a).

More specifically, the internal size of the discharge cell 170 corresponding to the longitudinal direction of the intermediate electrode 113 of the transparent electrode 113a of the intermediate electrode 113 is a, and the internal size of the discharge cell 170 ( When the size of the transparent electrode of the intermediate electrode 113 corresponding to a) is b, it is formed according to the formula (1.2 ≦ a / b ≦ 2.4).

If the size (b) of the transparent electrode 113a of the intermediate electrode 113 is formed smaller than the size (c) of the transparent electrodes 131a and 132a of the sustain electrode pair 112 in the unit discharge cell 170 as described above, Since the problem that the luminance is reduced by shielding the transparent electrode of the intermediate electrode 113 is solved to some extent, the luminance is improved than the conventional plasma display panel.

For reference, in the case of reducing the size of the transparent electrode of the intermediate electrode according to the present invention, the experimental measurement data of the degree of brightness enhancement is shown in the table below.

division Measurement result data Transparent electrode size of the intermediate electrode (㎛) 270 260 250 240 230 220 200 190 180 170 160 150 140 130 Luminance (cd / m ² ) 900 910 915 935 940 940 940 960 970 970 980 980 980 980 Driving voltage (V) 164 165 166 167 170 173 173 175 175 177

In the above table, it can be seen that the size (b) of the transparent electrode 113a of the intermediate electrode 113 is preferably 120 to 240 μm. As a result, when the size (a) of the unit discharge cell 170 is 290㎛, it can be seen that the formula (1.2≤a / b≤2.4) can be derived.

Meanwhile, the bus electrode of the plasma display panel of the present invention may be formed in a single layer structure using a metal such as Ag, Al or Cu, but may be formed to have a multilayer structure such as Cr / Al / Cr. Such transparent electrodes and bus electrodes are formed using a photo etching method, a photolithography method, or the like.

The first dielectric layer 115 is formed on the front substrate 111 to fill the sustain electrode pairs 112 and the intermediate electrodes 113. The first dielectric layer 115 may be directly energized between adjacent sustain electrodes 131 and 132 and the intermediate electrode 113 during discharge, and positive or negative electrons may be applied to the sustain electrodes 131 and 132 and the intermediate electrode 113. While preventing direct damage by damaging the electrodes 131, 132, 113, it is formed of a dielectric that can induce charge and accumulate wall charges. Such dielectrics include PbO, B ₂ O ₃ , and SiO ₂ . have.

The protective layer 116 is formed to cover the first dielectric layer 115. The protective layer 116 prevents cations and electrons from colliding with the first dielectric layer 115 during the discharge and damaging the first dielectric layer 115. In addition, the protective layer 116 emits a large amount of secondary electrons during discharge, thereby smoothing plasma discharge. The protective layer 116 performing this function is formed using a material having a high secondary electron emission coefficient and a high visible light transmittance.

As the protective layer 116, a material including MgO is formed on the first dielectric layer as a thin film. The protective layer 116 is mainly formed by sputtering or electron beam deposition after other processes of the upper plate 150 are completed.

On the front surface of the back substrate 121, address electrodes 122 intersecting with the X electrode 131, the Y electrode 132, and the intermediate electrode 113 are disposed in the unit discharge cell 170. The address electrodes 122 are intended to cause an address discharge to facilitate sustain-discharge between the X electrode 131 and the Y electrode 132, and more specifically, serve to lower a voltage for sustain-discharge. . In the above, the address discharge is a discharge occurring between the intermediate electrode 132 and the address electrode 122.

The space formed by the pair of X electrodes 131, Y electrodes 132, and the intermediate electrodes 113 and the address electrodes 122 intersecting the same is formed as a unit discharge cell 170 as one discharge unit. Done.

The second dielectric layer 125 is formed on the rear substrate 121 to fill the address electrode 122. The second dielectric layer 125 is formed as a dielectric that can induce charge while preventing cations or electrons from colliding with the address electrode 122 during discharge and damaging the address electrode 122. Such dielectrics include PbO and B ₂ O ₃ , SiO ₂ and the like.

Red light emission, green light emission, and blue light emission phosphor layers 126 are formed on the entire surface of the second dielectric layer 125 between the partition walls 130 partitioning the discharge cells 170. In addition, red, green, and blue light emitting phosphor layers 126 corresponding to the respective discharge cells are formed on the side surfaces of the partition wall 130.

The phosphor layer 126 has a component that generates ultraviolet light by receiving ultraviolet rays. The red phosphor layer formed in the red discharge cell includes a phosphor such as Y (V, P) O ₄ : Eu, and the green discharge cell. The red light emitting phosphor layer formed on the substrate includes a phosphor such as Zn ₂ SiO ₄ : Mn, and the blue light emitting phosphor layer formed on the blue discharge cell includes a phosphor such as BAM: Eu.

In addition, the discharge cells 180 are filled with a discharge gas in which neon (Ne), xenon (Xe), and the like are mixed, and in the state where the discharge gas is filled as described above, the front and rear substrates 111 and 121 of the substrates are filled. The front substrate and the back substrates 111 and 121 are sealed to each other and joined by a sealing member such as frit glass formed at the edge thereof.

As shown in FIG. 8, the plasma display apparatus 200 including the plasma display panel 100 according to an exemplary embodiment of the present invention includes the above-described plasma display panel 100, an image processor 256, and a logic controller ( 262, an address driver 223, an X driver 224, a Y driver 225, and an M driver 226. In FIG. 8, the X electrodes 131, the Y electrodes 132, and the intermediate electrode 113 forming a plurality of lines are illustrated.

Referring to the drawings, the Y electrodes 132 are spaced apart from each other to one side of the front substrate 111, and are connected to each other at the edge portion. When the plasma display panel 100 is driven, since the same electrical signal is applied to the Y electrodes 132, the Y electrodes 132 are electrically connected in common. Similarly to the Y electrodes 132, the X electrodes 131 are electrically connected in common because common signals are applied. However, since independent signals are applied to the intermediate electrodes 113, the intermediate electrodes 113 extend apart from each other and are connected to the intermediate electrode driver 226.

In the unit discharge cell 170, positions and shapes of the electrodes 113, 122, 131, and 132 may be substantially positioned in the intermediate electrode 113, the address electrode 122, and the X of FIG. 4 to 7. It is the same as the electrode 131 and the Y electrode 132.

The image processing unit 256 converts an external analog image signal into a digital signal to convert an internal image signal, for example, 8 bits of red (R), green (G), and blue (B) image data, a clock signal, vertical and horizontal, respectively. Generate sync signals. The logic controller 262 controls the driving control signals S _A , S _X , and _A according to an internal image signal from the image processor 256. S _Y , S _M ) is generated. The driving control signal S _A is represented by [A ₁ : A _m ], S _x corresponds to [X ₁ : X _n ] in FIG. 1, S _Y corresponds to [Y ₁ : Y _n ] in FIG. 1, and M _x corresponds to [M ₁ in FIG. 1]. ... M _n ]. Therefore, in FIG. 8, reference numeral S _A denotes a drive signal applied to the address electrode 122, S _X denotes a drive signal applied to the X electrode 131, and S _Y denotes a drive signal applied to the Y electrode 132. S _M denotes a drive signal applied to the intermediate electrode 113.

The address driver 223 may include driving control signals S _A , S _X , and _A from the logic controller 262. S _Y , The address driving signal S _A is processed in S _M to generate display data signals, and the generated display data signals are applied to the address electrodes 122. The X driver 224 may drive driving signals S _A , S _X , from the logic controller 262. S _Y , S _M) processes the X driving control signal _(X S) to be applied from the X electrode 131. In addition, the Y driver 225 may drive driving signals S _A , S _X , from the logic controller 262. S _Y , S _M) from the Y driving control signal (to handle the S _Y) is applied to the Y electrodes (132), M driving unit 226 drives the control signal from the logic controller (262), (S _A, S _X, S _Y , S _M) from among processes the M drive control signal (S _M) is applied to the intermediate electrode 113.

Thus, the present invention solves the problem of decreasing the luminance by shielding the transparent electrode of the intermediate electrode in the plasma display panel of the multi-electrode structure, thereby improving the luminance than the conventional plasma display panel.

Plasma display panel according to the present invention as described above, by forming the size of the transparent electrode of the intermediate electrode relatively smaller than the size of the transparent electrode of the sustain electrode to prevent the reduction in brightness due to the shielding of the transparent electrode of the intermediate electrode To provide.

Although a preferred embodiment of the present invention has been described in detail above, those skilled in the art to which the present invention pertains may make various changes without departing from the spirit and scope of the invention as defined in the appended claims. It will be appreciated that modifications or variations may be made. Therefore, changes in the future embodiments of the present invention will not be able to escape the technology of the present invention.

Claims (5)

Back substrate; A front substrate spaced apart from and parallel to the rear substrate; A partition wall disposed between the front substrate and the rear substrate and partitioning discharge cells; Sustain electrode pairs extending across the discharge cells and having X and Y electrodes, respectively; Intermediate electrodes disposed between the paired X and Y electrodes and extending in parallel with the X and Y electrodes; A first dielectric layer formed to cover the sustain electrode pairs and the intermediate electrodes; Address electrodes extending across the discharge cells to intersect the sustain electrode pair and the intermediate electrode in the discharge cell; A second dielectric layer formed to cover the address electrodes; A phosphor layer disposed in the discharge cells; And Includes; discharge gas in the discharge cell; The sustain electrode pairs and the intermediate electrodes each have a bus electrode and a transparent electrode (ITO electrode) electrically connected to the bus electrode, and the size of each transparent electrode of the intermediate electrodes in the discharge cells is the sustain electrode. Is formed smaller than the size of each transparent electrode of the pair, When the internal size of the discharge cell corresponding to the longitudinal direction of the sustain electrode pair and the intermediate electrode is a and the transparent electrode size of the intermediate electrode corresponding to the internal size (a) of the discharge cell is b, A plasma display panel, wherein the transparent electrode of the intermediate electrode is formed to conform to a formula (1.2 ≦ a / b ≦ 2.4). The method of claim 1, The size of the transparent electrode of the intermediate electrode is a plasma display panel, characterized in that 120 ~ 240 ㎛. delete The method according to claim 1 or 2, And the transparent electrode of the intermediate electrode is discontinuously disposed in each unit discharge cell. The method of claim 1, And the transparent electrode of the intermediate electrode is formed in an octagonal shape.

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