KR100787426B1 - Plasma display panel - Google Patents

Abstract

The present invention, the rear substrate and the front substrate spaced apart to face each other; A partition wall disposed between the front substrate and the rear substrate and partitioning discharge cells in which gas discharge occurs; A plurality of discharge electrode pairs extending across the discharge cells and including an X electrode and a Y electrode spaced apart from the discharge cell to interact with each other to generate a gas discharge; A first dielectric layer formed to cover the discharge electrode pairs; M electrodes formed on the first dielectric layer and extending along the discharge electrode pairs and including a transparent electrode and a white bus electrode; A second dielectric layer formed to cover the M electrodes; Address electrodes extending across the discharge cells to intersect the pair of discharge electrodes and the M electrodes in each discharge cell; A third dielectric layer formed to cover the address electrodes; A phosphor layer disposed in the discharge cells; And a discharge gas in the discharge cell. Through the new electrode structure of the present invention, the discharge space can be enlarged to increase the luminous efficiency, and the discharge start voltage can be reduced and the luminance can be prevented from decreasing.

Description

Plasma display panel {Plasma display panel}

1 is a partially cutaway perspective view of a typical plasma display panel.

2 is a partially cutaway perspective view of a plasma display panel according to an exemplary embodiment of the present invention.

3 is a view showing only the front substrate of the plasma display panel according to the present invention.

4 is a cross-sectional view taken along the line A-A of FIG. 2, showing a state in which the upper plate is rotated 90 degrees.

FIG. 5 is a plan view illustrating only electrodes and partition walls formed on the front substrate illustrated in FIG. 2, and illustrates a state in which the first and second dielectric layers are removed.

FIG. 6 is a diagram illustrating a modification of the plasma display panel shown in FIG. 4.

FIG. 7 is a plan view illustrating only a front substrate and electrodes formed thereon, and illustrates a state in which the first and second dielectric layers are removed.

FIG. 8 is a plan view illustrating two X electrode terminal portions formed in FIG. 7.

FIG. 9 is a block diagram illustrating a plasma display device including the plasma display panel of FIG. 3.

FIG. 10 is a waveform diagram of signals applied to electrodes disposed in one discharge cell of a plasma display panel in a unit sub-field.

Explanation of symbols on the main parts of the drawings

100: plasma display panel 111: front substrate

112: sustain electrode pair 113: M electrode

114: first dielectric layer 115: second dielectric layer

116: protective film 121: back substrate

122: address electrode 125: third dielectric layer

126: phosphor 130: partition wall

131: X electrode 132: Y electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a plasma display panel in which the luminous efficiency is increased and the discharge start voltage is reduced.

Recently, a plasma display panel, which is drawing attention as a replacement of a conventional cathode ray tube display device, is discharged after a discharge gas is filled between two substrates on which a plurality of electrodes are formed. The phosphor formed in a predetermined pattern by the ultraviolet rays is excited to obtain a desired image.

The plasma display panel may be classified into a direct current type and an alternating current type according to a discharge type. In the DC plasma display panel, the electrodes are exposed to the discharge space so that the movement of charged particles is directly performed between the corresponding electrodes. In the AC plasma display panel, at least one electrode is covered with a dielectric layer, so that the direct charges of the corresponding electrodes are mutually reduced. The discharge is performed by the electric field of the wall charge instead of the movement of.

In the DC plasma display panel, all electrodes are exposed to a discharge space, and charges are directly transferred between the corresponding electrodes. In the AC plasma display panel, at least one electrode is surrounded by a dielectric layer, and discharge is performed by an electric field of wall charge instead of direct charge transfer between the corresponding electrodes.

In the DC plasma display panel, since the charge is directly transferred between the corresponding electrodes, there is a problem in that the electrode is severely damaged. In recent years, an AC plasma display panel having an AC type, in particular, a three-electrode surface discharge structure is present. This has been generally employed.

The general AC plasma display panel 10 includes an upper plate 50 showing an image to a user and a lower plate 60 coupled in parallel with each other, as shown in FIG. 1. On the front substrate 11 of the upper plate 50, a pair of sustain electrodes 12, which are paired with the X electrode 31 and the Y electrode 32, is arranged, and the pair of sustain electrodes 12 of the front substrate 11 is disposed. On the rear substrate 21 of the lower substrate 60 opposite to the disposed surface, the address electrodes 22 are arranged to intersect the electrodes 31 and 32 of the front substrate 11.

Each of the first dielectric layer 15 and the second substrate is embedded in each of the front substrate 11 having the sustain electrode pairs 12 and the rear substrate 21 provided with the address electrodes 22. Dielectric layer 25 is formed.

A protective film 16 made of MgO is generally formed on the rear surface of the first dielectric layer 15. The front surface of the second dielectric layer 25 maintains a discharge distance and prevents electro-optic crosstalk between discharge cells. The partition 30 is formed. Red, green, and blue phosphors 26 are coated on both sides of the partition wall 30 and on the entire surface of the second dielectric layer 25 on which the partition wall 30 is not formed.

Each of the X electrode 31 and the Y electrode 32 includes transparent electrodes 31a and 32a and bus electrodes 31b and 32b. The space formed by the pair of X electrodes 31 and Y electrodes 32 arranged in this way and the address electrodes 22 intersecting the same form one discharge unit as the unit discharge cells 70.

In the plasma display panel 10 having such a shape, in order to increase the discharge area, the distance between the X electrode 31 and the Y electrode 32 must be arranged far. This is because when the distance between the X electrode 31 and the Y electrode 32 is far, the discharge space is increased and discharge is actively generated. However, when the distance between the X electrode 31 and the Y electrode 32 increases, there is a problem that power consumption increases because the discharge start voltage increases.

 In order to solve the above problems, an object of the present invention is to provide a plasma display panel in which a discharge space is enlarged to increase luminous efficiency, as well as a discharge start voltage is reduced and luminance is improved.

In order to achieve the above object, the present invention

A rear substrate and a front substrate spaced apart to face each other; A partition wall disposed between the front substrate and the rear substrate and partitioning discharge cells in which gas discharge occurs; A plurality of discharge electrode pairs extending across the discharge cells and including an X electrode and a Y electrode spaced apart from each other in the discharge cell to interact with each other to generate a gas discharge; A first dielectric layer formed to cover the discharge electrode pairs; M electrodes formed on the first dielectric layer and extending along the discharge electrode pairs and including a transparent electrode and a white bus electrode; A second dielectric layer formed to cover the M electrodes; Address electrodes extending across the discharge cells to intersect the pair of discharge electrodes and the M electrodes in each discharge cell; A third dielectric layer formed to cover the address electrodes; A phosphor layer disposed in the discharge cells; And a discharge gas in the discharge cell.

In the present invention, the Y electrodes are preferably connected in common at one side of the front substrate.

In addition, in the present invention, the X electrodes are preferably connected in common on one side of the front substrate.

In the present invention, the M electrode is preferably disposed between the paired X electrode and Y electrode.

According to another aspect of the present invention, the present invention provides a rear substrate and a front substrate spaced apart to face each other; A partition wall disposed between the front substrate and the rear substrate and partitioning discharge cells in which gas discharge occurs; M electrodes extending across the discharge cells and having a transparent electrode and a white bus electrode; A first dielectric layer formed to cover the M electrodes; An X electrode and a Y electrode formed on the rear surface of the first dielectric layer so as to extend in parallel to the M electrode, extending across the discharge cell, and spaced apart from each other in the discharge cell to interact with each other to generate a gas discharge. Discharge electrode pairs provided; A second dielectric layer formed to cover the discharge electrode pairs; Address electrodes extending across the discharge cells to intersect the pair of discharge electrodes and the M electrodes in each discharge cell; A third dielectric layer formed to cover the address electrodes; A phosphor layer disposed in the discharge cells; And a discharge gas in the discharge cell.

In the present invention, the Y electrodes are preferably connected in common at one side of the front substrate.

In addition, in the present invention, the X electrodes are preferably connected in common on one side of the front substrate.

In the present invention, the M electrode is preferably disposed between the paired X electrode and Y electrode.

Next, an embodiment of the present invention will be described in detail with reference to the drawings.

2 to 5, a plasma display panel 100 according to an exemplary embodiment of the present invention is shown.

As shown in FIG. 2, the plasma display panel 100 includes a top plate 150 and a bottom plate 160. In detail, the plasma display panel 100 is spaced apart from the rear substrate 121 and the rear substrate 121 and arranged in parallel. Disposed between the front substrate 111, the front substrate 111 and the rear substrate 121, and extending across the partition wall 130 partitioning the discharge cells 170 and the discharge cells 170, X Discharge electrode pairs 112 including electrodes 131 and Y electrodes 132, a first dielectric layer 114 formed to cover the discharge electrode pairs 112, and a rear surface of the first dielectric layer 114. A second dielectric layer 115 formed to cover the M electrode 113, which extends in parallel to the discharge electrode pairs 112, and is formed of only a transparent electrode and a white bus electrode; The address electrodes 122 and the address electrodes 122 extending across the discharge cells 170 so as to intersect with the discharge electrode pairs 112 and the M electrodes 113 in each discharge cell 170. And a discharge gas in the third dielectric layer 115, and discharge cells 170 of the phosphor layer 126 and, and the discharge cells 170 disposed in a formed to cover.

A plurality of discharge electrode pairs 112 are disposed on the front substrate 111. In this case, the front substrate 111 is generally formed of a transparent material mainly made of glass.

3 is a view showing only the front substrate of the plasma display panel according to the present invention. The discharge electrode pair 112 refers to a pair of discharge electrodes 131 and 132 formed on the rear surface of the front substrate 111 to generate sustain discharge, and the discharge electrode pairs 112 are formed on the front substrate 111. It is arranged in parallel at predetermined intervals. One discharge electrode of the pair of discharge electrodes 112 is the X electrode 131, and the other discharge electrode is the Y electrode 132.

Referring to FIG. 4, each of the X electrode 131 and the Y electrode 132 includes transparent electrodes 131a and 132a and bus electrodes 131b and 132b. The transparent electrodes 131a and 132a are formed of a transparent material that is a conductor capable of causing a discharge and does not prevent light emitted from the phosphor 126 from advancing to the front substrate 111. Such a material is indium tin (ITO). oxide). However, transparent conductors such as ITO generally have a high resistance, and thus, when the discharge sustaining electrode is formed only by the transparent electrode, a large voltage drop in the longitudinal direction consumes a lot of driving power and a slow response time. In order to improve, the bus electrodes 131b and 132b made of a metal material and formed in a narrow width are disposed on the transparent electrode. The bus electrode is composed of a black layer (132b ') and a white layer (132b'). A black layer (132b ') is formed on the lower surface of the transparent electrode and a white layer (132b ") on the lower surface of the black layer. Is formed.

The first dielectric layer 114 is formed on the front substrate 111 provided with the discharge electrode pairs 112 to fill the discharge electrode pairs 112. The first dielectric layer 114 is directly energized between the adjacent X electrode 131 and the Y electrode 132 during sustain-discharge, and positive or negative electrons directly collide with the discharge electrodes 131 and 132 to discharge the X electrode 131. And the Y electrode 132, while preventing damage, are formed of a dielectric material capable of inducing charge and accumulating wall charges. Such dielectrics include PbO, B ₂ O ₃ , SiO _2, and the like.

The M electrode 113 is disposed between the paired X electrode 131 and the Y electrode 132. The M electrode 113 is formed on the rear surface of the first dielectric layer 114 and extends in one direction to be parallel to the X electrode 131 and the Y electrode 132. The M electrode 113 is also provided with the transparent electrode 113a and the white bus electrode 113b. Unlike the X electrode 131 and the Y electrode 132, which are discharge electrodes of the M electrode of the present invention, the black electrode is provided only with the white layer 113b without providing the bus electrode with the black layer.

As in the present invention, if three electrodes are present on the front substrate and a bus electrode of a black layer is present on each of the three electrodes, the aperture ratio is reduced and the luminance is lowered. This has the advantage of lowering the discharge start voltage, widening the discharge space and improving the efficiency by using the M electrode, but since the M electrode is located between the X electrode 131 and the Y electrode 132, the black layer In the presence of the bus electrode, it is not preferable because the increase in luminance is lowered.

Therefore, in order to improve such a problem of deterioration of luminance, the bus electrode of the M electrode formed at the center may be formed of only a white layer. FIG. 5 is a plan view showing only electrodes and partition walls formed on the front substrate, and shows a state in which the first and second dielectric layers are removed. Only the white bus electrode is provided in the central M electrode part, and only the X and Y electrodes show the dark part by the black layer.

In addition, the second dielectric layer 115 is formed to fill the M electrodes 113. The second dielectric layer 115 prevents direct conduction between adjacent X electrodes 131, Y electrodes 132, and M electrodes, and cations or electrons directly collide with the M electrodes 113 to prevent the M electrodes ( 113) to inhibit damage. In addition, the second dielectric layer 115 is formed of a dielectric material capable of inducing charge to accumulate wall charges. Such dielectrics include PbO, B ₂ O ₃ , SiO ₂ , and the like, and are the same as the first dielectric layer 114. It is preferable to form using a dielectric.

6 shows a modification of this embodiment. Like reference numerals in the drawings shown above indicate the same members. The plasma display panel 300 according to the modification differs from the embodiment in that the M electrodes 113 ′ covered by the first dielectric layer 114 ′ are formed on the rear surface of the front substrate 111. X electrodes 131 ′ and Y electrodes 132 ′ are disposed on the first dielectric layer 114 ′, and the X electrodes 131 ′ and Y electrodes 132 ′ are disposed by the second dielectric layer 115 ′. Covered. Each of the X electrodes 131 'and the Y electrodes 132' includes transparent electrodes 131a 'and 132a', and bus electrodes 131b 'and 132b' each having a black layer and a white layer. The 113s' are provided with a bus electrode 113b 'having a transparent electrode 113a' and a white layer.

Even in the modified example, since the M electrodes 113 and the Y electrodes 132 in which the terminal portions are formed in the non-image display area of the front substrate are formed by different dielectric layers from each other, the M electrodes 113 and the Y electrodes 132 are different. ) Do not meet each other.

FIG. 7 illustrates an arrangement of electrodes formed on the front substrate 111 in a state in which the first dielectric layer 114 and the second dielectric layer 115 are removed. Referring to the drawings, in the image display area in which an image is displayed, the X electrodes 131, the Y electrodes 132, and the M electrodes 113 are spaced apart from each other and arranged in parallel on the front substrate 111. Here, the X electrodes 131, the Y electrodes 132, and the M electrodes 113 are shown as being disposed at the same level on the front substrate 111, but as described above, the X electrodes 131 and the Y electrodes are disposed. Only the electrodes 132 are formed at the same level, and the M electrodes 113 are formed farther from the front substrate 111 than the X electrodes 131 and the Y electrodes 132.

The bus electrodes 132b of the Y electrode extend to be spaced apart from each other to one side of the front substrate 111, and are connected to each other at the edge portion. Since the same signal is applied to the bus electrodes 132b of the Y electrode when the plasma display panel 100 is driven, the bus electrodes 132b of the Y electrode are electrically connected in common. The portion 132d to which the bus electrodes 132b of the Y electrode are commonly connected is a non-image display area of the plasma display panel, in which a substantial discharge is not generated. A terminal portion 132c is formed in the connecting portion 132d so that the bus electrodes 132b of the Y electrode can be electrically connected by the Y driving portion 225 and the FPCB. Although one terminal portion is illustrated in FIG. 7, two terminal portions 132c ′ may be formed as shown in FIG. 8. The number and formation positions of the terminal portions are not limited to this.

The bus electrodes 131b of the X electrodes are also connected in common because common signals are applied similarly to the bus electrodes 132b of the Y electrodes. That is, they are spaced apart from each other to the other side of the front substrate 111 and are connected to each other in the non-image display area, which is an edge portion. In addition, the terminal portion 131c is formed in the connected portion 131d to be electrically connected by the X driver 224 and the FPCB. Since the terminal portion 131c of the bus electrodes 131b of the X electrodes is exposed to the outside for connection with the FPCB, the first dielectric layer 114 and the second dielectric layer 115 are not formed in this portion.

Since independent signals are applied to the bus electrodes 113b of the M electrodes, the bus electrodes 113b of the M electrodes extend apart from each other. The bus electrodes 113b of the M electrodes extend to one side of the front substrate, and terminal portions 113c are formed at edges of the non-image display area, respectively. These terminal portions 113c are electrically connected by the M electrode driver 226 and the FPCB. Since the terminal portions 113c of the bus electrodes 113b of the M electrodes are exposed to the outside for connection with the FPCB, the first dielectric layer 114 and the second dielectric layer 115 are not formed in this portion.

In addition, a protective film 116 made of MgO is formed on the second dielectric layer 115. The passivation layer 116 prevents cations and electrons from colliding with the second dielectric layer 115 during the discharge, thereby damaging the first dielectric layer 115, has good light transmittance, and emits a large amount of secondary electrons during the discharge.

The address electrode 122 is disposed on the front surface of the rear substrate 121 so as to intersect the X electrode 131 and the Y electrode 132 of the front substrate 111.

The address electrodes 122 are intended to cause an address discharge to facilitate sustain-discharge between the X electrode 131 and the Y electrode 132. More specifically, the address electrodes 122 serve to lower a voltage for sustain-discharge. do. The address discharge is a discharge that occurs between the M electrode 132 and the address electrode 122.

The space formed by the pair of X electrodes 131, Y electrodes 132, and M electrodes arranged in this way, and the address electrodes 122 intersecting the same form one discharge unit as the unit discharge cells 170.

A third dielectric layer 125 is formed on the back substrate 121 provided with the address electrode 122 to fill the address electrode 122. The third dielectric layer 125 is formed as a dielectric capable of inducing charge while preventing cations or electrons from colliding with the address electrode 122 during discharge and damaging the address electrode 122. Such dielectrics include PbO and B ₂ O ₃ , SiO ₂ and the like.

Between the second dielectric layer 115 and the third dielectric layer 125, a partition wall 130 that maintains a discharge distance, partitions red, green, and blue discharge cells, and prevents electro-optical crosstalk between the discharge cells 170. ) Is formed. The partition wall 130 may be not only a matrix form but also a closed partition wall such as a waffle, a matrix, a delta, etc. as well as an open partition wall of various patterns, for example, a stripe or the like, as long as it can form a plurality of discharge spaces. . In addition, the closed partition wall may be formed such that the cross section of the discharge space becomes a polygon, such as a triangle, a pentagon, or a circle, an ellipse, or the like, in addition to the rectangle as in the present embodiment.

Phosphor layers 126 of red, green, and blue are formed on the entire surface of the second dielectric layer 125 between the partition walls 130 partitioning the discharge cells 170. In addition, the phosphor layer 126 is formed on the side surface of the partition wall 130.

The phosphor layer 126 has a component that generates ultraviolet light by receiving ultraviolet rays. The red phosphor layer formed on the red discharge cell includes a phosphor such as Y (V, P) O ₄ : Eu, and the green discharge cell. The red phosphor layer formed at includes a phosphor such as Zn ₂ SiO ₄ : Mn, and the blue phosphor layer formed at the blue discharge cell includes a phosphor such as BAM: Eu.

The discharge cell 170 is filled with a discharge gas such as Ne, He, Xe, and the like and a mixed gas thereof.

As shown in FIG. 9, the plasma display apparatus 200 including the plasma display panel 100 according to an exemplary embodiment of the present invention includes the above-described plasma display panel 100, an image processor 256, and a logic controller. 262, an address driver 223, an X driver 224, a Y driver 225, and an M driver 226.

The image processing unit 256 converts an external analog image signal into a digital signal to convert an internal image signal, for example, 8 bits of red (R), green (G), and blue (B) image data, a clock signal, vertical and horizontal, respectively. Generate sync signals. The logic controller 262 controls the driving control signals S _A , S _X , and _A according to an internal image signal from the image processor 256. S _Y , S _M ) is generated.

The address driver 223 generates the display data signals by processing the address driving signal S _A among the driving control signals S _A and S _S from the logic controller 262 and addresses the generated display data signals. Applied to the electrodes 122. The X driver 224 may drive driving signals S _A , S _X , from the logic controller 262. S _Y , S _M) processes the X driving control signal _(X S) to be applied from the X electrode 131. In addition, the Y driver 225 may drive driving signals S _A , S _X , from the logic controller 262. S _Y , The S _M driving control signal S _Y is processed and applied to the Y electrodes 132, and the M driving unit 226 receives the driving control signals S _A , S _X , and S from the logic controller 262. S _Y , S _M) from among processes the M drive control signal (S _M) is applied to the M electrode 113.

The X electrodes 131 are commonly connected, common driving control signals are applied, and the Y electrodes 132 are also commonly connected, and common driving control signals are applied.

FIG. 10 is a waveform diagram of signals applied to electrodes disposed in one discharge cells of the plasma display panel 200 in a unit sub-field SF. Each unit frame is divided into eight subfields SF ₁ , SF ₂ , SF ₃ , SF ₄ , SF ₅ , SF ₆ , SF ₇ , and SF ₈ to realize time division gray scale display. In addition, each subfield SF is divided into a reset time R, an addressing time A, and a sustain-discharge time S. FIG.

In FIG. 9, S _A denotes a drive signal applied to the address electrode 122, S _X denotes a drive signal applied to the X electrode 131, and S _Y denotes a drive signal applied to the X electrode 132. S _M indicates a drive signal applied to the M electrode 113.

Referring to the drawing, at the resetting time R of the unit subfield SF, the respective discharge cells 170 become uniform and at the same time suitable for addressing to be performed in the next step. At this time, the ground voltage, which is the first voltage V _G , is applied to the address electrode 122 and the Y electrode 132. The voltage applied to the M electrode 113 first rises to the second voltage V _SET + V _S and then decreases to the first voltage V _G. At this time, the first voltage V _G is first applied to the X electrode 131, and while the M electrode 113 is reduced from the second voltage V _SET + V _S to the first voltage V _G , the first voltage V _G is applied. A sustain voltage of 3 voltages V _S is applied.

At each addressing time A, display data pulses of the address voltage V _A are applied to the address electrode 122, and the M electrode biased with the scan voltage V _SCAN lower than the third voltage V _S. The scan pulse of the first voltage V _G is applied to 113. Accordingly, when high-level display data pulses are applied while the scan pulse is applied, wall charges are formed by the address discharge. That is, as a result of the address discharge, negative wall charges are accumulated on the X electrode 131, and positive wall charges are accumulated on the M electrode 113 and the Y electrode 132. However, although the scan pulse is applied to the M electrode 113 in FIG. 10, since the scan pulse is not applied to the discharge cells that do not require address discharge, wall charges are not formed in the discharge cell.

At each sustain-discharge time S, sustain-discharge pulses are alternately applied to all the X electrodes 131 and the Y electrodes 132, so that sustain discharges are generated when wall charges are formed at the corresponding addressing time A. FIG. Cause At this time, the M electrode 131 and the address electrode 122 are biased with the third voltage V _S and the first voltage V _G , respectively.

However, when the above sustain-discharge is started, the first voltage V _G is applied to the X electrode 131 in which the negative wall charges are accumulated, and the third voltage in the M electrode 113 in which the positive wall charges are accumulated. Since V _S ) is applied, discharge starts between the X electrode 131 and the M electrode 113 which are relatively close in distance. Therefore, since the discharge starts between the electrodes arranged at a close distance, the discharge start voltage is reduced.

After the discharge occurs between the X electrode 131 and the M electrode 113, the discharge region is extended to the Y electrode 132, so that sustaining-discharge is actively performed between the X electrode 131 and the Y electrode 132. Occurs. In particular, when the distance between the X electrode 131 and the Y electrode 132 is disposed far, since the discharge space is increased, the discharge is actively generated, and ultimately the luminous efficiency is increased. Therefore, due to the sustain-discharge between the X electrode 131, the M electrode 113, and the Y electrode 132, the discharge start voltage is reduced and the light emission efficiency is increased.

The luminance of the plasma display panel is proportional to the length of the sustain-discharge time S occupied in the unit frame. The length of the sustain-discharge time S occupied in the unit frame is 255T (T is the unit time). Therefore, it can be displayed in 256 gray levels, including the case where it is not displayed once in a unit frame.

Here, the first maintenance of the sub-fields (SF ₁₎ - the discharge time, the time (1T) corresponding to ^20, the second holding of the sub-field (SF ₂₎ - Time to discharge time corresponding to the 2 ¹ (2T) The time 4T corresponding to 2 ² in the sustain-discharge time of the third subfield SF ₃ , and the time 8T corresponding to 2 ³ in the sustain-discharge time of the fourth subfield SF ₄ . In the sustain-discharge time of the fifth subfield SF ₅ , a time 16T corresponding to 2 ⁴ and a sustained-discharge time of the sixth subfield SF ₆ , 32T correspond to 2 ⁵ . This time 64T corresponds to 2 ⁶ in the sustain-discharge time of the seventh subfield SF ₇ , and the time 128T corresponds to 2 ⁷ in the sustain-discharge time of the eighth subfield SF ₈ . Are set respectively.

Accordingly, if the subfield to be displayed among the eight subfields is appropriately selected, the display of 256 gray levels can be performed including all zero (zero) gray levels that are not displayed in any of the subfields.

The plasma display panel according to the present invention has the following effects.

First, since the discharge is initiated between the M electrode disposed between the X electrode and the Y electrode and the X electrode, the discharge start voltage is reduced. In addition, since the distance between the X electrode and the Y electrode can be arranged far, the discharge space is increased, the discharge occurs smoothly. Therefore, luminous efficiency is improved.

Second, the M electrode in the center portion of the discharge gap where the luminance is most generated is composed of only the white layer to improve the luminance decrease.

Third, since the M electrodes and the Y electrodes are formed by different layers from each other, the terminal portions may be formed without interfering with each other.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

Claims (8)

delete delete delete delete A rear substrate and a front substrate spaced apart to face each other; A partition wall disposed between the front substrate and the rear substrate and partitioning discharge cells in which gas discharge occurs; M electrodes extending across the discharge cells and having a transparent electrode and a white bus electrode formed on the transparent electrode with a narrower width than the transparent electrode; A first dielectric layer formed to cover the M electrodes; An X electrode and a Y electrode formed on the rear surface of the first dielectric layer so as to extend in parallel to the M electrode, extending across the discharge cell, and spaced apart from each other in the discharge cell to interact with each other to generate a gas discharge. Discharge electrode pairs provided; A second dielectric layer formed to cover the discharge electrode pairs; Address electrodes extending across the discharge cells to intersect the pair of discharge electrodes and the M electrodes in each discharge cell; A third dielectric layer formed to cover the address electrodes; A phosphor layer disposed in the discharge cells; And And a discharge gas in the discharge cell. The method of claim 5, And the Y electrodes are commonly connected to one side of the front substrate. The method of claim 5, And the X electrodes are commonly connected at one side of the front substrate. And the M electrode is disposed between the paired X and Y electrodes.

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