KR100641522B1 - Method for fabricating mim capacitor - Google Patents

Method for fabricating mim capacitor Download PDF

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KR100641522B1
KR100641522B1 KR1020020054552A KR20020054552A KR100641522B1 KR 100641522 B1 KR100641522 B1 KR 100641522B1 KR 1020020054552 A KR1020020054552 A KR 1020020054552A KR 20020054552 A KR20020054552 A KR 20020054552A KR 100641522 B1 KR100641522 B1 KR 100641522B1
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film
mim capacitor
dielectric
lower electrode
etching
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KR20040022952A (en
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이대근
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7687—Thin films associated with contacts of capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers

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  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 누설 전류 발생을 방지시키는 MIM 커패시터 제조방법에 관한 것이다. 즉, 본 발명은 MIM 구조 커패시터 제조시 유전체와 하부 전극층 측벽을 절연물질로 도포함으로써, 후속 공정에서 상부 전극용으로 사용되는 질화 타이타늄막 식각시 발생되는 금속 성분의 부산물들이 MIM 커패시터의 측면에 부착된다 할지라도, 상기 MIM 커패시터의 유전체와 하부 전극층 측벽에 도포된 절연물질 위에 부착되어 누설전류가 원천적으로 방지되는 이점이 있다.The present invention relates to a method of manufacturing a MIM capacitor that prevents leakage current generation. That is, the present invention applies the dielectric and the lower electrode layer sidewalls as an insulating material in the manufacture of the MIM structure capacitor, whereby by-products of metal components generated during etching of the titanium nitride film used for the upper electrode in the subsequent process are attached to the side of the MIM capacitor. However, there is an advantage that the leakage current is fundamentally prevented by being attached on the dielectric material of the MIM capacitor and the insulating material applied to the sidewalls of the lower electrode layer.

Description

엠.아이.엠 커패시터 제조 방법{METHOD FOR FABRICATING MIM CAPACITOR}M.I.M capacitor manufacturing method {METHOD FOR FABRICATING MIM CAPACITOR}

도 1a 내지 도 1d는 종래 MIM 커패시터 제조방법을 도시한 공정 수순도,1a to 1d is a process flowchart showing a conventional MIM capacitor manufacturing method,

도 2는 종래 MIM 커패시터 측벽에 금속 성분의 부산물이 증착된 예시도, 2 is an exemplary diagram in which a by-product of a metal component is deposited on a sidewall of a conventional MIM capacitor;

도 3a 내지 도 3e는 본 발명의 실시 예에 따른 MIM 커패시터 제조방법을 도시한 공정 수순도,3A to 3E are process flowcharts illustrating a method of manufacturing a MIM capacitor according to an embodiment of the present invention;

도 4는 본 발명의 실시 예에 따른 MIM 커패시터 측벽에 금속 성분의 부산물이 증착된 예시도.4 is an exemplary diagram in which a by-product of a metal component is deposited on a sidewall of a MIM capacitor according to an exemplary embodiment of the present invention.

본 발명은 반도체 소자의 금속-절연체-금속(Metal-Insulator-Metal: MIM) 구조를 가지는 MIM 커패시터 제조방법에 관한 것으로, 특히 누설 전류(Leakage Current) 발생을 방지시키는 MIM 커패시터 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a MIM capacitor having a metal-insulator-metal (MIM) structure of a semiconductor device, and more particularly, to a method of manufacturing a MIM capacitor that prevents leakage current.

통상적으로 MIM 커패시터라함은 절연층을 사이에 두고 양 극판으로 알루미늄 등과 같은 금속패턴을 사용하는 커패시터를 의미하는 것으로, 상부전극이나 하부전극의 일부 또는 전체를 폴리 실리콘으로 구성하고 있는 종래 커패시터와는 달리, 저전압에서도 구동이 가능하며, 셀 면적에 비해 높은 커패시턴스 특성을 가지고 있 어 고집접화 반도체 소자에 채용되고 있다.In general, the MIM capacitor means a capacitor using a metal pattern such as aluminum as an anode plate with an insulating layer interposed therebetween. Unlike a conventional capacitor in which part or all of an upper electrode or a lower electrode is made of polysilicon, In addition, it can be driven even at low voltage, and has a high capacitance characteristic compared to the cell area, so it is employed in highly integrated semiconductor devices.

도 1a 내지 도 1d는 종래 MIM 커패시터 제조 공정 수순을 도시한 것으로, 이하 상기 도 1a 내지 도 1d를 참조하여 종래 MIM 커패시터의 제조공정을 설명하면, 1A to 1D illustrate a conventional MIM capacitor manufacturing process. Hereinafter, a manufacturing process of a conventional MIM capacitor will be described with reference to FIGS. 1A to 1D.

먼저 도 1a에서와 같이 MIM구조를 위해 금속층(100)위에 질화 타이타늄막(TiN)(102), 질화 실리콘막(SiN)(104), 질화 타이타늄막(TiN)(106)을 차례로 적층시켜 MIM구조를 형성시킨다. 이때 상기 금속층(100)은 4000∼6000Å 두께로 형성되고, 하부 전극용 질화 타이타늄막(102)은 500∼1000Å 두께로 형성되며, 유전체 용 질화 실리콘막(104)은 400∼1000Å 두께로 형성된다. 또한 상부 전극용 질화 타이타늄막(106)은 1000∼1500Å 두께로 형성된다. First, as illustrated in FIG. 1A, a titanium nitride film (TiN) 102, a silicon nitride film (SiN) 104, and a titanium nitride film (TiN) 106 are sequentially stacked on the metal layer 100 for the MIM structure. To form. In this case, the metal layer 100 is formed to have a thickness of 4000 to 6000 GPa, the titanium nitride film 102 for the lower electrode is formed to have a thickness of 500 to 1000 GPa, and the silicon nitride film 104 for the dielectric is formed to have a thickness of 400 to 1000 GPa. In addition, the titanium nitride film 106 for the upper electrode is formed to have a thickness of 1000 to 1500 kPa.

이어 도 1b에서와 같이 상부 전극용 질화 타이타늄막(106) 위에 포토레지스트(Photo-resist)(108)를 증착시킨 후, MIM커패시터 형성 위치에 증착된 포토레지스트를 포토리소그라피(Photo-lithography) 공정 및 식각 공정을 통하여 패터닝시킨다. Subsequently, the photoresist 108 is deposited on the titanium nitride film 106 for the upper electrode as shown in FIG. 1B, and then the photoresist deposited at the MIM capacitor formation position is subjected to a photo-lithography process and Patterning is performed through an etching process.

그리고 도 1c 및 도 1d에서와 같이 상기 패터닝된 포토레지스트(108)를 마스크로하여 상기 MIM구조 반도체 기판을 식각하여 MIM 커패시터를 형성시킨다. 이때 상기 MIM 식각은 후공정인 비아 식각을 하부 질화 타이타늄 층위에서 멈출 것인지, 금속층위에서 멈출 것인지에 따라 상기 도 1c 및 도 1d에서와 같은 프로파일로 형성할 수 있게 된다.1C and 1D, the MIM structure semiconductor substrate is etched using the patterned photoresist 108 as a mask to form a MIM capacitor. In this case, the MIM etching may be formed in a profile as shown in FIGS. 1C and 1D according to whether the via etching, which is a post-process, is stopped on the lower titanium nitride layer or the metal layer.

그러나 상기한 바와 같은 종래 MIM 커패시터 제조공정에서는 누설전류 방지를 위해 1차적으로 MIM식각시 절연체 위에서 식각을 멈추는 방법이 있으나, 절연체 의 두께가 1000Å 미만으로 얇기 때문에 MIM커패시터의 크기가 분할되어 있을 경우 웨이퍼내에서의 식각율의 차이에 의해 부분적으로 하부 질화 타이타늄막이 오픈되어 누설전류가 발생하는 문제점이 있으며, 또한 도 2에서 보여지는 바와 같이 질화 타이타늄막 식각시 발생되는 금속 성분의 부산물(By-product)들(110)이 절연체인 질화막의 측면에 증착되어 커패시터에 전원이 공급되지 않는 경우에도 자연적으로 커패시터가 형성되어 누설 전류가 발생하는 문제점이 있었다.However, in the conventional MIM capacitor manufacturing process as described above, there is a method of stopping the etching on the insulator during the MIM etching to prevent leakage current. However, since the thickness of the insulator is thinner than 1000 mW, the wafer is divided when the size of the MIM capacitor is divided. Due to the difference in the etching rate in the inside, the lower titanium nitride film is partially opened and a leakage current is generated, and as shown in FIG. 2, a by-product of a metal component generated during etching of the titanium nitride film is shown. Even if the field 110 is deposited on the side of the nitride film which is an insulator, a capacitor is naturally formed and a leakage current is generated even when no power is supplied to the capacitor.

따라서, 본 발명의 목적은 누설 전류 발생을 방지시키는 MIM 커패시터 제조방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a MIM capacitor to prevent the occurrence of leakage current.

상술한 목적을 달성하기 위한 본 발명은 MIM 커패시터 제조방법에 있어서, (a)금속막 위에 하부 전극용 금속물질막과 유전체용 절연물질막을 순차적으로 증착시키는 단계와; (b)상기 하부 전극용 금속물질막과 유전체용 절연물질막을 MIM 커패시터 패턴으로 식각시키는 단계와; (c)상기 하부 전극막과 유전체막을 절연물질로 도포한 후, 상기 유전체막이 드러날 때까지 에치백하는 단계와; (d)상기 유전체용 절연물질막위에 상부 전극용 금속물질막을 증착시키는 단계와; (e)상기 상부 전극용 금속물질을 MIM 커패시터 패턴으로 식각시켜 MIM 커패시터를 형성시키는 단계;를 포함하는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of manufacturing a MIM capacitor, comprising the steps of: (a) sequentially depositing a lower electrode metal material film and a dielectric insulating material film on a metal film; (b) etching the lower electrode metal material layer and the dielectric insulating material layer with a MIM capacitor pattern; (c) coating the lower electrode film and the dielectric film with an insulating material and then etching back until the dielectric film is exposed; (d) depositing an upper electrode metal material film on the dielectric insulating material film; (e) forming a MIM capacitor by etching the upper electrode metal material in a MIM capacitor pattern.

이하, 첨부된 도면을 참조하여 본 발명에 따른 바람직한 실시 예의 동작을 상세하게 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the operation of the preferred embodiment according to the present invention.

도 3a 내지 도 3e는 본 발명의 실시 예에 따른 누설 전류를 방지하는 MIM 커패시터 제조 공정 수순을 도시한 것이다. 이하 상기 도 3a 내지 도 3e를 참조하여 본 발명의 MIM 커패시터 제조공정을 상세히 설명하기로 한다.3A to 3E illustrate a MIM capacitor manufacturing process procedure for preventing leakage current according to an exemplary embodiment of the present invention. Hereinafter, the MIM capacitor manufacturing process of the present invention will be described in detail with reference to FIGS. 3A to 3E.

먼저 도 3a에서와 같이 MIM구조를 위해 금속층(300)위에 하부 전극용 질화 타이타늄막(302)과 유전체용 질화 실리콘막(304)을 순차적으로 적층시키고, MIM 커패시터가 형성될 위치에 포토레지스트를 패터닝 형성시킨 후, 패터닝된 포토레지스트를 마스크로 하여 상기 질화막과 하부 전극용 질화 타이타늄막을 차례로 식각시킨다. First, as shown in FIG. 3A, the lower electrode titanium nitride film 302 and the dielectric silicon nitride film 304 are sequentially stacked on the metal layer 300 for the MIM structure, and the photoresist is patterned at the position where the MIM capacitor is to be formed. After the formation, the nitride film and the titanium nitride film for the lower electrode are sequentially etched using the patterned photoresist as a mask.

이어 도 3b에서와 같이 상기 식각 형성된 MIM구조위에 옥사이드(Oxide), 나이트라이드(Nitride), 폴리(Poly) 등과 같은 절연물질막(306)을 도포한 후, 도 3c에서와 같이 유전체용 질화 실리콘막이 들어날때까지 에치백(Etch-back)시킨다.Subsequently, as shown in FIG. 3B, an insulating material film 306 such as oxide, nitride, poly, or the like is coated on the etched MIM structure, and then a silicon nitride film for dielectric is formed as shown in FIG. 3C. Etch back until you come in.

그리고 도 3d에서와 같이 측벽에 절연체가 형성된 상기 MIM구조위에 상부 전극용 질화 타이타늄막(308)을 증착시킨 후, MIM커패시터가 형성될 위치에 포토레지스트(310)를 패터닝 형성시킨다. As shown in FIG. 3D, the titanium nitride film 308 for the upper electrode is deposited on the MIM structure having the insulator formed on the sidewall, and then the photoresist 310 is patterned at the position where the MIM capacitor is to be formed.

이어 도 3e에서와 같이 상기 패터닝된 포토레지스트(310)를 마스크로하여 상기 MIM 커패시터 형성 위치에 증착된 질화 타이타늄막외에 다른 영역에 증착된 질화 타이타늄막을 식각함으로써, MIM 커패시터를 형성시키게 된다. Subsequently, as shown in FIG. 3E, the patterned photoresist 310 is used as a mask to etch the titanium nitride film deposited in another region in addition to the titanium nitride film deposited at the MIM capacitor formation position, thereby forming a MIM capacitor.

이에 따라 도 4에서 보여지는 바와 같이 질화 타이타늄막 식각시 발생되는 금속 성분의 부산물들(310)이 MIM 커패시터의 측면에 부착된다 할지라도 TEOS위에 부착되기 때문에 누설전류가 원천적으로 방지되게 된다.Accordingly, as shown in FIG. 4, even though the by-products 310 of the metal component generated during the titanium nitride film etching are attached to the side of the MIM capacitor, leakage current is fundamentally prevented because they are attached to the TEOS.

한편 상술한 본 발명의 설명에서는 구체적인 실시 예에 관해 설명하였으나, 여러 가지 변형이 본 발명의 범위에서 벗어나지 않고 실시될 수 있다. 따라서 발명의 범위는 설명된 실시 예에 의하여 정할 것이 아니고 특허청구범위에 의해 정하여져야 한다.Meanwhile, in the above description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the invention should be determined by the claims rather than by the described embodiments.

이상에서 설명한 바와 같이, 본 발명은 MIM 구조 커패시터 제조시 유전체와 하부 전극층 측벽을 절연물질로 도포함으로써, 후속 공정에서 상부 전극용으로 사용되는 질화 타이타늄막 식각시 발생되는 금속 성분의 부산물들이 MIM 커패시터의 측면에 부착된다 할지라도, 상기 MIM 커패시터의 유전체와 하부 전극층 측벽에 도포된 절연물질 위에 부착되어 누설전류가 원천적으로 방지되는 이점이 있다.As described above, the present invention is applied to the dielectric and the lower electrode layer sidewalls as an insulating material in the manufacture of the MIM structure capacitor, so that by-products of the metal components generated during the etching of the titanium nitride film used for the upper electrode in the subsequent process of the MIM capacitor Although attached to the side, it is advantageous to adhere to the dielectric material of the MIM capacitor and the insulating material applied to the sidewalls of the lower electrode layer to prevent leakage current.

Claims (7)

금속-절연체-금속 구조를 가지는 커패시터 제조 방법에 있어서,In the capacitor manufacturing method having a metal-insulator-metal structure, (a)금속막 위에 하부 전극용 금속물질막과 유전체용 절연물질막을 순차적으로 증착시키는 단계와;(a) sequentially depositing a lower electrode metal material film and a dielectric insulating material film on the metal film; (b)상기 하부 전극용 금속물질막과 유전체용 절연물질막을 MIM 커패시터 패턴으로 식각시키는 단계와;(b) etching the lower electrode metal material layer and the dielectric insulating material layer with a MIM capacitor pattern; (c)상기 하부 전극막과 유전체막을 절연물질로 도포한 후, 상기 유전체막이 드러날 때까지 에치백하는 단계와;(c) coating the lower electrode film and the dielectric film with an insulating material and then etching back until the dielectric film is exposed; (d)상기 유전체용 절연물질막위에 상부 전극용 금속물질막을 증착시키는 단계와;(d) depositing an upper electrode metal material film on the dielectric insulating material film; (e)상기 상부 전극용 금속물질을 MIM 커패시터 패턴으로 식각시켜 MIM 커패시터를 형성시키는 단계;를 포함하는 것을 특징으로 하는 MIM 커패시터 제조 방법.(e) etching the upper electrode metal material with a MIM capacitor pattern to form a MIM capacitor. 제1항에 있어서,The method of claim 1, 상기 (c)단계에서, 상기 에치백후, 상기 MIM 커패시터의 하부 전극막과 유전체막 측벽에는 상기 절연물질이 도포되어 잔존하게 되는 것을 특징으로 하는 MIM 커패시터 제조방법.In the step (c), after the etch back, the insulating material is applied to the lower electrode film and the sidewall of the dielectric film of the MIM capacitor, characterized in that the remaining. 제1항에 있어서,The method of claim 1, 상기 (b)단계는, (b1)상기 절연물질막위에 포토레지스트막을 증착시키는 단계와;Step (b) comprises the steps of: (b1) depositing a photoresist film on the insulating material film; (b2)상기 포토레지스트막을 포토리소그라피 공정 및 식각 공정을 통해 패터닝시키는 단계와;(b2) patterning the photoresist film through a photolithography process and an etching process; (b3)상기 패터닝된 포토레지스트를 마스크로 하여 상기 유전체용 절연물질막 과 하부 전극용 금속물질을 식각하여 MIM 커패시터의 하부 전극과 유전체를 패턴을 형성시키는 단계;를 포함하는 것을 특징으로 하는 MIM 커패시터 제조 방법.(b3) etching the dielectric insulating film and the lower electrode metal material by using the patterned photoresist as a mask to form a pattern between the lower electrode and the dielectric of the MIM capacitor; Manufacturing method. 제1항에 있어서,The method of claim 1, 상기 (e)단계는, (e1)상기 상부 전극용 금속물질막위에 포토레지시트막을 증착시키는 단계와;The step (e) may include: (e1) depositing a photoresist film on the metal film for the upper electrode; (e2)상기 포토레지스트막을 포토리소그라피 공정 및 식각 공정을 통해 패터닝시키는 단계와;(e2) patterning the photoresist film through a photolithography process and an etching process; (e3)상기 패터닝된 포토레지스트를 마스크로 하여 상기 금속물질막을 식각하여 MIM 커패시터의 상부 전극을 패턴 형성시키는 단계;를 포함하는 것을 특징으로 하는 MIM 커패시터 제조 방법.(e3) etching the metal material layer using the patterned photoresist as a mask to form a pattern on the upper electrode of the MIM capacitor. 제1항에 있어서,The method of claim 1, 상기 상/하부 전극용 금속물질막은, 질화 타이타늄(TiN)으로 형성되는 것을 특징으로 MIM 커패시터 제조 방법.The metal material film for the upper / lower electrodes is formed of titanium nitride (TiN). 제1항에 있어서,The method of claim 1, 상기 유전체용 절연물질막은, 질화 실리콘(SiN)으로 형성되는 것을 특징으로 하는 MIM 커패시터 제조방법.The dielectric insulating film for the dielectric, characterized in that formed of silicon nitride (SiN) MIM capacitor manufacturing method. 제1항에 있어서,The method of claim 1, 상기 (c)단계에서, 상기 하부 전극막과 유전체막을 도포하는 절연물질은, 옥사이드(Oxide), 나이트라이드(Nitride), 폴리(Poly) 중 어느 하나로 형성되는 것을 특징으로 하는 MIM 커패시터 제조방법.In the step (c), the insulating material for applying the lower electrode film and the dielectric film, MIM capacitor manufacturing method, characterized in that formed of any one of (Oxide), nitride (Nitride), poly (Poly).
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