KR100311034B1 - Method for manufacturing capacitor of semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a capacitor of a semiconductor device is provided to be capable of preventing the fatigue phenomenon and the generation of an oxide layer at the sidewall of a storage node by using a lower electrode. CONSTITUTION: An insulating layer(42) having contact holes, is formed on a substrate(30). A spacer(44) is formed at both sidewalls of the contact hole. A conductive layer(48) is formed in the contact hole. A storage node pattern is formed at the contact hole region by sequentially depositing and patterning an adhesion layer(50) and a diffusion barrier(52) on the entire surface of the resultant structure. After depositing a platinum layer on the storage node pattern, a lower electrode(54) is formed by carrying out an etch-back process at the platinum layer. Then, a dielectric layer(56) and an upper electrode(58) are sequentially deposited on the resultant structure.

Description

Capacitor Manufacturing Method of Semiconductor Device

The present invention relates to a method for manufacturing a capacitor of a semiconductor device, and more particularly, to a method for manufacturing a capacitor using a high dielectric film.

As circuits become more integrated, capacitor charge charges in memory cells are reduced, and memory cell areas are becoming smaller. Therefore, the spacing between the elements constituting the circuit becomes relatively narrow, and accordingly, the technique of constituting the elements is also becoming more complicated. Accordingly, obtaining a capacitor with small but sufficient capacity has become one of the most important factors for the development of more advanced highly integrated semiconductor devices. According to such a demand, various methods for increasing the capacity of a capacitor of a memory cell have been proposed, and many kinds of capacitors have appeared, but the basic structure for forming the capacitor is the same.

The structure of a capacitor in a memory cell is based on a metal insulator semiconductor (MIS) composed of a lower electrode and a dielectric upper electrode. With the integration of circuits, the space occupied by capacitors in cells has become smaller, which limits the effective area, spacing, and dielectric constant of the capacitors. The smaller the spacing of the three components of the capacitor increases the capacity of the capacitor. The spacing is closely related to the nature of the dielectric inserted between the plates. The main factors limiting the spacing are the leakage current and breakdown voltage of the dielectric. For a given dielectric film thickness, the smaller the leakage current, the larger the breakdown voltage, the better the dielectric.

The effective area of the capacitor is proportional to the capacity but the area is reduced as the cell shrinks. Therefore, various methods for increasing the effective area within the limited area have been proposed and planar, trench, stack, hemisphere, pin and cylinder according to the method. Various types of capacitors have emerged, including molds and their complex types. The dielectric of the capacitor is closely related to the plate gap and the effective area of the capacitor. The larger the dielectric constant, the thinner the thickness, the less the leakage current and the larger the breakdown voltage, the smaller the space occupied by the capacitor in the memory cell. Such a dielectric can increase the capacitance of the capacitor and can make the memory cell smaller. Therefore, high dielectric constant is one of the indispensable elements for high integration of semiconductor circuits.

Representative dielectric materials having a large dielectric constant include tantalum pentoxide (Ta ₂ O ₅ ), titanium strontium trioxide (SrTiO ₃ : hereinafter referred to as STO), and barium titanstrontium trioxide [(BaSr) TiO ₃ : hereinafter referred to as BST]. have. Phenol pentoxide has a problem that the leakage current is large and the breakdown voltage is small in the thin film state. The STO and BST have a very high dielectric constant of about 300-600, which makes them suitable for semiconductor capacitors. In the future, STO and BST are expected to be able to cope with process simplification of capacitors and highly integrated semiconductor devices beyond MDRAM.

However, when using a high-k dielectric such as STO or BST, polycrystalline silicon cannot be used as an upper electrode of a storage node, and platinum (Pt), which does not oxidize well, must be used. The use of platinum (Pt) requires a series of layers to prevent diffusion and adhesion of silicon or oxygen. In case of using BST, oxide film (SiO2) is generated by direct contact between diffusion prevention layer and adhesion layer and BST, which causes weak contact area and leakage current.

Recently, a paper on capacitors using BST was published at the 1994 Symposium on Very Large Scale ICs (VLSIs). (Reference: A Memory Capacitor with Ba _x Sr _1-x TiO ₃ (BST) Film for Advanced DRAM) According to the above paper, silicide is formed by Si-Pt reaction generated during annealing after capacitor manufacturing. To prevent this, a diffusion barrier layer was used. In addition, in order to remove the reaction due to the direct contact between the BST, the diffusion barrier layer and the adhesion layer, an oxide film (CVDSiO ₂ ) by chemical vapor deposition was formed on the sidewall of the storage node. A capacitor manufacturing method using the BST will be described in detail with reference to the accompanying drawings.

1A to 1F are diagrams showing step-by-step steps of a capacitor manufacturing method using a conventional technique.

1A illustrates the step of forming the pad polysilicon. Specifically, a well (1) is formed on a silicon substrate (not shown), and then an isolation region 3 is formed to prevent contact with an adjacent device. The gate electrode 5 is formed on the resultant. A thin insulator 7 is deposited on the entire surface of the gate electrode. Subsequently, an insulating layer is deposited and patterned on the resultant to form an insulating film having the first contact hole 8. Subsequently, pad polysilicon 9 is formed in the first contact hole.

1B illustrates a step of forming a second contact hole. Specifically, brophosposilicate glass (hereinafter referred to as BPSG: BPSG) on the resultant of FIG. 1A is deposited and planarized to prevent leakage current. In order to form the second contact hole 13, a photoresist (not shown) is applied and patterned on the insulating layer. The BPSG 11 exposed by the patterning is etched to the pad polysilicon 9 interface.

1C shows a step of forming a conductive layer. Specifically, after removing the photoresist, a nitride film is deposited thinly in the second contact hole 13 by using LPCVD. Subsequently, the resultant is dry-etched as it is, and then planarized to form a spacer 15 on the sidewall of the second contact hole 13. The spacer 15 is to prevent the consumption of BPSG during the cleaning process in the process of forming the conductive layer, which is the next process.

After depositing about 3000 GPa of polysilicon into the second contact hole 13, n ⁺ ions are implanted to form a conductive layer 17.

1D illustrates a step of forming the lower electrode. Specifically, the entire surface of the insulating film and the conductive layer is etched back, and then the adhesion layer 19, the diffusion barrier layer 21, and the lower electrode 23 are sequentially deposited on the insulating film and the conductive layer. Titanium / titanium nitride (Ti / TiN) or titanium / titanium nitride / tantalum (Ti / TiN / Ta) or the like is used as the adhesion layer 19 and the diffusion barrier layer 21, and the lower electrode 23 is used. Use platinum (Pt). Subsequently, the lower electrode 23 is deposited on the diffusion barrier layer 21 at 1000-2000 mW using the sputter deposition method.

1E shows a step of depositing a high dielectric film. Specifically, a photoresist is applied on the lower electrode 23, and then a storage polymask is patterned. The lower electrode 23, the diffusion barrier layer 21, and the adhesion layer 19 other than the node are removed by the patterning. Subsequently, the BST film 25 is deposited using a metal organic chemical vapor deposition (MOCVD) method, which is a vapor phase epitaxial method using an organic metal compound as a raw material. As a result, the BST film 25 is deposited on the upper and sidewalls of the lower electrode 23 and the sidewalls of the adhesion layer 19 and the diffusion barrier layer 21.

1F illustrates a step of depositing an upper electrode. Specifically, the upper electrode 27 is deposited on the BST film 25 by sputtering. As a finishing step, a photoresist is deposited on the resultant, and by using a photolithography process, platinum (Pt) and BST other than cells are etched and removed, and photoresist is removed. Subsequently, a thin film of SiO ₂ is applied using a plasma-enhanced chemical vapor deposition (hereinafter referred to as PECVD) method, the BPSG is covered and planarized, and a contact metal is formed to complete the capacitor.

In the capacitor manufacturing method of the semiconductor device using the prior art, this part is weak by forming the oxide film (SiO ₂ ) by directly contacting the BST layer 25 with the diffusion barrier layer 21 and the adhesion layer 19 on the sidewall of the storage node. So that leakage current is generated. In addition, when an oxide spacer (SiO ₂ spacer) is used to prevent the diffusion barrier layer 21 and the adhesion layer 19 from being in direct contact with the BST layer 25, the weakening of the portion may be prevented. The addition of one dielectric layer has the same effect as the insertion of another dielectric material into the capacitor. As a result, the equivalent oxide film thickness is increased, resulting in a reduction in the capacity of the capacitor. In particular, the dielectric capacitance of the sidewall portion is lost, and in the high-density semiconductor device having a gigabit level, the distance between the storage node and the node is not wide enough to attach the oxide spacer.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a capacitor of a semiconductor device in which a lower electrode is deposited to sidewalls of an adhesion layer and a diffusion barrier layer in order to solve the above problems.

The present invention to achieve the above object,

Forming an insulating film having a contact hole on the substrate;

Forming a spacer on a sidewall of the contact hole;

Forming a conductive layer in the contact hole;

Depositing and patterning an adhesion layer and a diffusion barrier layer on the entire surface of the insulating layer and the conductive layer to planarize the storage node pattern in the contact hole region;

Depositing platinum on the storage node pattern and etching-back to form a lower electrode;

Depositing a high dielectric film on the lower electrode, and

It provides a method of manufacturing a capacitor of a semiconductor device comprising the step of depositing an upper electrode on the high dielectric film.

The spacer uses a low dielectric material (for example, nitride film (Si ₃ N ₄ )), and Ti / TiN or Ti / TiN / Ta is used as the adhesion layer and the diffusion barrier layer. It is desirable to vary the thickness.

A heat resistant metal (for example, platinum Pt) is used as the lower electrode, and when etch-back is performed, an ending point is used as an interface between the insulating layers between the storage node patterns. The lower electrode is formed to surround the top and sidewall portions of the storage node pattern. The lower electrode of the sidewall portion is used as an electrode and prevents the diffusion barrier layer and the adhesion layer from directly contacting the high dielectric layer.

It is preferable to use STO, BST, or other material having a large dielectric constant as the high dielectric film, and deposition is preferably performed by MOCVD. As the upper electrode, it is preferable to use the same heat resistant metal as the lower electrode.

The present invention can prevent the lowering of the capacitor without directly contacting the high-k dielectric layer, the diffusion barrier layer, and the adhesion layer, and increase the capacity of the capacitor by utilizing the sidewall of the storage node as the capacitor.

Hereinafter, embodiments of the present invention will be described in detail with the accompanying drawings.

2A to 2F are diagrams showing step by step a capacitor manufacturing method using the present invention.

2A illustrates a step of forming a contact hole. Specifically, a well 30 is formed on a substrate (not shown), the device isolation insulating layer 32 is formed, and then the gate electrode 34 is formed. Subsequently, an insulating film 36 of the gate electrode 34 is formed and patterned to deposit an insulating film having the first contact hole 38. Pad polysilicon 40 is formed by filling polycrystalline silicon in the first contact hole 38. An insulating film 42 is formed on the substrate on which the pad polysilicon 40 is formed. A positive photoresist (not shown) is applied on the insulating film and then patterned. When the dry etching is performed using the patterning, the insulating layer 42 is etched to the pad polysilicon 40 interface and the contact hole 46 is formed. Subsequently, the photoresist is removed by a wet method using a chemical or a dry method using an oxygen-plasma. In order to form a spacer 44 on the sidewall of the contact hole 46, a nitride film Si 3 N 4 is uniformly deposited by using low pressure chemical vapor deposition (LPCVD). Subsequently, the resultant material is etched back by dry etching to form spacers 44 on the sidewalls of the contact holes.

The nitride layer spacer 44 is to prevent the insulating layer 42 from being exhausted in the subsequent cleaning of the conductive layer. In the contact hole 46, polysilicon is deposited by about 3,000 kPa by LPCVD and n + ions are implanted to form a conductive layer.

2B shows the steps of forming an adhesion layer and a diffusion barrier layer. Specifically, the entire surface of the insulating film 42 and the conductive layer 48 is etch-back by dry etching. Titanium and titanium nitride (Ti / TiN) or titanium using the CVD method on the resultant The adhesion layer 50 and the diffusion barrier layer 52 are formed by using a low dielectric film such as titanium nitride and tantalum (Ti / TiN / Ta). When using Ti / TiN, Ti is deposited about 400 and TiN is about 600Å. When using Ti / TiN / Ta, Ti is deposited on 200, TiN is deposited on 400, and Ta is deposited on 400Å.

2C illustrates a step of forming the lower electrode. Specifically, in FIG. 2B, a positive photoresist film (not shown) is deposited thinly on the diffusion barrier layer 52. FIG. The photoresist is patterned to dry-etch the adhesion layer 50 and the diffusion barrier layer 52 in the contact hole 46 to form a storage node pattern. Subsequently, the photoresist in the storage node pattern portion is developed and removed. Subsequently, a heat resistant metal (for example, platinum (Pt)) is deposited on the storage node pattern by using a DC magnetron sputter method to form a lower electrode 54.

When platinum Pt is used as an example of the lower electrode 54, an upper portion of the diffusion barrier layer 52 and the adhesion layer 50 forming a storage node pattern may be formed on the upper portion of the diffusion barrier layer 52. 600-200 Å is deposited on the insulating film 42 interface between the 1000-2000 Å storage node patterns, and 300-400 Å is deposited on the sidewalls of the diffusion barrier layer 52 and the adhesion layer 50 forming the storage node pattern. Platinum Pt on the sidewalls of the diffusion barrier layer 52 and the adhesion layer 50 prevents direct contact between the high dielectric film (for example, BST), the diffusion barrier layer 52, and the adhesion layer 50. To prevent capacity degradation, the storage node sidewall can be used as a capacitor. Therefore, the oxidation phenomenon caused by the contact between the insulating layer and the node side wall of the conventional adhesion layer and the diffusion barrier layer can also be prevented.

2D shows etching the lower electrode. Specifically, the material of the lower electrode 54 on the sidewalls of the diffusion barrier layer 52 and the adhesion layer 50 and the portion other than the upper portion of the diffusion barrier layer 52 forming the storage node pattern is removed by dry etching. . As a result of the dry etching of the lower electrode 54, the lower electrode between the storage node patterns is removed, and at the same time, the lower electrode 54 on the diffusion barrier layer 52 is also removed about 600-l200 되고, leaving only about 400-800 Å. . As a result, the lower electrode 54 is formed to surround the storage node pattern, that is, the sidewalls of the diffusion barrier layer 52 and the adhesion layer 50 and the upper portion of the diffusion barrier layer 52.

2E shows a step of depositing a high dielectric film on the lower electrode. Specifically, a high dielectric film (e.g., BST: 56) is deposited by about 600 kV using the MOCVD method. As a result, capacity degradation due to contact between adjacent storage node patterns can be prevented.

2F illustrates depositing an upper electrode on the high dielectric film. Specifically, an upper electrode (for example, platinum (Pt) 58) is deposited on the high dielectric film 56 by using a DC megnetron sputter method. Subsequently, dry etching is used to etch the high-k dielectric film and the upper and lower electrode materials remaining in the wide area other than the node. Subsequently, an oxide film is deposited using a CVD method, the BPSG is covered, reflowed and planarized, and metal contact is performed to complete the capacitor.

In the present invention, the adhesion layer 50 and the diffusion barrier layer 52 are deposited first, and then the upper electrode 54 is deposited in a separate process. The adhesion layer 50 and the diffusion barrier layer 52 are first etched and removed, and then the lower electrode 54 is removed. Therefore, the complexity of the process caused by etching the lower electrode 23 with the oxide film mask can be avoided. In addition, it is possible to prevent the capacitor from declining due to the formation of an oxide spacer in a narrow space between the storage node and the node, and to prevent the narrowing of the gap caused by filling the dielectric material between the nodes. In addition, the present invention prevents the lower electrode 54 from directly contacting the diffusion barrier layer 52 and the adhesion layer 50 with the high-k dielectric film, thereby preventing the occurrence of the oxide film (SiO ₂ ). Therefore, not only can the capacitor capacity be increased, but also the effective area of the capacitor can be increased by using the sidewall of the storage node as the effective area of the capacitor. As a result, the capacitor capacity can be further increased. In addition, even finer patterns do not use oxide spacers (SiO ₂ ), which increases the process margin.

The present invention is not limited to the above embodiments, and it is apparent that many modifications can be made by those skilled in the art within the technical idea of the present invention.

1A to 1F are diagrams showing step-by-step steps of a capacitor manufacturing method using a conventional technique.

2A to 2F are diagrams showing step by step a capacitor manufacturing method using the present invention.

* Description of symbols on the main parts of the drawings *

1, 30: well 3,32: device isolation insulating layer

5, 34: gate electrode 7,36: insulating film, gate electrode

8, 38: first contact hole

9, 40: pad polysilicon 11, 42: insulating film (BPSG)

13, 46: second contact hole 15, 44: spacer

17, 48: conductive layer 19, 50: adhesion layer

21, 52: diffusion barrier layer (barrier) 23, 54: lower electrode

25, 56: dielectric film 27, 58: upper electrode

Claims (3)

Forming an insulating film having a contact hole on the substrate: Forming a spacer on a sidewall of the contact hole: Forming a conductive layer in the contact hole: Sequentially depositing and patterning an adhesion layer and a diffusion barrier layer on the entire surface of the insulating layer and the conductive layer to form a storage node pattern in the contact hole region: Depositing platinum on the storage node pattern and etching-back to form a lower electrode; Depositing a high dielectric film on the lower electrode, and And depositing an upper electrode on the high dielectric film. The method of claim 1, wherein the adhesion layer and the diffusion barrier layer are formed using Ti / TiN or Ti / TiN / Ta. The method of claim 1, wherein the lower electrode is formed to surround an upper sidewall and a sidewall of a storage node pattern.