KR20000003511A - METHOD OF FORMING CAPACITOR OF SEMICONDUCTOR USING TiN FILM - Google Patents

METHOD OF FORMING CAPACITOR OF SEMICONDUCTOR USING TiN FILM Download PDF

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KR20000003511A
KR20000003511A KR19980024753A KR19980024753A KR20000003511A KR 20000003511 A KR20000003511 A KR 20000003511A KR 19980024753 A KR19980024753 A KR 19980024753A KR 19980024753 A KR19980024753 A KR 19980024753A KR 20000003511 A KR20000003511 A KR 20000003511A
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forming
method
capacitor
film
semiconductor device
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KR19980024753A
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Korean (ko)
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송한상
임찬
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김영환
현대전자산업 주식회사
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02183Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10844Multistep manufacturing methods
    • H01L27/10847Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells
    • H01L27/1085Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the capacitor or connections thereto
    • H01L27/10852Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the capacitor or connections thereto the capacitor extending over the access transistor
    • H01L27/10855Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the capacitor or connections thereto the capacitor extending over the access transistor with at least one step of making a connection between transistor and capacitor, e.g. plug
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/60Electrodes
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/60Electrodes
    • H01L28/75Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer

Abstract

PURPOSE: The method is for increasing capacitance and also preventing the increase of leakage current by lowering the thickness of a dielectric film and for reducing the amount of capacitance change. CONSTITUTION: The method is characterized by forming a capacitor of MIM structure where a bottom electrode and a top electrode is made of metal, by forming the bottom electrode and the top electrode of the capacitor having a Ta2O5 dielectric film(19) with a TiN film(16, 20). The method can reduce the leakage current because the difference of work function between the Ta2O5 film and the TiN film is larger than the difference of work function between the Ta2O5 film and a polysilicon film, and can reduce the amount of capacitance change by using a metallic film as the bottom electrode and the top electrode, and can increase capacitance by forming the dielectric film with a thinner effective oxide film.

Description

질화티타늄막을 이용한 반도체 소자의 캐패시터 형성 방법 A capacitor forming a semiconductor device using a film of titanium nitride

본 발명은 반도체 장치 제조 분야에 관한 것으로, 특히 반도체 소자의 캐패시터 형성 방법에 관한 것이다. The present invention relates to a semiconductor device, particularly in a method for forming a capacitor of a semiconductor device.

고집적 반도체 메모리 소자에서 캐패시터의 정전용량(capacitance)을 증가시키기 위해서 유효산화막 두께(T ox )를 줄이고, 소자의 특성의 안정화를 위하여 정전용량의 변화량(ΔC)을 줄이는 것이 요구된다. In order to increase the capacitance of the high integration in a semiconductor memory device a capacitor (capacitance) reducing the effective oxide thickness (T ox), it is required that in order to stabilize the characteristics of the element to reduce the amount of change (ΔC) of capacitance.

Ta 2 O 5 유전막을 갖는 캐패시터의 하부전극을 폴리실리콘막으로 형성하는 경우에는 유효산화막의 두께를 30 Å 이하로 감소시키는 것이 어려울 뿐만 아니라, 유전막이 얇을수록 누설전류가 증가하며, 바이어스(bias) 전압에 따른 정전용량의 변화량이 증가하는 문제점이 있다. In the case of forming the lower electrode of the capacitor has a Ta 2 O 5 dielectric film of a polysilicon film, not only it is difficult to reduce the thickness of the effective oxide to less than 30 Å, and more dielectric layer is thinner increase the leakage current, bias (bias) there is a problem in that the increased amount of change in the capacitance according to voltage.

상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은 유전막의 두께를 감소시켜 정전용량을 증가시킴과 동시에 누설전류의 증가를 방지하고, 바이어스 전압에 따른 정전용량의 변화량을 줄일 수 있는 반도체 소자의 캐패시터 형성 방법을 제공하는데 그 목적이 있다. Capacitor of the invention as contemplated is and simultaneously reducing the thickness of the dielectric increases the capacitance prevents an increase in leakage current, and reduce an amount of change in the capacitance according to the bias voltage semiconductor device that can be in order to solve the above to provide a method for forming it is an object.

도1a 내지 도1g는 본 발명의 일실시예에 따른 반도체 소자의 캐패시터 형성 공정 단면도 Figure 1g to Figure 1a is a sectional view of a semiconductor device forming a capacitor according to one embodiment of the present invention

* 도면의 주요 부분에 대한 도면 부호의 설명 Description of reference numerals of the Related Art

10: 반도체 기판 12: 폴리실리콘 플러그 10: Semiconductor substrate 12: polysilicon plug

13, 15: WSi x 14: PSG막 13, 15: WSi x 14: PSG film

16, 20: TiN 17, 18: 감광막 패턴 16, 20: TiN 17, 18: photosensitive film pattern

19: Ta 2 O 5 19: Ta 2 O 5 film

상기 목적을 달성하기 위한 본 발명은 상기 캐패시터의 하부전극을 이루는 제1 TiN막을 형성하는 제1 단계; The present invention for achieving the abovementioned objects is a first step of forming the first TiN film forming the lower electrode of the capacitor; 상기 제1 TiN막 상에 Ta 2 O 5 막을 형성하는 제2 단계; A second step of forming a film Ta 2 O 5 on the TiN film of claim 1; 및 상기 Ta 2 O 5 막 상에 상부전극을 형성하는 제3 단계를 포함하는 반도체 소자의 캐패시터 형성 방법을 제공한다. And it provides a method for forming a semiconductor capacitor device comprising a third step of forming a top electrode over the Ta 2 O 5 film.

본 발명은 유효산화막의 두께를 감소시키고, 정전용량의 변화량을 줄이기 위해 Ta 2 O 5 유전막을 갖는 캐패시터의 하부전극과 상부전극을 TiN막으로 형성하여, 하부전극 및 상부전극이 금속막으로 이루어지는 MIM(metal-insulator-metal) 구조의 캐패시터를 형성하는데 그 특징이 있다. The present invention reduces the thickness of the effective oxide, MIM to form a lower electrode and the upper electrode of the capacitor has a Ta 2 O 5 dielectric layer to reduce an amount of change in capacitance as a TiN film, a lower electrode and an upper electrode is formed of a metal film (metal-insulator-metal) that has a feature to form a capacitor structure. Ta 2 O 5 막과 폴리실리콘막의 일함수 차보다 Ta 2 O 5 막과 TiN막의 일함수 차가 크기 때문에, 동일한 두께의 유효산화막을 형성하더라도 누설전류를 줄일 수 있으며, 동일한 크기의 누설전류가 발생하는 조건에서 보다 얇은 두께의 유전막을 형성하는 것이 가능하다. Since Ta 2 O 5 film and the polysilicon film, the work function difference than Ta 2 O 5 film and the TiN film, the work function difference in size, even when forming the effective oxide film of the same thickness and can reduce the leakage current, which is of the same magnitude leakage current it is possible to form a dielectric layer of a thinner thickness on the condition.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 바람직한 실시예를 첨부된 도면 도1a 내지 도1g를 참조하여 설명한다. Hereinafter to be described in detail enough characters can be easily performed from the invention one of ordinary skill in the art, reference to a preferred embodiment the figure 1a to 1g also attached to the present invention It will now be described with.

먼저, 도1a에 도시한 바와 같이 반도체 기판(10) 상에 형성된 층간절연막(11)을 선택적으로 식각하여 반도체 기판을 노출시키는 콘택홀을 형성한 후, 콘택홀 내에 폴리실리콘 플러그(plug)(12)를 형성하고, 폴리실리콘 플러그(12) 상에 제1 WSi x (13)를 형성한다. First, one after selectively etching the interlayer insulating film 11 formed on the semiconductor substrate 10 to form a contact hole exposing the semiconductor substrate, the polysilicon plug within the contact hole (plug) as shown in Figure 1a (12 ) and the formation to form the WSi x 1 (13) on the polysilicon plug 12. 상기 제1 WSi x (13)는 폴리실리콘 플러그(12) 상에 TiN막을 형성할 경우, 폴리실리콘 플러그(12)와 TiN막 계면에 TiSi가 형성되어 열적 안정성이 저하되는 것을 방지하기 위한 것이다. Wherein the WSi x 1 (13) is a case of forming a TiN film on the polysilicon plug 12, the polysilicon plug 12 and the TiN film TiSi in the interface is formed it is to prevent the thermal stability decreases.

다음으로, 도1b에 도시한 바와 같이 전체 구조 상에 PSG(phosphosilicate glass)막(14)을 4000 Å 내지 6000 Å 두께로 형성하고, PSG막(14)을 선택적으로 식각하여 하부전극이 형성될 영역에 개구부를 형성한다. Next, the area is to form a PSG (phosphosilicate glass) film 14 on the entire structure with 4000 Å to 6000 Å thick, and selectively etching the PSG film 14, the lower electrode is formed, as shown in Figure 1b to form an opening.

다음으로, 도1c에 도시한 바와 같이 전체 구조 상에 30 Å 내지 70 Å 두께로 제2 WSi x (15)를 형성하고, 제2 WSi x (15) 상에 하부전극을 이룰 200 Å 내지 500 Å 두께의 제1 TiN막(16)을 형성한 후, 개구부 내부를 감광막 패턴(17)으로 채운다. Next, as shown in Fig. 1c form a second 2 WSi x (15) by 30 Å to 70 Å thick on the entire structure, and claim 2 WSi x (15) onto the lower electrode to achieve 200 Å to about a 500 Å after the formation of the 1 TiN film 16 having a thickness, and fills the inside of the opening in the photoresist pattern (17).

상기 제1 TiN막(16)은 TiCl 4 를 증착원료로 사용하고, NH 3 를 가스를 반응가스로 사용하여 화학기상증착법(chemical vapor deposition)으로 형성한다. 1 wherein the TiN film 16 using the TiCl 4 in the vapor source and, by using the NH 3 gas as a reaction gas is formed by chemical vapor deposition (chemical vapor deposition). 이때, TiCl 4 및 NH 3 각각의 유량은 10 sccm 내지 1000 sccm이고, 반응로의 압력은 0.1 Torr 내지 2 Torr이며, 증착온도는 300 ℃ 내지 500 ℃이다. At this time, TiCl 4 and NH 3 flow rate of each is 10 sccm to about 1000 sccm, the pressure of the reactor is 0.1 Torr to 2 Torr, a deposition temperature is 300 ℃ to 500 ℃.

다음으로, 도1d에 도시한 바와 같이 제1 감광막 패턴(17)을 식각마스크로 제1 TiN막(16)을 선택적으로 식각하여 제2 WSi x (15)을 노출시킨다. Next, the degree to which the etch mask, the first photoresist pattern 17 as shown in the first 1d selectively etching the TiN film 16 is exposed to the WSi x 2 (15). 이때, 식각제는 Cl 2 및 O 2 의 혼합가스이고, Cl 2 의 유량은 20 sccm 내지 120 sccm이고, O 2 의 유량은 3 sccm 내지 20 sccm이다. The etching agent is a mixed gas of Cl 2 and O 2, the flow rate of Cl 2 is 20 sccm to about 120 sccm, the flow rate of O 2 is 3 sccm to about 20 sccm. 또한, 식각시 마이크로 파워(micro power)는 850 W 내지 1600 W이고, RF 파워는 40 W 내지 90 W이며, 식각시 압력은 2 mTorr로 유지한다. Further, the micro-power (micro power) during the etching and is 850 W to 1600 W, and the RF power is 40 W to 90 W, the etching when the pressure is kept at 2 mTorr.

이어서, 제1 감광막 패턴(17)을 제거하고, 개구부 내에 제2 감광막 패턴(18)을 형성한다. Then, removal of the first photoresist pattern 17 and to form a second photoresist pattern 18 in the opening.

다음으로, 도1e에 도시한 바와 같이 제2 WSi x (15)을 화학적 기계적 연마(chemical mechanical polishing)하여 층간절연막(14)을 노출시킨다. Next, the first and WSi x 2 (15), a chemical mechanical polishing (chemical mechanical polishing) as shown in Fig. 1e expose the interlayer dielectric film 14.

다음으로, 도1f에 도시한 바와 같이 습식식각으로 PSG(14)막을 제거하고, 제2 감광막 패턴(18)을 식각마스크로 제2 WSi x (15)을 건식식각하고, 제2 감광막 패턴(18)을 제거하여 실린더 형태의 제1 TiN막(16) 하부전극을 형성한다. Next, FIG as a wet etch, as shown in 1f PSG (14) removed, and the second as an etching mask the photosensitive film pattern (18) and dry etching the second WSi x (15), a second photosensitive film pattern (18 membrane ) to remove the claim 1 to form TiN film 16. the lower electrode of a cylindrical shape. 이때, 상기 제1 WSi x (13)와 상기 제1 TiN막(16) 사이에 상기 제2 WSi x (15)가 남게된다. At this time, between the first WSi x 1 (13) of claim 1 and the TiN film 16 is the first WSi x 2 (15) remains.

다음으로, 도1g에 도시한 바와 같이 하부전극 상에 Ta 2 O 5 막(19)을 형성한다. Next, to form a Ta 2 O 5 film 19 on the lower electrode as shown in Fig 1g. 이때, Ta 2 O 5 막(19)은 MOCVD(metal organic chemical vapor deposition) 방법으로 형성하며, 증착원료로는 탄탈륨에톡사이드(Ta(C 2 H 5 O) 5 )를 사용하고 반응 원료의 운반가스로 350 sccm 내지 450 sccm의 N 2 를 사용하고, 산화제로는 20 sccm 내지 50 sccm의 O 2 를 사용한다. At this time, Ta 2 O 5 film 19 is used for MOCVD (metal organic chemical vapor deposition) to form the way, the vapor source to the Messenger the tantalum side (Ta (C 2 H 5 O ) 5) and carrying a reaction raw material a gas using N 2 of 350 sccm to 450 sccm and the oxidizing agent is used in an O 2 of 20 sccm to 50 sccm. 또한, Ta 2 O 5 막(19) 형성시 반응로 내의 압력은 0.2 Torr 내지 0.4 Torr로 유지하고, 온도는 350 ℃ 내지 450 ℃가 되도록 한다. In addition, the pressure in the Ta 2 O 5 film 19 upon formation of the reaction is to be maintained at 0.2 Torr to about 0.4 Torr, and the temperature is 350 ℃ to 450 ℃.

이어서, 급속열처리 공정을 실시하고, Ta 2 O 5 막(19) 상에 상부전극을 이룰 제2 TiN막(20)을 제1 TiN막(16) 형성 조건과 동일한 조건에서 형성한다. Then, rapidly subjected to a heat treatment step, and forming a second TiN film 2 (20) to achieve a top electrode on the Ta 2 O 5 film 19 under the same condition as claim 1 TiN film 16 formed condition.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다. The present invention described above is not limited by the embodiments described above and the accompanying drawings, it is that various changes and modifications may be made without departing from the scope of the present invention in the art got to those of ordinary skill will be obvious.

상기와 같이 이루어지는 본 발명은 Ta 2 O 5 유전막을 갖는 캐패시터의 하부전극과 상부전극을 TiN막으로 형성하여, 동일한 두께의 유효산화막을 형성하더라도 누설전류를 줄일 수 있고, 정전용량의 변화량을 줄일 수 있으며, 동일한 크기의 누설전류가 발생하는 조건에서 보다 얇은 유효산화막 두께로 유전막을 형성하여 정전용량을 증가시킬 수 있다. To form a lower electrode and the upper electrode of the capacitor of this invention having a Ta 2 O 5 dielectric layer formed as described above, the TiN film, even if formed in the effective oxide film of the same thickness and can reduce the leakage current, to reduce the amount of change in capacitance and, it is possible to increase the capacitance by forming a dielectric film with a thinner effective oxide thickness in the condition that the size of the same leakage current.

Claims (16)

  1. 반도체 소자의 캐패시터 형성 방법에 있어서, In the method for forming a capacitor of a semiconductor device,
    상기 캐패시터의 하부전극을 이루는 제1 TiN막을 형성하는 제1 단계; A first step of forming the first TiN film forming the lower electrode of the capacitor;
    상기 제1 TiN막 상에 Ta 2 O 5 막을 형성하는 제2 단계; A second step of forming a film Ta 2 O 5 on the TiN film of claim 1; And
    상기 Ta 2 O 5 막 상에 상부전극을 형성하는 제3 단계를 포함하는 반도체 소자의 캐패시터 형성 방법. A capacitor forming a semiconductor device including a third step of forming a top electrode over the Ta 2 O 5 film.
  2. 제 1 항에 있어서, According to claim 1,
    상기 상부전극을 제2 TiN막으로 형성하는 반도체 소자의 캐패시터 형성 방법. A capacitor forming a semiconductor device of forming the upper electrode 2 to the TiN film.
  3. 제 2 항에 있어서, 3. The method of claim 2,
    상기 제1 TiN막 및 상기 제2 TiN막을 TiCl 4 를 증착원료로 사용하고, NH 3 를 가스를 반응가스로 사용하여 화학기상증착법(chemical vapor deposition)으로 형성하는 반도체 소자의 캐패시터 형성 방법. 1 wherein the TiN film and the second capacitor forming a semiconductor device of TiN films using the TiCl 4 in the vapor source to form a CVD (chemical vapor deposition) by use of the NH 3 gas as a reaction gas.
  4. 제 3 항에 있어서, 4. The method of claim 3,
    상기 NH 3 를 10 sccm 내지 1000 sccm 공급하는 반도체 소자의 캐패시터 형성 방법. A capacitor forming a semiconductor element for supplying the NH 3 10 sccm to about 1000 sccm.
  5. 제 3 항에 있어서, 4. The method of claim 3,
    상기 제1 TiN막 및 상기 제2 TiN막 형성시 압력은 0.1 Torr 내지 2 Torr의 이고, 온도는 300 ℃ 내지 500 ℃인 반도체 소자의 캐패시터 형성 방법. 1 wherein the TiN film and the second TiN film 2 to form the pressure is of 0.1 Torr to 2 Torr, temperature of the capacitor forming method of the semiconductor device 300 ℃ to 500 ℃.
  6. 제 2 항에 있어서, 3. The method of claim 2,
    상기 Ta 2 O 5 막을 MOCVD(metal organic chemical vapor deposition) 방법으로 형성하며, 증착원료로는 탄탈륨에톡사이드(Ta(C 2 H 5 O) 5 )를 사용하고 반응 원료의 운반가스로 N 2 를 사용하고, 산화제로 O 2 를 사용하는 반도체 소자의 캐패시터 형성 방법. Using the Ta 2 O 5 film MOCVD (metal organic chemical vapor deposition) to form the way, the vapor source to the Messenger the tantalum side (Ta (C 2 H 5 O ) 5) , and the N 2 as the carrier gas of the reaction raw material used, and the capacitor forming a semiconductor device using the O 2 as the oxidant.
  7. 제 6 항에 있어서, 7. The method of claim 6,
    상기 N 2 는 350 sccm 내지 450 sccm 공급하고, The N 2 supply is 350 sccm to 450 sccm,
    상기 O 2 는 20 sccm 내지 50 sccm 공급하는 반도체 소자의 캐패시터 형성 방법. A capacitor forming a semiconductor device of the O 2 supply is 20 sccm to 50 sccm.
  8. 제 7 항에 있어서, The method of claim 7,
    상기 Ta 2 O 5 막 형성시 압력은 0.2 Torr 내지 0.4 Torr이고, 온도는 350 ℃ 내지 450 ℃인 반도체 소자의 캐패시터 형성 방법. The Ta 2 O 5 film formed when the pressure is 0.2 Torr to about 0.4 Torr, the temperature is a capacitor forming method of the semiconductor device 350 ℃ to 450 ℃.
  9. 제 8 항에 있어서, The method of claim 8,
    상기 제2 단계 후, After the second step,
    급속열처리를 실시하는 제4 단계를 더 포함하는 반도체 소자의 캐패시터 형성 방법. A capacitor forming a semiconductor device of rapidly a fourth step of performing heat treatment further.
  10. 제 1 항 내지 제 8 항 중 어느 한 항에 있어서, The method according to any one of claims 1 to 8,
    상기 제1 단계는, The first step,
    반도체 기판 상에 형성된 층간절연막을 선택적으로 식각하여, 상기 반도체 기판을 노출시키는 콘택홀을 형성하는 단계; And selectively etching the interlayer insulating film formed on a semiconductor substrate, forming a contact hole exposing the semiconductor substrate;
    상기 콘택홀 내에 폴리실리콘 플러그를 형성하는 단계; Forming a polysilicon plug in said contact holes; And
    상기 폴리실리콘 플러그 상에 제1 WSi x 를 형성하는 단계를 포함하며, And forming a second 1 WSi x on the polysilicon plug,
    상기 하부전극을 이루는 제1 TiN막은 상기 제1 WSi x 과 접하는 반도체 소자의 캐패시터 형성 방법. A first capacitor forming a semiconductor element which is in contact with the first WSi x TiN film forming the lower electrode.
  11. 제 10 항에 있어서, 11. The method of claim 10,
    상기 제1 단계는, The first step,
    반도체 기판 상에 희생산화막을 형성하고, 상기 희생산화막을 선택적으로 식각하여 하부전극 형성 영역에 개구부를 형성하는 제5 단계; Forming a sacrificial oxide film on a semiconductor substrate, and a fifth step of forming an opening in the lower electrode forming region by selectively etching the sacrificial oxide film;
    상기 개구부 측벽 및 바닥 상에 제2 WSi x 및 상기 제1 TiN막을 형성하는 제6 단계; A sixth step of forming the 2 x and WSi film of claim 1 wherein the TiN on the opening side wall and a bottom;
    상기 희생산화막을 제거하는 제7 단계; A seventh step of removing the sacrificial oxide film; And
    상기 제2 WSi x 를 선택적으로 식각하여 상기 제1 WSi x 와 상기 제1 TiN막 사이에 상기 제2 WSi x 를 잔류시키며, 상기 제1 TiN막으로 실린더 형태의 하부전극을 형성하는 제8 단계를 포함하는 반도체 소자의 캐패시터 형성 방법. Wherein the 2 WSi x to selectively etched sikimyeo between the first 1 WSi x and the second 1 TiN film remaining the claim 2 WSi x, an eighth step of forming a lower electrode of a cylindrical shape with the first 1 TiN film a capacitor forming a semiconductor device comprising.
  12. 제 11 항에 있어서, 12. The method of claim 11,
    상기 희생산화막을 4000 Å 내지 6000 Å 두께의 PSG(phosphosilicate glass)막으로 형성하는 반도체 소자의 캐패시터 형성 방법. A capacitor forming a semiconductor device forming the sacrificial oxide film by 4000 Å to 6000 Å thickness of PSG (phosphosilicate glass) film.
  13. 제 12 항에 있어서, 13. The method of claim 12,
    상기 제2 WSi x 를 30 Å 내지 70 Å 두께로 형성하고, Formed by the first 2 WSi x to 30 Å to 70 Å thick,
    상기 제1 TiN막을 200 Å 내지 500 Å 두께로 형성하는 반도체 소자의 캐패시터 형성 방법. A capacitor forming a semiconductor device of claim 1 formed with the TiN film 200 Å to about 500 Å thick.
  14. 제 13 항에 있어서, 14. The method of claim 13,
    상기 제6 단계는, The sixth step includes
    상기 제5 단계가 완료된 전체 구조 상에 상기 제2 WSi x 를 형성하는 단계; Forming the first 2 WSi x on the entire structure of the fifth step has been completed;
    상기 제2 WSi x 상에 상기 제1 TiN막을 형성하는 단계; Forming the first TiN film 1 on the first 2 WSi x;
    상기 제1 TiN을 선택적으로 식각하여 상기 제2 WSi x 를 노출시키는 단계; Exposing the first 2 WSi x by selectively etching the TiN of claim 1; And
    상기 제2 WSi x 를 연마하여 상기 층간절연막을 노출시키는 단계를 포함하는 반도체 소자의 캐패시터 형성 방법. A capacitor forming a semiconductor device of claim 2 by grinding the WSi x exposing the interlayer insulation film.
  15. 제 14 항에 있어서, 15. The method of claim 14,
    상기 제1 TiN을 선택적으로 식각하여 상기 제2 WSi x 를 노출시키는 단계는, Exposing the first 2 WSi x by selectively etching the above claim 1 is TiN,
    Cl 2 및 O 2 의 혼합가스를 사용한 식각을 실시하는 반도체 소자의 캐패시터 형성 방법. A capacitor forming a semiconductor device for performing an etching using a mixed gas of Cl 2 and O 2.
  16. 제 15 항에 있어서, 16. The method of claim 15,
    상기 Cl 2 의 양은 20 sccm 내지 120 sccm이고, The amount of the Cl 2 20 sccm to 120 sccm,
    상기O 2 의 유량은 3 sccm 내지 20 sccm이고, The flow rate of the O 2 is 3 sccm to about 20 sccm,
    식각시 마이크로 파워(micro power)는 850 W 내지 1600 W이고, And when the etching micro-power (micro power) is 850 W to 1600 W,
    RF 파워는 40 W 내지 90 W이고 RF power is 40 W to 90 W, and
    식각시 압력은 2 mTorr인 반도체 소자의 캐패시터 형성 방법. When the etching pressure of 2 mTorr capacitor forming a semiconductor device.
KR19980024753A 1998-06-29 1998-06-29 METHOD OF FORMING CAPACITOR OF SEMICONDUCTOR USING TiN FILM KR20000003511A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7018933B2 (en) 2000-06-07 2006-03-28 Samsung Electronics, Co., Ltd. Method of forming a metal-insulator-metal capacitor
KR100585002B1 (en) * 2004-05-31 2006-05-29 주식회사 하이닉스반도체 Method for fabricating capacitor in semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7018933B2 (en) 2000-06-07 2006-03-28 Samsung Electronics, Co., Ltd. Method of forming a metal-insulator-metal capacitor
KR100585002B1 (en) * 2004-05-31 2006-05-29 주식회사 하이닉스반도체 Method for fabricating capacitor in semiconductor device

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