KR0130544B1 - Capacitor manufacturing method of semiconductor device - Google Patents

Abstract

A fabrication method of stacked capacitors is provided to improve capacitance and step coverage using novel capacitor structure having a storage electrode formed on dielectric layer and a plate electrode. The method comprises the steps of: dry-etching a first polysilicon layer(9) using a first PR layer(10); depositing a dielectric layer(11) and a second polysilion layer(12); forming a contact hole(30); sequentially forming a doped third polysilicon (14), CVD oxide(15) and a doped a fourth polysilicon(16); sequentially etching the polysilicon layers(16,14,12) and the CVD oxide(15) to form a storage node; forming a second dielectic layer(18) and a fifth polysilicon(19); and exposing the first polysilicon layer(9).

Description

Capacitor Manufacturing Method of Semiconductor Device

1A to 1F are cross-sectional views showing steps of manufacturing a stacked capacitor according to the present invention.

* Explanation of symbols for main parts of the drawings

1: silicon substrate 2: field coral film

3: gate oxide film 4: gate electrode

5 insulating film 6 impurity region

7: spacer oxide film 8: nitride film

9: first polysilicon 10: first photosensitive film

11: first dielectric film 12: second polysilicon

13 second photosensitive film 14 third polysilicon

15 CVD oxide film 16 fourth polysilicon

17: third photosensitive film 18: second dielectric film

19: fifth polysilicon 20: fourth photosensitive film

21: 6th polysilicon 30: Contact hole

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor of a semiconductor device, and more particularly to a method of manufacturing an ultra-high density stacked capacitor having an increased storage capacity by forming a dielectric film and a plate electrode under a charge storage electrode of a capacitor. Conventional stacked capacitors form a dielectric film only on the top and sides of the charge storage electrode, and then form a plate electrode thereon, which has to be raised in height to obtain the desired accumulation capacity within the limited unit cell area. Problems are caused by the step in forming the wiring. Accordingly, an object of the present invention is to provide a method of manufacturing an ultra-high density stack capacitor having an increased accumulation capacity while solving the above problems. Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. 1A to 1F are cross-sectional views showing steps of manufacturing a stacked capacitor according to the present invention, and FIG. 1A is a field oxide film 2, a gate oxide film 3, and a gate electrode 4 on a silicon substrate 1; ), The insulating film 5, the impurity region 6, and the spacer oxide film 7 are sequentially formed to form a predetermined transistor, and then the nitride film 8 and the doped first polysilicon 9 are successively formed over the entire structure. It shows the state formed by. FIG. 1B illustrates a state in which the first polysilicon layer 9 is dry-etched to form a constant etch bias after forming the first photoresist layer 10 having a predetermined pattern. After removing the first photosensitive film 10, the first dielectric film 11 and the second polysilicon film 12 are formed to a predetermined thickness on the entire structure, and then the contact mask for the charge storage electrode is formed. The state where the contact hole 30 is formed by forming the patterned 2nd photosensitive film 13 is used. FIG. 1d illustrates the doped third polysilicon 14 and the planarized CVD oxide film 15 after removing the patterned second photoresist layer 13, and then after the predetermined photolithography, the third polysilicon 14 ) And the doped fourth polysilicon 16 is formed on the entire structure, and the third photosensitive film 17 having a predetermined pattern is formed on the fourth polysilicon 16. It is shown. In FIG. 1E, the exposed fourth polysilicon 16 is etched using the third photoresist layer 17, the exposed CVD oxide layer 15 is wet-etched, and then the second dielectric layer 18 is formed on the entire structure. And the fifth polysilicon 19 are formed to a predetermined thickness, and then a fourth photosensitive film 20 having a predetermined pattern is formed to expose the first polysilicon 9 by anisotropic etching using the same. FIG. 1F illustrates a state in which a predetermined capacitor is formed by removing the fourth photoresist film 20 and then forming the doped sixth polysilicon 21. According to the present invention, the third and fourth polysilicon 14, 16 are for charge storage electrodes, and the first and sixth polysilicon 9, 21 are for plate electrodes. The second and fifth polysilicon layers 12 and 19 are doped or not doped with an impurity and have a thickness of 100 to 500 microseconds, which serves as an etch protection layer of the dielectric layers 11 and 18, which are lower layers.

A stack structure is formed of the third and fourth polysilicon (14, 16) for the charge storage electrode, and the first and second dielectric films (11, 18) and the first and sixth polysilicon (9, 21) for the plate electrode. A dielectric film and a plate electrode are formed above and below the charge storage electrode to secure an increased storage capacity.

As described above, by forming the dielectric film and the plate electrode under the electron storage electrode of the capacitor, the capacitance of the capacitor can be increased to improve the reliability of the device by reducing the characteristic and the step difference.

Claims (2)

In the method of manufacturing a capacitor of a semiconductor device, a field oxide film, a gate oxide film, a gate electrode, an insulating film, an impurity region, and a spacer oxide film are sequentially formed on a silicon substrate to form a predetermined transistor, and then a nitride film and a doped material on the entire structure. 1 forming a polysilicon, dry etching the first polysilicon film to form a constant etch bias after forming the first photoresist film having a predetermined pattern therefrom, and removing the first photoresist film from the step Forming a contact hole by forming a first dielectric film and a second polysilicon film on the entire structure to a predetermined thickness, and then forming a patterned second photoresist film using a contact mask for a charge storage electrode; After removing the patterned second photoresist, a doped third polysilicon and a planarized CVD oxide film are formed. Forming a third photoresist film having a predetermined pattern on the fourth polysilicon after forming a doped fourth polysilicon on the entire structure after leaving the third polysilicon remaining about 50 to 500Å after a predetermined photolithography. And etching the exposed fourth polysilicon using the third photosensitive film from the above step, removing the exposed CVD oxide film by wet etching, and then forming the second dielectric film and the fifth polysilicon on the entire structure to a predetermined thickness. Thereafter, forming a fourth photoresist film having a predetermined pattern and exposing the first polysilicon by anisotropic etching using the same, and removing the fourth photoresist film from the above step and forming the doped sixth polysilicon. The third and fourth polysilicon as the charge storage electrode of the capacitor, the first and the second dielectric film as the dielectric film of the capacitor, and the first and the six polysilicon as the capacitor A capacitor manufacturing method of a semiconductor device, characterized by comprising a plate electrode of a capacitor to increase the storage capacity of the capacitor. 2. The method of claim 1, wherein the second and fifth polysilicon layers are formed in an etching protection layer of a dielectric film as a lower layer to a thickness of 100 to 500 microseconds.