KR100631371B1 - Array Panel used for a Liquid Crystal Display and Method for Fabricating the same - Google Patents

Abstract

end. The technical field to which the invention described in the claims belongs:

Array panel for liquid crystal display device and manufacturing method thereof

I. The technical problem the invention is trying to solve:

Conventionally, the gate metal of the array panel for a liquid crystal display device is made of a double metal layer such as molybdenum (Mo) / aluminum neodymium (AlNd) because aluminum (Al) has a weak chemical resistance and poor contact with ITO. Simultaneous etching of the two metal layers is difficult, and thus a process is added, thereby reducing productivity.

All. The gist of the solution of the invention:

In order to solve the above problems, in the present invention, a single metal layer containing aluminum is used as the gate metal, and molybdenum (Mo) and chromium (Cr) are formed between the gate pad and the gate pad electrode without adding a process using a semi-transmissive mask. By forming source and drain metals with lower reducibility than aluminum such as aluminum, tungsten (W), titanium (Ti), and indium (In) as a contact buffer layer, it solves the problem of using aluminum as gate wiring and does not add a process. An array panel for a liquid crystal display device and a method for manufacturing the same are provided.

Description

Array panel used for a liquid crystal display and method for fabricating the same}             

1 is an exploded perspective view showing a typical liquid crystal panel.

2 is a process block diagram of an array panel for a liquid crystal display device according to a general five mask process.

3 is a plan view corresponding to some pixel parts of an array panel for a liquid crystal display according to the present invention;

4A to 4G are cross-sectional views taken along cutting process lines A-A ', B-B' and C-C 'of FIG.

5A and 5B are cross-sectional views illustrating a process of forming a photo resist pattern on a substrate using a general exposure mask.

6A and 6B are cross-sectional views illustrating a process of forming a photoresist pattern on a substrate using a general transflective mask.

<Description of Symbols for Main Parts of Drawings>

T: thin film transistor portion C: capacitor electrode portion                 

P: gate pad portion 118: drain electrode

120: capacitor auxiliary electrode 122: contact buffer layer

130: pixel electrode 132: gate pad electrode

 BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an array panel for a liquid crystal display device. More particularly, in using a single metal layer including aluminum as a gate metal, the liquid crystal display device array simplifies the process while solving a problem of contact between aluminum and ITO. A panel and a method of manufacturing the same.

The driving principle of the liquid crystal display device is to use the optical anisotropy and polarization property of the liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Accordingly, if the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular arrangement direction of the liquid crystal due to optical anisotropy to express image information.

Currently, an active matrix LCD (AM-LCD), in which thin film transistors (TFTs) and pixel electrodes connected to the thin film transistors are arranged in a matrix manner, has the highest resolution and video performance, and is most noticeable. I am getting it.

In general, the structure of a liquid crystal panel, which is a basic component of a liquid crystal display, will be described.

1 is an exploded perspective view schematically illustrating a general liquid crystal panel.

As shown in the drawing, a general liquid crystal panel is largely composed of an upper panel 10 and a lower array panel 20. The black matrix 6a, R, G, and B cells are formed on the substrate 1 of the upper panel 10. A color filter 6 including 6b is formed, and a common electrode 18 is formed on the lower surface of the substrate 1.

On the substrate 1 of the lower array panel 20, an array wiring including a pixel region P and a pixel electrode 17 formed on the pixel region and a switching element is formed, and the upper panel 10 and the lower array are formed. The liquid crystal 14 is filled between the panels 20.

In the lower array panel 20, a thin film transistor T, which is a switching element, is positioned in a matrix type, and the gate line 13 and the data line 15 passing through the plurality of thin film transistors T cross each other. Is formed.

The pixel region P is a region where the gate line 13 and the data line 15 cross each other.

In the liquid crystal display device including the liquid crystal panel configured as described above, the liquid crystal 14 positioned on the pixel electrode 17 is oriented by a signal applied from the thin film transistor T, Accordingly, the image can be expressed by controlling the amount of light passing through the liquid crystal 14.                         

2 is a process block diagram of an array panel for a liquid crystal display device according to a general five mask process.

In this case, an inverted staggered thin film transistor structure is most frequently used in the thin film transistor of the array panel for a liquid crystal display device.

The inverted staggered thin film transistor has the advantage of improving the interfacial characteristics of the thin film transistor because the interface between the insulating film and the amorphous silicon is not exposed to air because the deposition process of the insulating film, the amorphous silicon and the impurity amorphous silicon is performed in one chamber. have.

The array panel is formed by coating a thin film on a transparent substrate mainly through a plasma enhanced chemical vapor deposition (PECVD) and a sputtering method. In particular, the ITO and the metal wiring of the pixel electrode are deposited by the sputtering method.

As shown, in ST1, a transparent substrate is prepared, a cleaning process is performed to remove foreign substances on the transparent substrate, and a metal material is deposited on the cleaned substrate by a sputtering method, and then the metal is deposited. The gate wiring including the gate electrode and the gate pad is formed by exposing, etching and patterning using the first mask.

In this case, a glass substrate which is inexpensive and widely used as a substrate of a large area liquid crystal panel is mainly used as the transparent substrate.

Wherein, yeoteuna gate metal in the prior art, aluminum (Al) is mainly used, aluminum is chemically weak resistance, so the more than 200 ℃ the advent of hilrak (hillock) which have grown to a certain site can ㎛ the Al ₂ 0 ₃ in the surface There is a method of coating and using.

However, when the gate wiring is formed using only a metal layer containing aluminum, aluminum ions react with indium and tin of indium tin oxide (ITO) during the etching process of the ITO forming the pixel electrode, thereby reducing the transparent conductive characteristics of the ITO. The problem arises.

Therefore, there is a method of laminating a metal film such as molybdenum (Mo), tungsten (W), etc. in a clad structure on a metal layer containing aluminum.

This method is used because the specific resistance is lower than that of pure aluminum, but it is excellent in chemical resistance and thermal stability and can solve the above problems.

In ST2, a gate insulating film is formed of an insulating material such as a silicon nitride film on the substrate on which the gate wiring is formed, and subsequently, an amorphous silicon and an impurity amorphous silicon layer are deposited.

In ST3, the amorphous silicon and the impurity amorphous silicon layer are exposed and etched with a second mask to form an active layer.

The impurity amorphous silicon layer is an ion doped amorphous silicon layer to increase electron mobility, and is formed for the purpose of lowering the contact resistance between the metal layer and the amorphous silicon layer to be formed later.

In ST4, a metal layer is deposited on the substrate on which the active layer is formed by sputtering. In ST5, the metal layer is formed by a third mask process to form a source, a drain electrode, and a data wiring.

In ST6, a protective layer is formed on the substrate on which the source and drain electrodes are formed, and a drain contact hole, a gate pad contact hole, and a data pad contact hole are formed by a fourth mask process.

The protective layer is used to prevent damage or deterioration of the thin film transistor caused by rubbing and moisture infiltration during the liquid crystal cell process of the liquid crystal display device. The material of the protective layer is a silicon nitride film or It is formed of BCB (BenzoCycloButene), which is an organic insulating film.

ST7 is a step of depositing a transparent conductive material on the substrate on which the drain contact hole is formed, and then forming a pixel electrode, a gate, and a data pad electrode in the pixel region and the pad electrode portion by a fifth mask process.

Indium Tin Oxide (ITO) is generally used as this transparent conductive material.

At this time, the gate pad electrode is configured to be in direct contact with the gate pad through the gate pad contact hole, and the ITO forming the gate pad electrode has poor contact with aluminum, so that the first metal layer of the gate pad in contact with the ITO is generally molybdenum. It is made of a metal such as or chromium, and the second metal layer is made of aluminum which is a low resistance wiring material.

When using this double metal layer as a gate metal, the following problems occur.

First, when the gate wiring is formed of a double metal layer such as molybdenum / aluminum neodymium, it is difficult to obtain a desired taper angle during simultaneous etching.

The taper angle of this gate wiring prevents the disconnection of the data wiring caused by step coverage during the deposition of the data wiring later and serves as a factor for determining the voltage-current characteristics. If it loses, the problem which shows commutation characteristic arises.

Secondly, in order to prevent the above-mentioned problem, a double metal layer has to be etched, so a process is added.

When the process is added, the possibility of deterioration of the electrical characteristics is increased due to the foreign matter in the air or the etching process in which the important elements of the array panel for the liquid crystal display are added. Will fall.

However, when the gate metal is used as a double metal layer, as described above, a problem in that productivity is reduced due to the addition of a process occurs.

In order to solve the above problems, in the present invention, the gate metal is made of a single metal layer containing aluminum, and instead of improving the lamination structure of the part where aluminum and ITO contact each other, the object is to simplify the process and improve the product yield. It is done.

In order to achieve the above object, in the present invention, the gate metal is a single metal layer including aluminum, and a source and a drain metal having a lower reducibility than aluminum are used between the gate pad and the gate pad electrode without adding a process using a semi-transmissive mask. By forming a contact buffer layer, it is possible to prevent chemical reaction between aluminum and ITO, which is a pad electrode material, and to improve the characteristics of aluminum while simplifying the process, thereby reducing signal delay, thereby improving image quality and productivity. And a method for producing the same.

That is, in the present invention, the gate wiring made of a single metal layer containing aluminum (Al); A data wiring comprising a source electrode crossing the gate wiring and made of a metal having a lower reducibility than the aluminum, and having a source electrode spaced apart from the drain electrode by a predetermined distance; A thin film transistor including the source and drain electrodes; A pixel electrode connected to the thin film transistor; A gate pad positioned at an end of the gate wiring; A contact buffer layer formed of the same material as the data line on the gate pad; An array panel for contacting the contact buffer layer and including a gate pad electrode formed of the same material as the pixel electrode is provided.

The display device may further include a capacitor electrode having the same material as the gate wiring, an insulating layer on the capacitor electrode, and a capacitor auxiliary electrode having the same material as the data wiring between the insulating layer and the pixel electrode. The metal forming the drain electrode and the data wiring is one of chromium (Cr), molybdenum (Mo), tungsten (W), titanium (Ti), and indium (In).

In still another aspect of the present invention, there is provided a method of preparing a substrate, comprising: preparing a substrate; Forming a gate wiring including a gate electrode and a capacitor electrode as a single metal layer including aluminum (Al) on the substrate, and a gate pad having a predetermined area at an end of the gate wiring by a first mask process; Wow; Continuously depositing a gate insulating film and a semiconductor layer on an entire surface of the substrate on which the gate wiring is formed; Forming an active layer on the gate electrode by a second mask process and simultaneously exposing an upper portion of the gate pad; Depositing a metal layer having a lower reducibility than aluminum on the substrate on which the active layer is formed, and then forming a contact buffer layer on the source, drain electrode and the gate pad, respectively, on the active layer by a third mask process; Forming a protective layer on the substrate on which the source and drain electrodes are formed and forming a drain contact hole and a gate pad contact hole by a fourth mask process; Depositing ITO on the substrate on which the drain contact hole is formed, a pixel electrode contacting the drain electrode through the drain contact hole and a gate pad electrode contacting the contact buffer layer through the gate pad contact hole by a fifth mask process It provides a method of manufacturing an array panel for a liquid crystal display device comprising the step of forming a.

The second mask process uses a transflective mask having an opaque region, a transflective region, and a full transmissive region, wherein the opaque region corresponds to the active layer and the fully transmissive region corresponds to the gate pad portion. The semi-transmissive mask may arbitrarily adjust the thickness of the photoresist on the substrate by controlling the transmittance of light using a metal film including chromium (Cr) and a transparent conductive material film, and in the second mask process, Removing only the semiconductor layer on the capacitor electrode, and in the third mask process further comprises forming a capacitor auxiliary electrode on the capacitor electrode of the same metal layer as the source and drain electrodes.

The metal constituting the source and drain electrodes is one of chromium (Cr), molybdenum (Mo), tungsten (W), titanium (Ti), and indium (In).

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

3 is a plan view of some pixel parts of the array panel for a liquid crystal display device of the present invention.

As shown, the gate wiring 103 including the gate electrode 102 is formed in the horizontal direction.

At this time, the gate metal is characterized by a single metal layer containing aluminum.

In the longitudinal direction, the data line 117 including the source electrode 116 intersects with the gate line 103, and the source electrode 116 is formed to be spaced apart from the drain electrode 118 by a predetermined distance. .

The gate electrode 102 and the source and drain electrodes 116 and 118 form a thin film transistor T.

In addition, a gate pad (not shown) having a predetermined area is positioned at an end of the gate wiring 103, and the contact buffer layer 122 and the gate pad electrode 132 are sequentially stacked on the gate pad so that the gate pad portion ( P).

The contact buffer layer 122 is made of the same metal as the source and drain electrodes, and the gate pad electrode 132 is made of the same material as the pixel electrode.

The contact buffer layer 122 is indicated by hatched areas to indicate that it is the same material as the data line 117.

The formation of the contact buffer layer 122 between the gate pad and the gate pad electrode 132 is to block contact between aluminum formed of the gate pad metal and ITO formed of the gate pad electrode material.

At this time, the electrical connection between the gate pad and the gate pad electrode 132 passes through the contact buffer layer 122, which is a metal layer, and the gate pad 106 and the gate pad electrode 112 are formed by forming the contact buffer layer 122. It is possible to effectively prevent the deterioration of the properties of both materials due to the contact between aluminum, which is a material forming each material, and ITO.

Then, a capacitor electrode 104 is formed which uses a part of the gate wiring 103 as a common electrode of maintenance capacitance.

Since the capacitor electrode 104 is formed in the gate wiring 103 and may cause a signal delay of the gate wiring, it is preferable to form the gate wiring 103 with a single metal layer containing aluminum which is a low resistance material.

At this time, aluminum has a problem that the heel lock occurs, thereby preventing the film formation of the insulating film, aluminum and the ITO, a pixel electrode material formed on the capacitor electrode 104 is in contact with each other to cause a chemical reaction. Therefore, the capacitor auxiliary electrode 120 made of the data line 117 material is formed at the portion of the capacitor electrode 104 in contact with the pixel electrode 103.

4A to 4G are cross-sectional views illustrating the manufacturing process steps of cutting lines A-A ', B-B' and C-C 'of FIG. 3, and will be described in connection with the 5 mask process block of FIG. 2. would.

In this case, A-A 'is a thin film transistor portion, B-B' is a capacitor electrode portion, and C-C 'is a cut line of the gate pad portion.

FIG. 4A illustrates the deposition of a single metal layer including aluminum on the substrate 1 cleaned by the process corresponding to ST1 of FIG. 2, followed by the gate electrode 102, the capacitor electrode 104, and the gate pad in a first mask process. Step 106 is formed.

4B illustrates a process corresponding to ST2 of FIG. 2, wherein the gate insulating layer 108, the amorphous silicon 110a (a-Si), and the impurity amorphous silicon 110b (n + -a-Si) are formed on the entire surface of the substrate on which the gate electrode 102 is formed. ) Is continuously deposited.

In FIG. 4C, a photoresist 112 is used during the masking process of the substrate on which the semiconductor layer 110 made of amorphous silicon 110a (a-Si) and impurity amorphous silicon (110b; n + -a-Si) is formed. The thickness is formed differently in the thin film transistor unit T, the capacitor electrode unit C, and the gate pad unit P, respectively.

That is, the photoresist 112 is formed thickest in the thin film transistor portion T, the thinner than the thin film transistor portion T in the capacitor electrode portion C, and the photoresist is removed in the gate pad portion P. Do it.

The mask process may use a transflective mask, which will be described in detail with reference to FIG. 6A.

FIG. 4D illustrates a process corresponding to ST3 of FIG. 2. The gate pad portion in which the photoresist 112 is removed by the same etching rate while patterning the semiconductor layer 110 and forming the active layer 111a as shown in FIG. In P, the upper portion of the gate pad 106 is exposed.

At this time, an ohmic contact layer 111b made of an impurity amorphous silicon layer 110b is disposed on the active layer 111a, and the ohmic contact layer 111b serves to lower the contact resistance between the active layer 111a and the metal layer. Do it.

That is, according to the general exposure mask, two mask processes are required for the process of forming the active layer 110 and the process of exposing the upper portion of the gate pad 106, but in the present invention, the semi-transmissive mask may be used at one time. have.

FIG. 4E is a process corresponding to ST4 and 5 of FIG. 2, and then deposits source and drain metals, and then, on the source, drain electrodes 116 and 118, the capacitor electrode 104, and the gate pad 106 by a third mask process. The contact buffer layer 122 is formed on the capacitor auxiliary electrode 120 and the gate pad portion P in the same process using the same material as the source and drain metals 116 and 118, respectively.

At this time, the ohmic contact layer 110b is removed between the source and drain electrodes 116 and 118 to form a channel ch of the thin film transistor unit T.                     

The metal forming the source and drain electrodes 116 and 118 is less reducible than aluminum and has high chemical resistance and high thermal stability, such as chromium (Cr), tungsten (W), molybdenum (Mo), titanium (Ti), and indium ( In) made of any one metal.

FIG. 4F is a step corresponding to ST6 of FIG. 2. After the protective layer 124 is deposited on the substrate on which the source and drain electrodes 116 and 118 are formed, the drain contact hole 126 and the capacitor contact are formed by a fourth mask process. The hole 127 and the gate pad contact hole 128 are formed.

4G illustrates a process step corresponding to ST7 of FIG. 2. After depositing ITO on the substrate on which the protective layer 124 is formed, the pixel electrode 130 is formed on the pixel region by a fifth mask process. In this case, the pixel electrode 130 contacts the drain electrode 118 through the drain contact hole 126 and also contacts the capacitor auxiliary electrode 120 through the capacitor contact hole 127.

The gate pad portion P is formed of the same material as the pixel electrode 130 to form the gate pad electrode 132 in contact with the contact buffer layer 122.

Next, the transflective mask process used to form the photoresist pattern of FIG. 4C will be described in comparison with a general exposure mask process.

5A and 5B are cross-sectional views illustrating a process of forming a photoresist pattern on a substrate using a general exposure mask.

As illustrated, the metal film 150 to form a pattern on the substrate 1 and the array panel 170 in which a positive photoresist film 152 is laminated in this order, An exposure mask 160 composed of only the light transmitting part T and the light blocking part A is configured to be aligned with the array panel 170, and then a light source is applied to the array panel 170 through the exposure mask 160. When irradiated with light, the light source passing through the light transmitting portion T reacts with the photoresist 152, and the exposed photoresist 152 is removed in the developing step, and the array panel 170 is shown in FIG. 5B. ), Only the photoresist 152 at a position corresponding to the light blocking portion A of the exposure mask 160 forms a pattern.

When the photoresist 152 is formed in a predetermined pattern, after curing the pattern of the photoresist 152 at a predetermined temperature, the metal film 150 of the lower layer is etched along the pattern of the photoresist, The photoresist 152 pattern film remaining on the metal film 150 is removed to form a metal pattern film.

In this case, the material of the light blocking film 162 forming the light blocking unit is preferably a chromium-based metal.

6A and 6B are cross-sectional views illustrating a process of forming a photoresist pattern on a substrate using a general transflective mask. As shown in FIG. 6A and 6B, a portion of the array panel 210 having the structure described above with reference to FIG. (I), the transflective mask 200 comprised by the part (II) which passes a part of light, and the part (III) which passes a light completely is positioned.

In this case, a transparent conductive material may be used as the semi-transmissive film 206 constituting part II of the light, and a chromium-based light blocking film 201 constituting the part I that completely blocks light. It is preferable to use a metal. At this time, the amount of light absorption can be finely adjusted by adjusting the thickness of the semi-transmissive film 206 or the light shielding film 201.

The transmissive film 206 and the light shielding film 201 may be doubled in the portion I which completely blocks the light as shown.

6B illustrates a photoresist 252 formed in three patterns having different thicknesses of the array panel 210 formed through exposure and development using the semi-transmissive mask (200 of FIG. 6A).

That is, by using the semi-transmissive mask, the photoresist pattern of FIG. 4C of the present invention is formed, and the I, II, and III portions of FIG. 6B are sequentially formed in the thin film transistor portion (T in FIG. 4C), Corresponds to the pattern of the photoresist (112 in FIG. 4C) of the capacitor electrode portion (C in FIG. 4C) and the gate pad portion (P in FIG. 4C).

The metal film 250 to form a pattern between the photoresist 252 and the substrate 1 of the array panel 210 corresponds to the semiconductor layer 110 (in FIG. 4C) in the present invention.

That is, the process of exposing the upper portion of the gate pad (106 of FIG. 4C) while forming the active layer (111a of FIG. 4C) using the transflective mask 200 is performed by one mask process.

In order to achieve the above object, the mask is not necessarily limited to a transflective mask, and any mask may be used as long as the mask can perform the step of exposing the upper portion of the gate pad while forming the active layer at one time.

As described above, in the array panel for a liquid crystal display device and the manufacturing method thereof according to the present invention, a low-resistance wiring metal material is formed of a gate wiring metal as a single metal layer containing aluminum suitable for high quality of a large area liquid crystal panel, In forming the source and drain metals as the contact buffer layer between aluminum and ITO, a process is not added by using a semi-permeable mask, so that the product yield can be improved while improving the properties of the aluminum.

Claims (8)

A gate wiring made of a single metal layer containing aluminum (Al); A data wiring comprising a source electrode crossing the gate wiring and made of a metal having a lower reducibility than the aluminum, and having a source electrode spaced apart from the drain electrode by a predetermined distance; A thin film transistor including the source and drain electrodes; A pixel electrode connected to the thin film transistor; A gate pad positioned at an end of the gate wiring; A contact buffer layer formed of the same material as the data line on the gate pad; A gate pad electrode in contact with the contact buffer layer and made of the same material as the pixel electrode Array panel for a liquid crystal display device comprising a. The method of claim 1, And a capacitor electrode of the same material as the gate wiring, an insulating layer on the capacitor electrode, and a capacitor auxiliary electrode of the same material as the data wiring between the insulating layer and the pixel electrode. panel. The method of claim 1, And the metal forming the source, drain electrode, and data wiring is one of chromium (Cr), molybdenum (Mo), tungsten (W), titanium (Ti), and indium (In). Preparing a substrate; Forming a gate wiring including a gate electrode and a capacitor electrode as a single metal layer including aluminum (Al) on the substrate, and a gate pad having a predetermined area at an end of the gate wiring by a first mask process; Wow; Continuously depositing a gate insulating film and a semiconductor layer on an entire surface of the substrate on which the gate wiring is formed; Forming an active layer on the gate electrode by a second mask process and simultaneously exposing an upper portion of the gate pad; Depositing a metal layer having a lower reducibility than aluminum on the substrate on which the active layer is formed, and then forming a contact buffer layer on the source, drain electrode and the gate pad, respectively, on the active layer by a third mask process; Forming a protective layer on the substrate on which the source and drain electrodes are formed and forming a drain contact hole and a gate pad contact hole by a fourth mask process; Depositing ITO on the substrate on which the drain contact hole is formed, a pixel electrode contacting the drain electrode through the drain contact hole through a fifth mask process, and a gate pad electrode contacting the contact buffer layer through the gate pad contact hole Forming steps Method of manufacturing an array panel for a liquid crystal display device comprising a. The method of claim 4, wherein The second mask process uses a transflective mask having an opaque region, a transflective region, and a full transmissive region, wherein the opaque region corresponds to the active layer and the fully transmissive region corresponds to the gate pad portion. A method of manufacturing an array panel for a liquid crystal display device. The method of claim 4, wherein The semi-transmissive mask is a method of manufacturing an array panel for a liquid crystal display device that arbitrarily adjusts the thickness of the photo resist on the substrate by controlling the transmittance of light using a metal film containing chromium (Cr) and a transparent conductive material film. . The method of claim 4, wherein And removing only a semiconductor layer on the capacitor electrode in the second mask process, and forming a capacitor auxiliary electrode on the capacitor electrode using the same metal layer as the source and drain electrodes. Method of manufacturing an array panel for use. The method of claim 4, wherein The metal forming the source and drain electrodes is one of chromium (Cr), molybdenum (Mo), tungsten (W), titanium (Ti), and indium (In).

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