KR101252000B1 - Thin film transistor panel and manufacturing method thereof - Google Patents
Thin film transistor panel and manufacturing method thereof Download PDFInfo
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- KR101252000B1 KR101252000B1 KR1020060053883A KR20060053883A KR101252000B1 KR 101252000 B1 KR101252000 B1 KR 101252000B1 KR 1020060053883 A KR1020060053883 A KR 1020060053883A KR 20060053883 A KR20060053883 A KR 20060053883A KR 101252000 B1 KR101252000 B1 KR 101252000B1
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Abstract
According to an embodiment of the present invention, a contact hole is formed at the same time as the contact auxiliary member is formed with the semiconductor, and the gate pad or gate layer signal transmission line of the aluminum-based metal exposed through the contact hole is made of the same material as the data line. By covering and protecting with a contact medium member to be made, or by directly connecting with the data layer signal transmission line, it is possible to prevent the ITO or IZO and aluminum-based metals in direct contact, effectively preventing corrosion of aluminum or aluminum alloy by direct contact. . In addition, the manufacturing cost of the thin film transistor array panel can be reduced by patterning the semiconductor, the contact auxiliary member, the data line, and the like using one mask.
Gate line, aluminum, ITO, corrosion, contact media reinforcing member, gate layer signal line, data layer signal line
Description
1 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention.
FIG. 2 is a cross-sectional view of the thin film transistor array panel of FIG. 1 taken along the line II-II'-II ''-II '' ',
3 is a layout view of a thin film transistor array panel according to another exemplary embodiment of the present invention.
FIG. 4 is a cross-sectional view of the thin film transistor array panel of FIG. 3 taken along the line IV-IV'-IV ''-IV '' '.
5, 7, 10, and 12 are layout views sequentially showing thin film transistor array panels at an intermediate stage of a method of manufacturing the thin film transistor array panels shown in FIGS. 1 and 2 according to an embodiment of the present invention;
FIG. 6 is a cross-sectional view of the thin film transistor array panel of FIG. 5 taken along the line VI-VI′-VI ″ -VI ′ ″.
FIG. 8 is a cross-sectional view of the thin film transistor array panel of FIG. 7 taken along a line VIII-VIII'-VIII ''-VIII '' ',
9A through 9F are cross-sectional views illustrating a process of forming an intermediate structure of the TFT panel shown in FIGS. 7 and 8.
FIG. 11 is a cross-sectional view of the thin film transistor array panel of FIG. 10 taken along the line XI-XI′-XI ″ -XI ′ ″.
FIG. 13 is a cross-sectional view of the thin film transistor array panel of FIG. 12 taken along the line XIII-XIII'-XIII ''-XIII '' ',
14 and 17 are layout views showing the thin film transistor array panel at an intermediate stage of the method of manufacturing the thin film transistor array panel illustrated in FIGS. 3 and 4 according to another embodiment of the present invention;
FIG. 15 is a cross-sectional view of the thin film transistor array panel of FIG. 14 taken along the line XV-XV′-XV ″ -XV ′ ″.
16A through 16F are cross-sectional views illustrating a process of forming an intermediate structure of the thin film transistor array panel illustrated in FIGS. 14 and 15.
FIG. 18 is a cross-sectional view of the thin film transistor array panel of FIG. 17 taken along the lines XVIII-XVIII'-XVIII ''-XVIII '' ',
19 is a layout view of a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention.
20 is a cross-sectional view of the thin film transistor array panel of FIG. 19 taken along a line XX-XX'-XX ''-XX '' '.
21, 23 and 26 are layout views showing the thin film transistor array panel at an intermediate stage of the method for manufacturing the thin film transistor array panel shown in FIGS. 19 and 20 according to an embodiment of the present invention;
FIG. 22 is a cross-sectional view of the thin film transistor array panel of FIG. 21 taken along a line XXII-XXII'-XXII ''-XXII '' '.
FIG. 24 is a cross-sectional view of the thin film transistor array panel of FIG. 23 taken along a line XXIV-XXIV'-XXIV ''-XXIV '' '.
25A to 25F are cross-sectional views illustrating a process of forming an intermediate structure of the thin film transistor array panel illustrated in FIGS. 23 and 24.
FIG. 27 is a cross-sectional view of the thin film transistor array panel of FIG. 26 taken along the line XXVII-XXVII'-XXVII ''-XXVII '' ',
28 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.
FIG. 29 is an example of a layout view of a portion of a display area in the thin film transistor array panel of the liquid crystal display illustrated in FIG. 28.
FIG. 30 is an example of a layout view illustrating a portion of a driving region in the thin film transistor array panel of the liquid crystal display illustrated in FIG. 28.
FIG. 31 is a cross-sectional view of the thin film transistor array panel of FIGS. 30 and 2930 taken along a line XXXI-XXXI'-XXXI ''-XXXI '' ',
32, 33, 35, and 36 are cross-sectional views of a thin film transistor array panel at an intermediate stage of a method of manufacturing the thin film transistor array panel illustrated in FIG. 31 according to an embodiment of the present invention;
34A through 34F are cross-sectional views illustrating a process of forming an intermediate structure of the thin film transistor array panel of FIG. 33.
FIG. 37 is another example of the layout view of a portion of the display area of the thin film transistor array panel of the liquid crystal display illustrated in FIG. 28.
FIG. 38 is another example of a layout view illustrating a portion of a driving region in the thin film transistor array panel of the liquid crystal display illustrated in FIG. 28.
FIG. 39 is a cross-sectional view of the layout views of FIGS. 38 and 38 taken along a line XXXIX-XXXIX'-XXXIX``-XXXIX '' '.
≪ Description of reference numerals &
60.Exposure Mask 61: Substrate
62: opaque member
81, 82 ...
110 ... substrate
121 Gate
125, 126, 127, 128 ... gate layer signal line
129 ... gate pad
131
140 gate insulating film
141, 142a-142c, 181, 182, 183a, 183b, 185 ... contact hole
150.Intrinsic Amorphous Silicon Layer
151, 154, 156a, 156b, 158 ... semiconductor
160.Impurity amorphous silicon layer
161, 163, 165, 166a, 166b, 168 ... resistive contact members
164: impurity semiconductor
171
173 Source electrode 174: data conductor
175
178 ... Contact
180 ... Shield
191
The present invention relates to a thin film transistor array panel for a liquid crystal display device and a manufacturing method thereof.
In general, a liquid crystal display device includes a liquid crystal layer positioned between a field generating electrode and a pair of display panels provided with a polarizing plate. The field generating electrode generates an electric field in the liquid crystal layer and the arrangement of liquid crystal molecules changes as the intensity of the electric field changes. For example, the liquid crystal molecules of the liquid crystal layer in the state in which the electric field is applied to change the polarization of the light passing through the liquid crystal layer. The polarizer displays a desired image by appropriately blocking or transmitting polarized light to create bright and dark areas.
Such a liquid crystal display includes a pixel including a switching element, a display panel having a display signal line, and a gate driver having a plurality of stages that turn on / off a switching element of a pixel by sending a gate signal to a gate line among the display signal lines. do.
A gate on / off voltage, a clock signal, and the like are input to the stage of the gate driver, and these signals are supplied to a signal line connected to one side of each stage.
The gate driver may be directly integrated on the substrate. In this case, the gate line may be extended to be directly connected to the substrate. At this time, in order to connect the gate wiring of the gate driver and the data wiring to each other, a contact hole that exposes the gate wiring is formed, and the gate wiring and the data wiring are connected through the contact hole using a connecting member made of ITO or the like.
On the other hand, when the gate driver is formed outside the substrate, in order to supply the gate on / off voltage to the stage of the gate driver, a pad unit connecting the on / off signal line and each stage of the gate driver is required. At this time, in order to connect the pad portion and the signal line, a contact hole exposing the signal line is formed, and each stage of the signal line and the gate driver is connected through the contact hole using a connection member made of ITO or the like.
On the other hand, as the area of the display device increases, the signal line becomes longer and the resistance increases accordingly. As the resistance increases, problems such as signal delay or voltage drop may occur. To solve this problem, it is necessary to form a signal line with a material having a low specific resistance.
One of the materials with low resistivity is an alloy containing aluminum (Al), and generally forms a signal line in the form of a multilayer with other metals.
However, when the signal line including aluminum contacts the pixel electrode of the display device or the ITO used as the connecting member, the aluminum may be oxidized and corroded.
Accordingly, an object of the present invention is to solve this problem, and to provide a liquid crystal display device and a method of manufacturing the same, which can prevent oxidation and corrosion caused by contact between a signal line or gate pad part including aluminum and ITO. It is.
A thin film transistor array panel according to an exemplary embodiment of the present invention includes a gate insulating film having a substrate, a first signal line formed on the substrate, and a first contact hole formed on the first signal line and exposing a portion of the first signal line. A first semiconductor formed on the gate insulating film, a second signal line formed on the first semiconductor, a drain electrode formed on the first semiconductor and spaced apart from the second signal line, and formed on the gate insulating film, A protective layer having a conductor connected to the first signal line through the first contact hole, the second signal line, the drain electrode, and a second contact hole formed on the conductor and exposing the drain electrode; And a drain electrode formed through the second contact hole. It may include a pixel electrode that is determined.
The thin film transistor array panel further includes a third contact hole in which the passivation layer exposes a portion of the conductor, and the thin film transistor array panel is formed on the passivation layer and is connected to the conductor through the third contact hole. The semiconductor device may further include a member, and the first signal line may include a gate electrode positioned below the first semiconductor.
The thin film transistor array panel further includes a third signal line formed under the gate insulating layer, the third signal line including a gate electrode disposed under the first semiconductor, and a gate driving circuit connected to the conductor and the third signal line. can do.
The thin film transistor array panel further includes a second semiconductor formed between the exposed portion of the first signal line and the conductor, the second semiconductor having a fourth contact hole aligned with the first contact hole, The conductor may be connected to the first signal line through the first and fourth contact holes.
The planar shape of the second semiconductor may be substantially the same as the planar shape of the conductor except for the fourth contact hole.
The first semiconductor may extend along the second signal line and the drain electrode, and the planar shape of the second signal line and the drain electrode may be substantially the same as the planar shape of the first semiconductor portion underlying it.
The thin film transistor array panel may further include a storage electrode formed of the same layer as the first signal line and overlapping the pixel electrode, and a third semiconductor formed on the storage electrode on the gate insulating layer.
The first signal line may include a first conductive layer made of aluminum or an aluminum alloy.
The first signal line may further include a second conductive layer disposed under the first conductive layer and made of chromium, molybdenum, chromium alloy, or molybdenum alloy.
An exposed portion of the first signal line exposed through the first contact hole may not include the first conductive layer.
The first contact hole may expose a boundary of the first signal line.
A method of manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention may include forming a first signal line on a substrate, laminating a gate insulating film on the first signal line, laminating an intrinsic amorphous silicon layer on the gate insulating film, Stacking an impurity amorphous silicon layer on the amorphous silicon layer, forming a photoresist film having a different thickness depending on a position on the impurity amorphous silicon layer and exposing a first portion of the impurity amorphous silicon layer, using the photoresist as a mask Patterning the impurity amorphous silicon layer, the intrinsic amorphous silicon layer, and the gate insulating film to form an impurity semiconductor and an intrinsic semiconductor, and simultaneously forming a first contact hole in the gate insulating film to expose a portion of the first signal line; A second signal line and a drain electrode are formed on the impurity semiconductor. And forming a conductor connected to the first signal line through the first contact hole, and having a second contact hole exposing a portion of the drain electrode on the data line, the drain electrode, and the conductor. Forming a passivation layer; and forming a pixel electrode connected to the drain electrode through the second contact hole on the passivation layer.
The forming of the impurity semiconductor, the intrinsic semiconductor, and the first contact hole may include etching and removing the first portion of the impurity amorphous silicon layer, the portion of the intrinsic amorphous silicon layer and the gate insulating layer below the photoresist as an etch mask. Reducing the thickness of the photoresist film to expose a second portion of the impurity amorphous silicon layer, removing the second portion of the impurity amorphous silicon layer and the portion of the intrinsic amorphous silicon layer below it, and the photoresist film It may include the step of removing.
The forming of the photoresist film includes applying the photoresist film and exposing the photoresist film through a mask having a light transmission region, a semi-transmission region, and a light shielding region, wherein the light transmission region is a first layer of the impurity amorphous silicon layer. And a semi-transmissive region may correspond to a second portion of the impurity amorphous silicon layer.
The first contact hole may be located under the first portion of the impurity amorphous silicon layer.
The first signal line may include a first conductive layer made of aluminum or an aluminum alloy.
The first signal line is made of chromium, molybdenum, chromium alloy, or molybdenum alloy, and includes a second conductive layer disposed below the first conductive layer, and after forming the first contact hole, through the first contact hole The method may further include removing the exposed first conductive layer portion of the first signal line portion.
The passivation layer may further have a third contact hole exposing a portion of the conductor, and the forming of the pixel electrode may include forming a contact auxiliary member connected to the conductor through the third contact hole.
According to another exemplary embodiment of the present disclosure, a method of manufacturing a thin film transistor array panel includes forming a first signal line on a substrate, stacking a gate insulating film on the first signal line, and stacking an intrinsic amorphous silicon layer on the gate insulating film. Stacking an impurity amorphous silicon layer on the amorphous silicon layer, etching the impurity amorphous silicon layer, the intrinsic amorphous silicon layer, and the gate insulating layer to form a first contact hole exposing a portion of the first signal line; Stacking a conductive layer on the impurity silicon layer, stacking a photosensitive film having a different thickness depending on a position on the conductive layer, and using the photosensitive film as a mask to form the conductive layer, the impurity amorphous silicon layer and the intrinsic amorphous silicon layer. A patterning pattern connected to the first signal line through the first contact hole Forming a sieve, a second signal line and a drain electrode, and a contact auxiliary member and a semiconductor thereunder; a protective film having a second contact hole exposing a portion of the drain electrode on the data line, the drain electrode, and the conductor; And forming a pixel electrode connected to the drain electrode through the second contact hole on the passivation layer.
The passivation layer may further have a third contact hole exposing a portion of the conductor, and the forming of the pixel electrode may include forming a contact auxiliary member connected to the conductor through the third contact hole.
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.
In the drawings, the thickness is enlarged to clearly represent the layers and regions. Like parts are designated with like reference numerals throughout the specification. Whenever a portion of a layer, film, region, plate, or the like is referred to as being "on" another portion, it includes not only the case where it is "directly on" another portion, but also the case where there is another portion in between. Conversely, when a part is "directly over" another part, it means that there is no other part in the middle.
Next, a thin film transistor array panel according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.
1 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view of the thin film transistor array panel of FIG. 1 taken along a line II-II'-II ''-II '' '.
A plurality of
The
The
The
However, the
In FIG. 2, for the
Side surfaces of the
A
On the
A plurality of linear and island ohmic
Side surfaces of the
A plurality of
The
The
One
The
The
The
The
A passivation layer 180 is formed on the
The passivation layer 180 is formed with a plurality of
A plurality of
The
The
The connecting
The contact
The
Next, a thin film transistor array panel according to another exemplary embodiment of the present invention will be described with reference to FIGS. 3 and 4. 3 is a layout view of a thin film transistor array panel according to another exemplary embodiment of the present invention, and FIG. 4 is a cross-sectional view of the thin film transistor array panel of FIG. 3 taken along line IV-IV'-IV ''-IV '' '. .
The layer structure of the thin film transistor array panel according to the present embodiment is substantially the same as that shown in FIGS. 1 and 2.
A plurality of
A plurality of
However, unlike the thin film transistor array panel shown in FIGS. 1 and 2, the upper layer 129q of the portion exposed through the
As such, when the upper layer 129q of the
Various features of the thin film transistor array panel illustrated in FIGS. 1 and 2 may also be applied to the thin film transistor array panel illustrated in FIGS. 3 and 4.
Next, a method of manufacturing the thin film transistor array panel illustrated in FIGS. 1 and 2 according to an embodiment of the present invention will be described in detail with reference to FIGS. 5 to 13.
5, 7, 10, and 12 are layout views of a thin film transistor array panel at an intermediate stage of a method of manufacturing the thin film transistor array panel illustrated in FIGS. 1 and 2 according to an embodiment of the present invention. 5 is a cross-sectional view of the thin film transistor array panel of FIG. 5 taken along the line VI-VI'-VI ''-VI '' ', and FIG. 8 is a VIII-VIII'-VIII' '-VIII' of the thin film transistor array panel of FIG. 11 is a cross-sectional view taken along the line XI-XI'-XI ''-XI '' ', and FIG. 13 is a thin film of FIG. 9 is a cross-sectional view illustrating a transistor panel cut along a line XIII-XIII'-XIII ''-XIII '' ', and FIGS. 9A to 9F illustrate step-by-step processes of forming the TFT panel shown in FIGS. 7 and 8. It is a cross section.
5 and 6, a lower conductive film made of chromium, chromium-nitrogen alloy, molybdenum, or the like is laminated on the insulating
Next, referring to FIGS. 7 and 8, the
Next, a process of forming the intermediate structure of the thin film transistor array panel illustrated in FIGS. 7 and 8 will be described in detail with reference to FIGS. 9A to 9F.
Referring to FIG. 9A, the
The
The exposure mask 60 includes a
In the translucent region B, an opaque member 62 having a predetermined value, for example, a width less than or equal to the resolution of the exposure machine, is disposed at intervals less than or equal to the predetermined value, which is called a slit pattern. The light-transmitting region A is a region without the opaque member 62 at all and has a width greater than or equal to a predetermined value, and the light-shielding region C is a region covered with the opaque member 62 as a whole and has a width greater than or equal to the predetermined value.
Instead of providing a slit pattern in the translucent region B, a lattice pattern or a thin film having a medium transmittance or a medium thickness may be provided.
As shown in FIG. 9B, when the
At this time, the ratio of the thickness of the
As another example of the method of varying the thickness of the photoresist film, a photoresist film capable of reflow is used. That is, a thin portion is formed by forming a reflowable photosensitive film with a conventional mask having only a light transmitting area and a light blocking area, and then reflowing to allow the photosensitive film to flow down to a region in which no light remains.
Next, as shown in FIG. 9C, the impurity
Next, referring to FIG. 9D, the
Thereafter, as shown in FIG. 9E, the impurity
Finally, as shown in FIG. 9F, portions of the
As such, the
Next, referring to FIGS. 10 and 11, a plurality of
Subsequently, an exposed portion of the
12 and 13, the passivation layer 180 is laminated and patterned together with the
Lastly, as shown in FIGS. 1 and 2, the ITO or IZO, etc. are stacked on the passivation layer 180 by sputtering, and photo-etched to remove the plurality of
Next, a method of manufacturing the thin film transistor array panel illustrated in FIGS. 3 and 4 according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 14 to 18.
14 and 17 are layout views of a thin film transistor array panel at an intermediate stage of a method of manufacturing the thin film transistor array panel shown in FIGS. 3 and 4 according to an embodiment of the present invention, and FIG. 18 is a cross-sectional view of the display panel taken along the lines XV-XV'-XV ''-XV '' ', and FIG. 18 is a cross-sectional view of the thin film transistor display panel of FIG. 17 taken along the line XVIII-XVIII'-XVIII' '-XVIII' ''. 16A to 16F are cross-sectional views illustrating a process of forming the thin film transistor array panel illustrated in FIGS. 14 and 15.
First, as shown in FIGS. 14 and 15, the lower conductive film and the upper conductive film are sequentially stacked and photo-etched to form a plurality of
Subsequently, the
Next, a process of forming the intermediate structure of the thin film transistor array panel illustrated in FIGS. 14 and 15 will be described in detail with reference to FIGS. 16A to 16F.
Referring to FIG. 16A, the
Thereafter, as shown in FIG. 16B, when the
Next, as shown in FIG. 16C, the impurity
Next, as shown in FIG. 16D, the
Thereafter, the impurity
Finally, as shown in FIG. 16F, portions of the
As such, the
Next, the metal layers are sputtered and photo-etched to form a plurality of
Then, as shown in Figs. 17 and 18, after the protective film 180 is laminated, a plurality of contact holes 181, 182, 183a, 183b, and 185 are formed by patterning by photo (etching) or the like. .
3 and 4, a plurality of
Next, a thin film transistor array panel for a liquid crystal display according to another exemplary embodiment of the present invention will be described in detail with reference to FIGS. 19 and 20.
19 is a layout view of a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 20 is a cross-sectional view of the thin film transistor array panel of FIG. 19 taken along a line XX-XX'-XX ''-XX '' '. One cross section.
The layered structure of the thin film transistor array panel according to the present embodiment is similar to the thin film transistor array panel according to the embodiments shown in FIGS. 1 and 2.
A plurality of
A plurality of
However, unlike the thin film transistor array panels shown in FIGS. 1 and 2, the thin film transistor array panels illustrated in FIGS. 19 and 20 are disposed on the sustain
Further, an island-type ohmic contact member 168 and an island-shaped semiconductor 158 are formed below the
The
The
The
The passivation layer 180 has a double layer structure of the lower inorganic layer 180p and the upper organic layer 180q, and the surface of the upper organic layer 180q is flat.
Various features of the thin film transistor array panel illustrated in FIGS. 1 and 2 may be applied to the thin film transistor array panel illustrated in FIGS. 19 and 20.
Next, a method of manufacturing the thin film transistor array panel illustrated in FIGS. 19 and 20 according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 21 to 27.
21, 23 and 26 are layout views of the thin film transistor array panel at an intermediate stage of the method of manufacturing the thin film transistor array panel shown in FIGS. 19 and 20 according to an embodiment of the present invention, and FIG. FIG. 24 is a cross-sectional view of the thin film transistor array panel taken along the line XXII-XXII'-XXII ''-XXII '' ', and FIG. 24 is a line XXIV-XXIV'-XXIV' '-XXIV' '' of the thin film transistor array panel of FIG. FIG. 27 is a cross-sectional view of the thin film transistor array panel of FIG. 26 taken along a line XXVII-XXVII'-XXVII``-XXVII '' ', and FIGS. 25A to 25F are FIGS. 23 and 25. 24 is a cross-sectional view illustrating the process of forming the thin film transistor array panel illustrated in FIG. 24.
First, as shown in FIGS. 21 and 22, an aluminum alloy such as aluminum (Al) or aluminum-neodymium alloy (AlNd), or the like is laminated on the insulating
Next, referring to FIGS. 23 and 24, the
Next, a method of forming an intermediate structure of the thin film transistor array panel illustrated in FIGS. 23 and 24 will be described in detail with reference to FIGS. 25A to 25F.
As shown in FIG. 25A, the
Next, as shown in FIG. 25C, after the data conductive layer 170 is laminated by a method such as sputtering, a photosensitive film 410 is formed as shown in FIG. 25D.
At this time, referring to FIG. 25D, the thickness of the photoresist film 410 varies depending on the position. The thickness of the photoresist film 410 is the thickest in the light shielding region F, and in the light shielding region F in the translucent region E It is thinner and there is no photosensitive film in the transmissive area D.
Referring to FIG. 25E, a plurality of
Subsequently, as shown in FIG. 25F, the photosensitive film 410 is ashed to remove the portion of the
Thereafter, the
Finally, by removing the exposed portion of the
Referring to FIGS. 26 and 27, after forming the passivation layer 180 including the lower inorganic layer 180p and the upper organic layer 180q, the plurality of contact holes may be photo-etched together with the
Finally, as illustrated in FIGS. 19 and 20, a plurality of
A liquid crystal display according to another exemplary embodiment of the present invention will now be described with reference to FIG. 28.
28 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.
As shown in FIG. 28, the liquid crystal display according to the exemplary embodiment of the present invention includes a liquid
The liquid
The display area DA includes a plurality of gate lines G1 -Gn, a plurality of data lines D1 -Dm, a plurality of sustain electrode lines (not shown), a plurality of pixel electrodes (not shown), and a plurality of thin film transistors. Etc. are formed.
In the driving area CA, a gate driver for generating a gate signal and a plurality of signal transmission lines (not shown) for transmitting various signals from the outside to the gate driver are formed. The gate driver may be a shift register including a plurality of stages (not shown) connected in turn.
An example of the thin film transistor array panel of the liquid crystal display shown in FIG. 28 will be described in detail with reference to FIGS. 29 to 31.
FIG. 29 is an example of a layout view of a portion of a display area in the thin film transistor array panel of the liquid crystal display illustrated in FIG. 28, and FIG. 30 illustrates a portion of a driving region in the thin film transistor array panel of the liquid crystal display illustrated in FIG. 28. FIG. 31 is a cross-sectional view of the thin film transistor array panel of FIGS. 30 and 29 taken along the line XXXI-XXXI'-XXXI ''-XXXI '' '.
Since the display unit DA has a stacked structure similar to that shown in FIGS. 1 and 2, the display unit DA will be described in detail with reference to the driving area CA.
Referring to FIG. 30, a plurality of circuit parts 610 (corresponding to one stage of a shift register) generating a gate signal and a plurality of signal transmission lines transmitting various signals to the
Next, the specific layer structure of the thin film transistor array panel will be described in detail.
A plurality of
Each
The gate layer signal transmission lines 125-128 are required to drive the
The
The
On the
On the
Each
Like the gate layer signal transmission lines 125-128, the data layer
The passivation layer 180 is formed on the
A plurality of
As described above, the thin film transistor and the connection line are formed in the
As such, the gate layer
Various features of the thin film transistor array panel illustrated in FIGS. 1 and 2 may also be applied to the thin film transistor array panels illustrated in FIGS. 29 to 31.
Next, a method of manufacturing the thin film transistor array panel illustrated in FIGS. 29 to 31 will be described in detail with reference to FIGS. 32 to 36.
32, 33, 35, and 36 are cross-sectional views at intermediate stages of a method of manufacturing the thin film transistor array panel shown in FIGS. 29 to 31 according to an embodiment of the present invention, and FIGS. 34A to 34F are FIGS. 33 is a cross-sectional view illustrating a process of forming the thin film transistor array panel of FIG. 33.
Referring to FIG. 32, a plurality of
Next, as shown in FIG. 33, the
Next, a process of forming the intermediate structure of the thin film transistor array panel illustrated in FIG. 33 will be described in detail with reference to FIGS. 34A to 34F.
Referring to FIG. 34A, the
As shown in FIG. 34B, when the
Next, as shown in FIG. 34C, the impurity
Next, referring to FIG. 34D, the
Thereafter, as shown in FIG. 34E, the impurity
Finally, as shown in FIG. 34F, a portion of the
Next, referring to FIG. 35, a plurality of
Subsequently, an exposed portion of the
As shown in FIG. 36, the passivation layer 180 is stacked and patterned together with the
Finally, as illustrated in FIGS. 29 and 31, a plurality of
FIG. 37 is another example of a layout view of a portion of the display area of the thin film transistor array panel of the liquid crystal display of FIG. 28, and FIG. 38 is a diagram illustrating a driving area of the thin film transistor array panel of the liquid crystal display of FIG. 28. FIG. 39 is a cross-sectional view of the thin film transistor array panel of FIGS. 38 and 37 taken along the line XXXIX-XXXIX'-XXXIX ''-XXXIX '' '.
The layer structure of the thin film transistor array panel according to the present embodiment is similar to the embodiment shown in FIGS. 29 to 31.
In the driving region CA, a plurality of
A plurality of
The
A plurality of
On the
Each
A passivation layer 180 is formed on the
The passivation layer 180 may have a double layer structure of the lower inorganic layer 180p and the upper organic layer 180q, and the surface of the upper organic layer 180q may be flat. However, the passivation layer 180 may be formed of a single layer.
A plurality of
However, unlike the thin film transistor array panels shown in FIGS. 29 to 31, the thin film transistor array panels illustrated in FIGS. 37 to 39 are disposed on the sustain
Various features of the thin film transistor array panel illustrated in FIGS. 29 to 31 may also be applied to the thin film transistor array panels illustrated in FIGS. 3 to 39.
The manufacturing method of the thin film transistor array panel according to the present embodiment is similar to the manufacturing method of the thin film transistor array panel shown in FIGS. 21 to 27.
However, the gate layer signal transmission lines 125-128 are formed in the same step as the
As described above, a contact hole is formed in which a contact hole is formed in the semiconductor and a contact hole is formed in the gate insulating film, and the gate pad or gate layer signal transmission line of the aluminum-based metal exposed through the contact hole is made of the same material as the data line. By covering and protecting the member or directly connecting the data layer signal transmission line, the ITO or IZO and the aluminum-based metal can be prevented from directly contacting each other, thereby effectively preventing corrosion of the aluminum or aluminum alloy by the direct contact. In addition, the manufacturing cost of the thin film transistor array panel can be reduced by patterning the semiconductor, the contact auxiliary member, the data line, and the like using one mask.
Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.
Claims (20)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007025068A JP4921997B2 (en) | 2006-02-07 | 2007-02-05 | Thin film transistor display panel and manufacturing method thereof |
US11/671,727 US7675065B2 (en) | 2006-02-07 | 2007-02-06 | Thin film transistor panel and manufacturing method thereof |
CN2007100923045A CN101017835B (en) | 2006-02-07 | 2007-02-07 | Thin film transistor panel and manufacturing method thereof |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
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KR20060011459 | 2006-02-07 | ||
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CN106292171A (en) * | 2015-05-29 | 2017-01-04 | 鸿富锦精密工业(深圳)有限公司 | The manufacture method of electric connection structure, array base palte and insulating cover |
CN104865765B (en) * | 2015-06-19 | 2018-10-30 | 合肥鑫晟光电科技有限公司 | Array substrate and production method, display panel and production method and display device |
CN105070719A (en) * | 2015-07-10 | 2015-11-18 | 深圳市华星光电技术有限公司 | Thin film transistor array substrate and manufacturing method thereof |
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KR19990049196A (en) * | 1997-12-12 | 1999-07-05 | 구자홍 | Liquid Crystal Display Manufacturing Method |
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JP3119228B2 (en) * | 1998-01-20 | 2000-12-18 | 日本電気株式会社 | Liquid crystal display panel and method of manufacturing the same |
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KR100579192B1 (en) * | 2004-03-11 | 2006-05-11 | 삼성에스디아이 주식회사 | Top-emission type organic electro luminescence display device and method for fabricating of the same |
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KR19990049196A (en) * | 1997-12-12 | 1999-07-05 | 구자홍 | Liquid Crystal Display Manufacturing Method |
KR20020031764A (en) * | 2000-10-24 | 2002-05-03 | 구본준, 론 위라하디락사 | Array Panel used for a Liquid Crystal Display and Method for Fabricating the same |
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