KR20070080540A - Thin film transistor panel and manufacturing method thereof - Google Patents

Abstract

A TFT is provided to effectively prevent aluminum or aluminum alloy from being corroded by preventing a direct contact of ITO(indium tin oxide) or IZO(indium zinc oxide) and aluminum-based metal. A first signal line is formed on a substrate(110). A gate insulation layer(140) is formed on the first signal line, having a first contact hole exposing a part of the first signal line. A first semiconductor is formed on the gate insulation layer. A second signal line is formed on the first semiconductor. A drain electrode(175) is formed on the first semiconductor, separated from the second signal line. A conductor is formed on the gate insulation layer, connected to the first signal line through the first contact hole. A passivation layer(180) is formed on the second signal line, the drain electrode and the conductor, having a second contact hole exposing the drain electrode. A pixel electrode(191) is formed on the passivation layer, connected to the drain electrode through the second contact hole. A second semiconductor can be formed between the exposed part of the first signal line and the conductor, including a fourth contact hole aligned with the first contact hole. The conductor can be connected to the first signal line through the first and fourth contact holes.

Description

Thin film transistor array panel and manufacturing method therefor {THIN FILM TRANSISTOR PANEL AND MANUFACTURING METHOD THEREOF}

1 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view of the thin film transistor array panel of FIG. 1 taken along the line II-II'-II ''-II '' ',

3 is a layout view of a thin film transistor array panel according to another exemplary embodiment of the present invention.

FIG. 4 is a cross-sectional view of the thin film transistor array panel of FIG. 3 taken along the line IV-IV'-IV ''-IV '' '.

5, 7, 10, and 12 are layout views sequentially showing thin film transistor array panels at an intermediate stage of a method of manufacturing the thin film transistor array panels shown in FIGS. 1 and 2 according to an embodiment of the present invention;

FIG. 6 is a cross-sectional view of the thin film transistor array panel of FIG. 5 taken along the line VI-VI′-VI ″ -VI ′ ″.

FIG. 8 is a cross-sectional view of the thin film transistor array panel of FIG. 7 taken along a line VIII-VIII'-VIII ''-VIII '' ',

9A through 9F are cross-sectional views illustrating a process of forming an intermediate structure of the TFT panel shown in FIGS. 7 and 8.

FIG. 11 is a cross-sectional view of the thin film transistor array panel of FIG. 10 taken along the line XI-XI′-XI ″ -XI ′ ″.

FIG. 13 is a cross-sectional view of the thin film transistor array panel of FIG. 12 taken along the line XIII-XIII'-XIII ''-XIII '' ',

14 and 17 are layout views showing the thin film transistor array panel at an intermediate stage of the method of manufacturing the thin film transistor array panel illustrated in FIGS. 3 and 4 according to another embodiment of the present invention;

FIG. 15 is a cross-sectional view of the thin film transistor array panel of FIG. 14 taken along the line XV-XV′-XV ″ -XV ′ ″.

16A through 16F are cross-sectional views illustrating a process of forming an intermediate structure of the thin film transistor array panel illustrated in FIGS. 14 and 15.

FIG. 18 is a cross-sectional view of the thin film transistor array panel of FIG. 17 taken along the lines XVIII-XVIII'-XVIII ''-XVIII '' ',

19 is a layout view of a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention.

20 is a cross-sectional view of the thin film transistor array panel of FIG. 19 taken along a line XX-XX'-XX ''-XX '' '.

21, 23 and 26 are layout views showing the thin film transistor array panel at an intermediate stage of the method for manufacturing the thin film transistor array panel shown in FIGS. 19 and 20 according to an embodiment of the present invention;

FIG. 22 is a cross-sectional view of the thin film transistor array panel of FIG. 21 taken along a line XXII-XXII'-XXII ''-XXII '' '.

FIG. 24 is a cross-sectional view of the thin film transistor array panel of FIG. 23 taken along a line XXIV-XXIV'-XXIV ''-XXIV '' '.

25A to 25F are cross-sectional views illustrating a process of forming an intermediate structure of the thin film transistor array panel illustrated in FIGS. 23 and 24.

FIG. 27 is a cross-sectional view of the thin film transistor array panel of FIG. 26 taken along the line XXVII-XXVII'-XXVII ''-XXVII '' ',

28 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 29 is an example of a layout view of a portion of a display area in the thin film transistor array panel of the liquid crystal display illustrated in FIG. 28.

FIG. 30 is an example of a layout view illustrating a portion of a driving region in the thin film transistor array panel of the liquid crystal display illustrated in FIG. 28.

FIG. 31 is a cross-sectional view of the thin film transistor array panel of FIGS. 30 and 2930 taken along a line XXXI-XXXI'-XXXI ''-XXXI '' ',

32, 33, 35, and 36 are cross-sectional views of a thin film transistor array panel at an intermediate stage of a method of manufacturing the thin film transistor array panel illustrated in FIG. 31 according to an embodiment of the present invention;

34A through 34F are cross-sectional views illustrating a process of forming an intermediate structure of the thin film transistor array panel of FIG. 33.

FIG. 37 is another example of the layout view of a portion of the display area of the thin film transistor array panel of the liquid crystal display illustrated in FIG. 28.

FIG. 38 is another example of a layout view illustrating a portion of a driving region in the thin film transistor array panel of the liquid crystal display illustrated in FIG. 28.

FIG. 39 is a cross-sectional view of the layout views of FIGS. 38 and 38 taken along a line XXXIX-XXXIX'-XXXIX``-XXXIX '' '.

<Description of Drawing>

60.Exposure Mask 61: Substrate

62: opaque member

81, 82 ... contact aid member 83 ... connection leg

110 ... substrate

121 Gate gate 124 Gate electrode

125, 126, 127, 128 ... gate layer signal line

129 ... gate pad

131 Holding electrodes 133a, 133b Holding electrodes

140 gate insulating film

141, 142a-142c, 181, 182, 183a, 183b, 185 ... contact hole

150.Intrinsic Amorphous Silicon Layer

151, 154, 156a, 156b, 158 ... semiconductor

160.Impurity amorphous silicon layer

161, 163, 165, 166a, 166b, 168 ... resistive contact members

164: impurity semiconductor

171 Data line 172a-172c Data layer signal line

173 Source electrode 174: data conductor

175 Drain electrode 176a, 176b reinforcing member

178 ... Contact media member 179 ... Data pad

180 ... Shield

191 pixel electrodes 400, 410 photoresist

The present invention relates to a thin film transistor array panel for a liquid crystal display device and a manufacturing method thereof.

In general, a liquid crystal display device includes a liquid crystal layer positioned between a field generating electrode and a pair of display panels provided with a polarizing plate. The field generating electrode generates an electric field in the liquid crystal layer and the arrangement of liquid crystal molecules changes as the intensity of the electric field changes. For example, the liquid crystal molecules of the liquid crystal layer in the state in which the electric field is applied to change the polarization of the light passing through the liquid crystal layer. The polarizer displays a desired image by appropriately blocking or transmitting polarized light to create bright and dark areas.

Such a liquid crystal display includes a pixel including a switching element, a display panel having a display signal line, and a gate driver having a plurality of stages that turn on / off a switching element of a pixel by sending a gate signal to a gate line among the display signal lines. do.

A gate on / off voltage, a clock signal, and the like are input to the stage of the gate driver, and these signals are supplied to a signal line connected to one side of each stage.

The gate driver may be directly integrated on the substrate. In this case, the gate line may be extended to be directly connected to the substrate. At this time, in order to connect the gate wiring of the gate driver and the data wiring to each other, a contact hole that exposes the gate wiring is formed, and the gate wiring and the data wiring are connected through the contact hole using a connecting member made of ITO or the like.

On the other hand, when the gate driver is formed outside the substrate, in order to supply the gate on / off voltage to the stage of the gate driver, a pad unit connecting the on / off signal line and each stage of the gate driver is required. At this time, in order to connect the pad portion and the signal line, a contact hole exposing the signal line is formed, and each stage of the signal line and the gate driver is connected through the contact hole using a connection member made of ITO or the like.

On the other hand, as the area of the display device becomes larger, the signal lines also become longer and accordingly the resistance becomes larger. As the resistance increases, problems such as signal delay or voltage drop may occur. To solve this problem, it is necessary to form a signal line with a material having a low specific resistance.

One of the materials with low resistivity is an alloy containing aluminum (Al), and generally forms a signal line in the form of a multilayer with other metals.

However, when the signal line including aluminum contacts the pixel electrode of the display device or the ITO used as the connecting member, the aluminum may be oxidized and corroded.

Accordingly, an object of the present invention is to solve this problem, and to provide a liquid crystal display device and a method of manufacturing the same, which can prevent oxidation and corrosion caused by contact between a signal line or gate pad part including aluminum and ITO. It is.

A thin film transistor array panel according to an exemplary embodiment of the present invention includes a gate insulating film having a substrate, a first signal line formed on the substrate, and a first contact hole formed on the first signal line and exposing a portion of the first signal line. A first semiconductor formed on the gate insulating film, a second signal line formed on the first semiconductor, a drain electrode formed on the first semiconductor and spaced apart from the second signal line, and formed on the gate insulating film, A protective layer having a conductor connected to the first signal line through the first contact hole, the second signal line, the drain electrode, and a second contact hole formed on the conductor and exposing the drain electrode; And a drain electrode formed through the second contact hole. It may include a pixel electrode that is determined.

The thin film transistor array panel further includes a third contact hole in which the passivation layer exposes a portion of the conductor, and the thin film transistor array panel is formed on the passivation layer and is connected to the conductor through the third contact hole. The semiconductor device may further include a member, and the first signal line may include a gate electrode positioned below the first semiconductor.

The thin film transistor array panel further includes a third signal line formed under the gate insulating layer, the third signal line including a gate electrode disposed under the first semiconductor, and a gate driving circuit connected to the conductor and the third signal line. can do.

The thin film transistor array panel further includes a second semiconductor formed between the exposed portion of the first signal line and the conductor, the second semiconductor having a fourth contact hole aligned with the first contact hole, The conductor may be connected to the first signal line through the first and fourth contact holes.

The planar shape of the second semiconductor may be substantially the same as the planar shape of the conductor except for the fourth contact hole.

The first semiconductor may extend along the second signal line and the drain electrode, and the planar shape of the second signal line and the drain electrode may be substantially the same as the planar shape of the first semiconductor portion underlying it.

The thin film transistor array panel may further include a storage electrode formed of the same layer as the first signal line and overlapping the pixel electrode, and a third semiconductor formed on the storage electrode on the gate insulating layer.

The first signal line may include a first conductive layer made of aluminum or an aluminum alloy.

The first signal line may further include a second conductive layer disposed under the first conductive layer and made of chromium, molybdenum, chromium alloy, or molybdenum alloy.

An exposed portion of the first signal line exposed through the first contact hole may not include the first conductive layer.

The first contact hole may expose a boundary of the first signal line.

A method of manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention may include forming a first signal line on a substrate, laminating a gate insulating film on the first signal line, laminating an intrinsic amorphous silicon layer on the gate insulating film, Stacking an impurity amorphous silicon layer on the amorphous silicon layer, forming a photoresist film having a different thickness depending on a position on the impurity amorphous silicon layer and exposing a first portion of the impurity amorphous silicon layer, using the photoresist as a mask Patterning the impurity amorphous silicon layer, the intrinsic amorphous silicon layer, and the gate insulating film to form an impurity semiconductor and an intrinsic semiconductor, and simultaneously forming a first contact hole in the gate insulating film to expose a portion of the first signal line; A second signal line and a drain electrode are formed on the impurity semiconductor. And forming a conductor connected to the first signal line through the first contact hole, and having a second contact hole exposing a portion of the drain electrode on the data line, the drain electrode, and the conductor. Forming a passivation layer; and forming a pixel electrode connected to the drain electrode through the second contact hole on the passivation layer.

The forming of the impurity semiconductor, the intrinsic semiconductor, and the first contact hole may include etching and removing the first portion of the impurity amorphous silicon layer, the portion of the intrinsic amorphous silicon layer and the gate insulating layer below the photoresist as an etch mask. Reducing the thickness of the photoresist film to expose a second portion of the impurity amorphous silicon layer, removing the second portion of the impurity amorphous silicon layer and the portion of the intrinsic amorphous silicon layer below it, and the photoresist film It may include the step of removing.

The forming of the photoresist film includes applying the photoresist film and exposing the photoresist film through a mask having a light transmission region, a semi-transmission region, and a light shielding region, wherein the light transmission region is a first layer of the impurity amorphous silicon layer. And a semi-transmissive region may correspond to a second portion of the impurity amorphous silicon layer.

The first contact hole may be located under the first portion of the impurity amorphous silicon layer.

The first signal line may include a first conductive layer made of aluminum or an aluminum alloy.

The first signal line is made of chromium, molybdenum, chromium alloy, or molybdenum alloy, and includes a second conductive layer disposed below the first conductive layer, and after forming the first contact hole, through the first contact hole The method may further include removing the exposed first conductive layer portion of the first signal line portion.

The passivation layer may further have a third contact hole exposing a portion of the conductor, and the forming of the pixel electrode may include forming a contact auxiliary member connected to the conductor through the third contact hole.

According to another exemplary embodiment of the present disclosure, a method of manufacturing a thin film transistor array panel includes forming a first signal line on a substrate, stacking a gate insulating film on the first signal line, and stacking an intrinsic amorphous silicon layer on the gate insulating film. Stacking an impurity amorphous silicon layer on the amorphous silicon layer, etching the impurity amorphous silicon layer, the intrinsic amorphous silicon layer, and the gate insulating layer to form a first contact hole exposing a portion of the first signal line; Stacking a conductive layer on the impurity silicon layer, stacking a photosensitive film having a different thickness depending on a position on the conductive layer, and using the photosensitive film as a mask to form the conductive layer, the impurity amorphous silicon layer and the intrinsic amorphous silicon layer. A patterning pattern connected to the first signal line through the first contact hole Forming a sieve, a second signal line and a drain electrode, and a contact auxiliary member and a semiconductor thereunder; a protective film having a second contact hole exposing a portion of the drain electrode on the data line, the drain electrode, and the conductor; And forming a pixel electrode connected to the drain electrode through the second contact hole on the passivation layer.

The passivation layer may further have a third contact hole exposing a portion of the conductor, and the forming of the pixel electrode may include forming a contact auxiliary member connected to the conductor through the third contact hole.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right over" but also when there is another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Next, a thin film transistor array panel according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view of the thin film transistor array panel of FIG. 1 taken along a line II-II'-II ''-II '' '.

A plurality of gate lines 121 and a plurality of storage electrode lines 131 are formed on an insulating substrate 110 made of transparent glass or plastic.

The gate line 121 transmits a gate signal and mainly extends in a horizontal direction. Each gate line 121 includes a plurality of gate electrodes 124 protruding downward and a wide gate pad 129 for connection with another layer or an external driving circuit. A gate driving circuit (not shown) for generating a gate signal may be mounted on a flexible printed circuit film (not shown) attached to the substrate 110 or directly mounted on the substrate 110, It may be integrated into the substrate 110. When the gate driving circuit is integrated on the substrate 110, the gate line 121 may extend to be directly connected to the gate driving circuit.

The storage electrode line 131 receives a predetermined voltage, and includes a stem line extending substantially in parallel with the gate line 121 and a plurality of pairs of first and second storage electrodes 133a and 133b separated therefrom. Each of the storage electrode lines 131 is positioned between two adjacent gate lines 121, and the stem line is closer to the lower side of the two gate lines 121. Each of the sustain electrodes 133a and 133b has a fixed end connected to the stem line and a free end opposite thereto. The fixed end of the first sustain electrode 133a has a large area, and its free end is divided into two parts, a straight portion and a bent portion. However, the shape and arrangement of the storage electrode line 131 may be modified in various ways.

The gate line 121 and the storage electrode line 131 include two conductive layers having different physical properties, a lower layer, and an upper layer thereon. The top layer is made of aluminum-based metals such as aluminum (Al) or aluminum-neodymium alloy (AlNd) such as low resistivity to reduce signal delay and voltage drop. In contrast, the lower layer is made of a material having excellent physical, chemical and electrical contact properties with other materials, particularly indium tin oxide (ITO) or indium zinc oxide (IZO), such as molybdenum-based metals, chromium, tantalum, and titanium.

However, the gate line 121 and the storage electrode line 131 may have a single film structure made of aluminum or an aluminum alloy.

In FIG. 2, for the gate electrode 124, the storage electrode line 131, and the storage electrodes 133a and 133b, the lower layer of the letter P and the upper layer of the letter Q are denoted by reference numerals.

Side surfaces of the gate line 121 and the storage electrode line 131 are inclined with respect to the surface of the substrate 110, and the inclination angle is preferably about 30 ° to about 80 °.

A gate insulating layer 140 made of silicon nitride (SiNx) or silicon oxide (SiOx) is formed on the gate line 121 and the storage electrode line 131. The gate insulating layer 140 has a plurality of contact holes 141 exposing a portion of the gate pad 129.

On the gate insulating layer 140, a plurality of linear semiconductors 151 made of hydrogenated amorphous silicon (amorphous silicon is abbreviated as a-Si), polycrystalline silicon, or the like are formed. The linear semiconductor 151 mainly extends in the longitudinal direction and includes a plurality of projections 154 extending toward the gate electrode 124. The linear semiconductor 151 has a wider width in the vicinity of the gate line 121 and the storage electrode line 131 and covers them widely.

A plurality of linear and island ohmic contacts 161 and 165 are formed on the semiconductor 151. The ohmic contacts 161 and 165 may be made of a material such as n + hydrogenated amorphous silicon in which n-type impurities such as phosphorus are heavily doped, or may be made of silicide. The linear ohmic contact 161 has a plurality of protrusions 163, and the protrusion 163 and the island-type ohmic contact 165 are paired and disposed on the protrusion 154 of the semiconductor 151.

Side surfaces of the semiconductor 151 and the ohmic contacts 161 and 165 are also inclined with respect to the surface of the substrate 110, and the inclination angle is about 30 ° to 80 °.

A plurality of data lines 171, a plurality of drain electrodes 175, and a plurality of contact intermediate members 178 are disposed on the ohmic contacts 161 and 165 and the gate insulating layer 140. Is formed.

The data line 171 transmits a data signal and mainly extends in the vertical direction to cross the gate line 121. Each data line 171 also crosses the storage electrode line 131 and runs between adjacent sets of storage electrodes 133a and 133b. Each data line 171 includes a plurality of source electrodes 173 extending toward the gate electrode 124 and bent in a J-shape and a wide data pad 179 for connecting to another layer or an external driving circuit. do. A data driving circuit (not shown) for generating a data signal is mounted on a flexible printed circuit film (not shown) attached to the substrate 110, directly mounted on the substrate 110, or integrated in the substrate 110. Can be. When the data driving circuit is integrated on the substrate 110, the data line 171 may be extended to be directly connected to the data driving circuit.

The drain electrode 175 is separated from the data line 171 and faces the source electrode 173 with the gate electrode 124 as the center. Each drain electrode 175 includes one wide end and the other end having a rod shape. The wide end portion overlaps the storage electrode line 131, and the rod-shaped end portion is partially surrounded by the source electrode 173.

One gate electrode 124, one source electrode 173, and one drain electrode 175 together with the protrusion 154 of the semiconductor 151 form one thin film transistor (TFT). A channel of the transistor is formed in the protrusion 154 between the source electrode 173 and the drain electrode 175.

The contact medium member 178 covers the gate pad 129 exposed through the contact hole 141 of the gate insulating layer 140 and contacts the gate pad 129.

The data line 171, the drain electrode 175, and the contact medium member 178 may be made of a refractory metal such as chromium (Cr), molybdenum, tantalum, and titanium, or an alloy thereof. It may have a multilayer structure including a film (not shown) and a low resistance conductive film (not shown). However, the data line 171 and the drain electrode 175 may be made of various metals or conductors.

 The data line 171, the drain electrode 175, and the contact medium member 178 may also be inclined at an inclination angle of about 30 ° to about 80 ° with respect to the surface of the substrate 110.

The ohmic contacts 161 and 165 exist only between the semiconductor 151 below and the data line 171 and the drain electrode 175 thereon, and lower the contact resistance therebetween. Although the linear semiconductor 151 is narrower than the data line 171 in most places, as described above, the width of the linear semiconductor 151 is widened at the portion where it meets the gate line 121 to smooth the profile of the surface, thereby disconnecting the data line 171. prevent. The semiconductor 151 has an exposed portion between the source electrode 173 and the drain electrode 175, and not covered by the data line 171 and the drain electrode 175.

A passivation layer 180 is formed on the data line 171, the drain electrode 175, the contact medium member 178, and the exposed semiconductor 151. The passivation layer 180 may be made of an inorganic insulator or an organic insulator, and may have a flat surface. Examples of the inorganic insulator include silicon nitride and silicon oxide. The organic insulator may have photosensitivity and the dielectric constant is preferably about 4.0 or less. However, the passivation layer 180 may have a double layer structure of the lower inorganic layer and the upper organic layer so as not to damage the exposed portion of the semiconductor 151 while maintaining excellent insulating properties of the organic layer, and the organic insulating layer forming the upper layer may have a flat surface. In this case, the surface of the passivation layer 180 may be flat.

The passivation layer 180 is formed with a plurality of contact holes 182 and 185 exposing the pad 179 and the drain electrode 175 of the data line 171, respectively, and exposing the contact medium member 178. A plurality of contact holes 181 are formed, and a plurality of contact holes 181 are formed in the passivation layer 180 and the gate insulating layer 140 to expose a portion of the lower layer 133ap of the storage electrode line 131 near the fixed end of the first storage electrode 133a. A plurality of contact holes 183b exposing the contact hole 183a and the lower film 133bp of the free end protrusion of the first sustain electrode 133a are formed.

A plurality of pixel electrodes 191, a plurality of overpasses 83, and a plurality of contact assistants 81 and 82 are formed on the passivation layer 180. They may be made of a transparent conductive material such as ITO or IZO or a reflective metal such as aluminum, silver, chromium or an alloy thereof.

The pixel electrode 191 is physically and electrically connected to the drain electrode 175 through the contact hole 185 and receives a data voltage from the drain electrode 175. The pixel electrode 191 to which the data voltage is applied has a liquid crystal between the two electrodes by generating an electric field together with a common electrode (not shown) of another display panel (not shown) to which a common voltage is applied. The direction of liquid crystal molecules (not shown) of the layer (not shown) is determined. The polarization of light passing through the liquid crystal layer varies according to the direction of the liquid crystal molecules determined as described above. The pixel electrode 191 and the common electrode form a capacitor (hereinafter, referred to as a "liquid crystal capacitor") to maintain an applied voltage even after the thin film transistor is turned off.

The pixel electrode 191 and the drain electrode 175 connected to the pixel electrode 191 overlap with the storage electrode line 131 including the storage electrodes 133a and 133b. A capacitor formed by the pixel electrode 191 and the drain electrode 175 electrically connected to the pixel electrode 191 overlapping the storage electrode line 131 is called a storage capacitor, and the storage capacitor enhances the voltage holding capability of the liquid crystal capacitor.

The connecting leg 83 crosses the gate line 121 and exposes the exposed portion of the storage electrode line 131 and the storage electrode through contact holes 183a and 183b positioned on opposite sides with the gate line 121 interposed therebetween. 133b) is connected to the exposed end of the free end. The storage electrode lines 131 including the storage electrodes 133a and 133b may be used together with the connecting legs 83 to repair defects in the gate line 121, the data line 171, or the thin film transistor.

The contact auxiliary members 81 and 82 contact and cover the contact medium member 178 and the data pad 179 through the contact holes 181 and 182, respectively. The contact assisting members 81 and 82 complement and protect the adhesion between the contact mediating member 178 and the data pad 179 with the external device.

The contact medium member 178 is sandwiched between the gate pad 129 made of aluminum-based metal and the contact auxiliary member 181 made of a material such as ITO or IZO, such as a poor contact between the aluminum-based metal and ITO, for example. It prevents corrosion of aluminum by ITO.

Next, a thin film transistor array panel according to another exemplary embodiment of the present invention will be described with reference to FIGS. 3 and 4. 3 is a layout view of a thin film transistor array panel according to another exemplary embodiment of the present invention, and FIG. 4 is a cross-sectional view of the thin film transistor array panel of FIG. 3 taken along line IV-IV'-IV ''-IV '' '. .

The layer structure of the thin film transistor array panel according to the present embodiment is substantially the same as that shown in FIGS. 1 and 2.

A plurality of gate lines 121 and a plurality of storage electrode lines 131 are formed on the substrate 110. The gate line 121 includes a gate electrode 124 and a gate pad 129, and the sustain electrode line 131 includes sustain electrodes 133a and 133b. The gate line 121 and the storage electrode line 131 have a double layer structure including a lower layer having good contact characteristics and an upper layer of an aluminum-based metal. The gate layer 121 and the storage electrode line 131 are denoted by adding a reference numeral p to the lower layer and a reference q to the upper layer. . On the gate line 121 and the storage electrode line 131, the gate insulating layer 140 having the contact hole 141, the plurality of linear semiconductors 151 including the protrusions 154, and the plurality of linears including the protrusions 163. The ohmic contact 161 and the plurality of islands of ohmic contact 165 are sequentially formed.

A plurality of data lines 171 including a source electrode 173 and a data pad 179, a plurality of drain electrodes 175, and a plurality of contact mediating members 178 are formed on the ohmic contacts 161 and 165. The passivation layer 180 is formed thereon. A plurality of contact holes 181, 182, 183a, 183b, and 185 are formed in the gate insulating layer 140 and the passivation layer 180. A plurality of pixel electrodes 191, a plurality of contact auxiliary members 81 and 82, and a plurality of connection legs 83 are formed on the passivation layer 180.

However, unlike the thin film transistor array panel shown in FIGS. 1 and 2, the upper layer 129q of the portion exposed through the contact hole 141 in the gate pad 129 is removed, leaving only the lower layer 129q. In addition, since the contact hole 141 is larger than the gate pad 129, the substrate 110 around the gate pad 129 is exposed, and the exposed portion is covered with the contact medium member 178.

As such, when the upper layer 129q of the gate pad 129 is removed, corrosion of aluminum or an aluminum alloy due to contact with ITO or IZO can be effectively prevented.

Various features of the thin film transistor array panel illustrated in FIGS. 1 and 2 may also be applied to the thin film transistor array panel illustrated in FIGS. 3 and 4.

Next, a method of manufacturing the thin film transistor array panel illustrated in FIGS. 1 and 2 according to an embodiment of the present invention will be described in detail with reference to FIGS. 5 to 13.

5, 7, 10, and 12 are layout views of a thin film transistor array panel at an intermediate stage of a method of manufacturing the thin film transistor array panel illustrated in FIGS. 1 and 2 according to an embodiment of the present invention. 5 is a cross-sectional view of the thin film transistor array panel of FIG. 5 taken along the line VI-VI'-VI ''-VI '' ', and FIG. 8 is a VIII-VIII'-VIII' '-VIII' of the thin film transistor array panel of FIG. 11 is a cross-sectional view taken along the line XI-XI'-XI ''-XI '' ', and FIG. 13 is a thin film of FIG. FIG. 9 is a cross-sectional view of the transistor panel cut along the line XIII-XIII'-XIII &quot; -XIII '' ', and FIGS. 9A to 9F illustrate step-by-step processes of forming the thin film transistor array panel shown in FIGS. 7 and 8. It is a cross section.

5 and 6, a lower conductive film made of chromium, chromium-nitrogen alloy, molybdenum, or the like is laminated on the insulating substrate 110 by sputtering, and an upper conductive film made of aluminum alloy or the like is stacked thereon. The upper conductive layer and the lower conductive layer are etched to form a plurality of gate lines 121 and a plurality of storage electrode lines 131 having a double layer structure. Each gate line 121 includes a plurality of gate electrodes 124 and gate pads 129, and each storage electrode line 131 includes a plurality of storage electrodes 133a and 133b. In the figure, the lower layer is denoted by the reference numeral p and the upper layer is denoted by the reference numeral q.

Next, referring to FIGS. 7 and 8, the gate insulating layer 140 having the contact hole 141, the plurality of linear intrinsic semiconductors 151 including the protrusions 154, and the plurality of linear impurity semiconductors 164 may be formed. Form.

Next, a process of forming the intermediate structure of the thin film transistor array panel illustrated in FIGS. 7 and 8 will be described in detail with reference to FIGS. 9A to 9F.

Referring to FIG. 9A, the gate insulating layer 140, the intrinsic amorphous silicon layer 150, and the impurity amorphous silicon layer 160 are successively stacked by chemical vapor deposition, and the photoresist film 400 is applied thereon.

The photosensitive film 400 is irradiated with light through the exposure mask 60 and then developed. An example of the exposure mask 60 used in the photolithography process is shown above FIG. 9A.

The exposure mask 60 includes a substrate 61 and an opaque member 62 formed thereon. The exposure mask 60 and the substrate 110 may be divided into a light transmissive area A, a transflective area B, and a light shielding area C according to the degree of distribution of the opaque member 62 on the exposure mask 60. .

In the translucent region B, an opaque member 62 having a predetermined value, for example, a width less than or equal to the resolution of the exposure machine, is disposed at intervals less than or equal to the predetermined value, which is called a slit pattern. The light-transmitting region A is a region without the opaque member 62 at all and has a width greater than or equal to a predetermined value, and the light-shielding region C is a region covered with the opaque member 62 as a whole and also has a width greater than or equal to the predetermined value.

Instead of providing a slit pattern in the translucent region B, a lattice pattern or a thin film having a medium transmittance or a medium thickness may be provided.

As shown in FIG. 9B, when the photosensitive film 400 is irradiated with light through the exposure mask 60 and developed, the thickness of the developed photosensitive film 400 varies depending on the position. All of the portions 400 are removed, and the thickness of the portion of the photosensitive film 400 positioned in the translucent region B decreases, and the thickness of the portion of the photosensitive film 400 hardly decreases even after development in the light shielding region C.

At this time, the ratio of the thickness of the photosensitive film 400 in the semi-transmissive region (B) and the light-shielding region (C) may vary depending on the process conditions in the subsequent process, the thickness in the semi-transmissive region (B) It is preferable to set it as 1/2 or less of the thickness in (C).

As another example of the method of varying the thickness of the photoresist film, a photoresist film capable of reflow is used. That is, a thin portion is formed by forming a reflowable photosensitive film with a conventional mask having only a light transmitting area and a light blocking area, and then reflowing to allow the photosensitive film to flow down to a region in which no light remains.

Next, as shown in FIG. 9C, the impurity amorphous silicon layer 160, the intrinsic amorphous silicon layer 150, and the gate insulating layer 140 are etched using the remaining photoresist layer 400 as an etching mask. Contact holes exposing the gate pad 129 in the gate insulating layer 140 by removing portions of the impurity amorphous silicon layer 160, the intrinsic amorphous silicon layer 150, and the gate insulating layer 140 present in the region A. 141 is formed.

Next, referring to FIG. 9D, the photoresist layer 400 is ashed to remove portions of the photoresist layer 400 remaining in the translucent region B and are disposed in the light shielding region C. Reduce the height of the part.

Thereafter, as shown in FIG. 9E, the impurity amorphous silicon layer 160 and the intrinsic amorphous silicon layer 150 are etched using the photoresist film 400 remaining in the light shielding region C as an etching mask. The linear impurity semiconductor 164 and the linear intrinsic semiconductor 151 are formed.

Finally, as shown in FIG. 9F, portions of the photoresist layer 400 remaining in the light blocking region C are removed by ashing.

As such, the gate insulating layer 140, the intrinsic amorphous silicon layer 150, and the impurity amorphous silicon layer 160 are patterned using one exposure mask to form the linear impurity semiconductor 164 and the linear intrinsic semiconductor 151. At the same time, the contact hole 141 of the gate insulating layer 140 exposing the gate pad 129 can be formed, so that an additional exposure mask is not required, thereby increasing the process cost.

Next, referring to FIGS. 10 and 11, a plurality of data lines 171 and a plurality of drain electrodes 175 including a source electrode 173 and a data pad 179 are formed by stacking a metal layer by sputtering and photolithography. And a plurality of contact mediating members 178.

Subsequently, an exposed portion of the linear impurity semiconductor 164 that is not covered by the data line 171 and the drain electrode 175 is removed, and thus the plurality of linear ohmic contacts 161 including the protrusions 163 and the plurality of linear ohmic contacts 161 are removed. The island-like ohmic contact 165 is completed while exposing the portion of the intrinsic semiconductor 154 thereunder.

12 and 13, the passivation layer 180 is laminated and patterned together with the gate insulating layer 140 by photo (etching), such as the contact medium member 178, the data pad 179, and the first holding. A plurality of contact holes 181, 182, 183a, 183b exposing a part of the storage electrode line 131 near the fixed end of the electrode 133a, a part of the free end protrusion of the first storage electrode 133a, and the drain electrode 175, respectively; 185).

Lastly, as shown in FIGS. 1 and 2, the ITO or IZO, etc. are stacked on the passivation layer 180 by sputtering, and photo-etched to remove the plurality of pixel electrodes 191 and the plurality of contact assistants 81 and 82. And a plurality of connecting legs 83.

Next, a method of manufacturing the thin film transistor array panel illustrated in FIGS. 3 and 4 according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 14 to 18.

14 and 17 are layout views of a thin film transistor array panel at an intermediate stage of a method of manufacturing the thin film transistor array panel shown in FIGS. 3 and 4 according to an embodiment of the present invention, and FIG. 18 is a cross-sectional view of the display panel taken along the lines XV-XV'-XV ''-XV '' ', and FIG. 18 is a cross-sectional view of the thin film transistor display panel of FIG. 17 taken along the line XVIII-XVIII'-XVIII' '-XVIII' ''. 16A to 16F are cross-sectional views illustrating a process of forming the thin film transistor array panel illustrated in FIGS. 14 and 15.

First, as shown in FIGS. 14 and 15, the lower conductive film and the upper conductive film are sequentially stacked and photo-etched to form a plurality of gate lines 121 and a plurality of storage electrode lines 131 having a double layer structure. do. The gate line 121 includes a gate electrode 124 and a gate pad 129, and the storage electrode line 131 includes storage electrodes 133a and 133b, and the lower and upper layers are denoted by reference numerals, respectively. p and q added.

Subsequently, the gate insulating layer 140 having the contact hole 141, the plurality of linear intrinsic semiconductors 151 including the protrusions 154, and the plurality of linear impurity semiconductors 164 are formed. Then, the upper layer 129q of the portion of the gate pad 129 exposed through the contact hole 141 is removed.

Next, a process of forming the intermediate structure of the thin film transistor array panel illustrated in FIGS. 14 and 15 will be described in detail with reference to FIGS. 16A to 16F.

Referring to FIG. 16A, the gate insulating layer 140, the intrinsic amorphous silicon layer 150, and the impurity amorphous silicon layer 160 are successively stacked by chemical vapor deposition, and the photosensitive film 400 is coated thereon.

Thereafter, as shown in FIG. 16B, when the photosensitive film 400 is irradiated with light through the exposure mask 60 including the substrate 61 and the opaque member 62, the light is positioned in the light-transmitting region A. FIG. All of the photoresist layer 400 is removed, and the thickness of the portion of the photoresist layer 400 positioned in the semi-transmissive region B is reduced, and the thickness of the photoresist layer 400 does not decrease even after development in the light shielding region C. At this time, the transmissive area A of the exposure mask 60 is slightly wider than the gate pad 129 unlike the exposure mask shown in FIG. 9A.

Next, as shown in FIG. 16C, the impurity amorphous silicon layer 160, the intrinsic amorphous silicon layer 150, and the gate insulating layer 140 are etched using the remaining portion of the photoresist film 400 as an etching mask. In the region A, a contact hole 141 exposing a portion of the upper layer 129q of the gate pad 129 is formed. Subsequently, an exposed portion of the upper layer 129q of the gate pad 129 is removed to expose a portion of the lower layer 129p of the gate pad 129.

Next, as shown in FIG. 16D, the photoresist film 400 is ashed to remove portions of the photoresist film 400 remaining in the translucent region B, and the photoresist film 400 disposed in the region C is next formed. Reduce the height of the part

Thereafter, the impurity amorphous silicon layer 160 and the intrinsic amorphous silicon layer 150 are etched using the portion of the photoresist film 400 remaining in the light shielding region C remaining in the region C as an etching mask. As in 16e, linear impurity semiconductor 164 and linear intrinsic semiconductor 151 are formed.

Finally, as shown in FIG. 16F, portions of the photoresist layer 400 remaining in the light blocking region C are removed by ashing.

As such, the gate insulating layer 140, the intrinsic amorphous silicon layer 150, and the impurity amorphous silicon layer 160 are patterned using one exposure mask to form the linear impurity semiconductor 164 and the linear intrinsic semiconductor 151. While forming the gate insulating film 140 contact hole 141 exposing the gate pad 129, the top film 129q of the gate pad 129 made of aluminum or aluminum alloy, which is susceptible to corrosion, can be removed. No additional exposure mask is required, so the process cost does not increase.

Next, the metal layers are sputtered and photo-etched to form a plurality of data lines 171 including a source electrode 173 and a data pad 179, a plurality of drain electrodes 175, and a plurality of contact mediating members ( 178). Subsequently, the exposed portions of the linear impurity semiconductor 164 that are not covered by the data line 171 and the drain electrode 175 are removed to form a plurality of linear ohmic contacts 161 including the protrusions 163 and a plurality of island types. While completing the ohmic contact 165, the portion of the intrinsic semiconductor 154 beneath it is exposed.

Then, as shown in Figs. 17 and 18, after the protective film 180 is laminated, a plurality of contact holes 181, 182, 183a, 183b, and 185 are formed by patterning by photo (etching) or the like. .

3 and 4, a plurality of pixel electrodes 191, a plurality of contact auxiliary members 81 and 82, and a plurality of connecting legs 83 are formed on the passivation layer 180.

Next, a thin film transistor array panel for a liquid crystal display according to another exemplary embodiment of the present invention will be described in detail with reference to FIGS. 19 and 20.

19 is a layout view of a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 20 is a cross-sectional view of the thin film transistor array panel of FIG. 19 taken along a line XX-XX'-XX ''-XX '' '. One cross section.

The layered structure of the thin film transistor array panel according to the present embodiment is similar to the thin film transistor array panel according to the embodiments shown in FIGS. 1 and 2.

A plurality of gate lines 121 including the gate electrode 124 and the gate pad 129 and a plurality of storage electrode lines 131 including the storage electrodes 133a and 133b are formed on the substrate 110. On the gate line 121 and the storage electrode line 131, the gate insulating layer 140 having the contact hole 141, the plurality of linear semiconductors 151 including the protrusions 154, and the plurality of linears including the protrusions 163. The ohmic contact 161 and the plurality of islands of ohmic contact 165 are sequentially formed.

A plurality of data lines 171 including a source electrode 173 and a data pad 179, a plurality of drain electrodes 175, and a plurality of contact mediating members 178 are formed on the ohmic contacts 161 and 165. The passivation layer 180 is formed thereon. A plurality of contact holes 181, 182, and 185 are formed in the gate insulating layer 140 and the passivation layer 180. A plurality of pixel electrodes 191, a plurality of contact auxiliary members 81 and 82, and a plurality of connection legs 83 are formed on the passivation layer 180.

However, unlike the thin film transistor array panels shown in FIGS. 1 and 2, the thin film transistor array panels illustrated in FIGS. 19 and 20 are disposed on the sustain electrodes 133a and 133b and formed of the same layer as the data line 171. Reinforcing members 176a and 176b. Under the reinforcing members 176a and 176b, island-type resistive contact members 166a and 166b having a substantially planar shape as the reinforcing members 176a and 176b and the island-like semiconductors 156a and 156b below are formed. The reinforcing members 176a and 176b may prevent exposure of the sustain electrodes 133a and 133b to prevent corrosion.

Further, an island-type ohmic contact member 168 and an island-shaped semiconductor 158 are formed below the contact medium member 178, and their planar shapes are substantially the same.

The linear semiconductor 151 has a substantially planar shape with the data line 171, the drain electrode 175, and the ohmic contacts 161 and 165 thereunder. However, the linear semiconductor 151 has an exposed portion between the source electrode 173 and the drain electrode 175, and not covered by the data line 171 and the drain electrode 175.

The contact hole 141 penetrates through the island-like semiconductor 158 and the island-like ohmic contact 168 in substantially the same planar shape to connect the contact medium member 178 thereon with the gate pad 129.

The gate line 121 and the storage electrode line 131 have a single film structure such as aluminum-based metal.

The passivation layer 180 has a double layer structure of the lower inorganic layer 180p and the upper organic layer 180q, and the surface of the upper organic layer 180q is flat.

Various features of the thin film transistor array panel illustrated in FIGS. 1 and 2 may be applied to the thin film transistor array panel illustrated in FIGS. 19 and 20.

Next, a method of manufacturing the thin film transistor array panel illustrated in FIGS. 19 and 20 according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 21 to 27.

21, 23 and 26 are layout views of the thin film transistor array panel at an intermediate stage of the method of manufacturing the thin film transistor array panel shown in FIGS. 19 and 20 according to an embodiment of the present invention, and FIG. FIG. 24 is a cross-sectional view of the thin film transistor array panel taken along the line XXII-XXII'-XXII ''-XXII '' ', and FIG. 24 is a line XXIV-XXIV'-XXIV' '-XXIV' '' of the thin film transistor array panel of FIG. FIG. 27 is a cross-sectional view of the thin film transistor array panel of FIG. 26 taken along a line XXVII-XXVII'-XXVII``-XXVII '' ', and FIGS. 25A to 25F are FIGS. 23 and 25. 24 is a cross-sectional view illustrating the process of forming the thin film transistor array panel illustrated in FIG. 24.

First, as shown in FIGS. 21 and 22, an aluminum alloy such as aluminum (Al) or aluminum-neodymium alloy (AlNd), or the like is laminated on the insulating substrate 110 by sputtering or the like, followed by photolithography to form a gate electrode ( A plurality of gate lines 121 including the 124 and the gate pad 129 and a plurality of storage electrode lines 131 including the storage electrodes 133a and 133b are formed.

Next, referring to FIGS. 23 and 24, the gate insulating layer 140, the plurality of linear intrinsic semiconductors 151 including the protrusions 154, the plurality of island-like semiconductors 156a, 156b, and 158, and the protrusions 163. A plurality of linear resistive contact members 161 including a plurality of islands and a plurality of island-type resistive contact members 165, 166a, 166b, 168, and 169, and a plurality of sources including a source electrode 173 and a data pad 179. The data line 171, the plurality of drain electrodes 175, the plurality of contact mediating members 178, and the plurality of reinforcing members 176a and 176b are formed. Island resistive contact member 168. In the island type semiconductor 158 and the gate insulating layer 140, contact holes 141 exposing the gate pad 129 are formed.

Next, a method of forming an intermediate structure of the thin film transistor array panel illustrated in FIGS. 23 and 24 will be described in detail with reference to FIGS. 25A to 25F.

As shown in FIG. 25A, the gate insulating film 140, the intrinsic amorphous silicon layer 150, and the impurity amorphous silicon layer 160 are successively laminated by chemical vapor deposition or the like. Thereafter, as shown in FIG. 25B, the impurity amorphous silicon layer 160, the intrinsic amorphous silicon layer 150, and the gate insulating layer 140 are etched to form a plurality of contact holes 141 exposing the gate pad 129. do.

Next, as shown in FIG. 25C, after the data conductive layer 170 is laminated by a method such as sputtering, a photosensitive film 410 is formed as shown in FIG. 25D.

At this time, referring to FIG. 25D, the thickness of the photoresist film 410 varies depending on the position. The thickness of the photoresist film 410 is the thickest in the light shielding region F, and in the light shielding region F in the translucent region E It is thinner and there is no photosensitive film in the transmissive area D.

Referring to FIG. 25E, a plurality of data conductors 174 and a plurality of reinforcing members are formed by etching and removing a portion of the data metal layer 170 exposed in the light-transmitting region D by using the photoresist 410 as an etching mask. 176a and 176b and a plurality of contact medium members 178 are formed. Subsequently, portions of the impurity amorphous silicon layer 160 and the portions of the intrinsic amorphous silicon layer 150 exposed to the light-transmitting region D are etched and removed to remove the plurality of linear impurity semiconductors 164 and the plurality of island-like impurity semiconductors 166a, A plurality of linear (intrinsic) semiconductors 151 and a plurality of island (intrinsic) semiconductors 156a, 156b, and 158 including 166b and 168 and protrusions 154 are formed.

Subsequently, as shown in FIG. 25F, the photosensitive film 410 is ashed to remove the portion of the photosensitive film 400 remaining in the semi-transmissive region E, and the photosensitive film disposed in the light shielding region F ( 400) Reduce the height of the part.

Thereafter, the data conductor 174 is etched using the portion of the photoresist film 410 remaining in the light shielding region F as an etch mask, and the plurality of data lines 171 including the source electrode 173 and the plurality of data lines are etched. While forming the drain electrode 175, the linear impurity semiconductor 164 between the source electrode 173 and the drain electrode 175 is exposed.

Finally, by removing the exposed portion of the linear impurity semiconductor 164, as shown in FIG. 24, the plurality of linear impurity semiconductors 161 including the protrusions 163 and the plurality of island-type ohmic contacts 165 are formed. Complete

Referring to FIGS. 26 and 27, after forming the passivation layer 180 including the lower inorganic layer 180p and the upper organic layer 180q, the plurality of contact holes may be photo-etched together with the gate insulating layer 140. 181, 182, 183a, 183b, and 185.

Finally, as illustrated in FIGS. 19 and 20, a plurality of pixel electrodes 191, a plurality of contact auxiliary members 81 and 82, and a plurality of connection legs 83 are formed on the passivation layer 180. Leg (83)

A liquid crystal display according to another exemplary embodiment of the present invention will now be described with reference to FIG. 28.

28 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 28, the liquid crystal display according to the exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a data driver 500 connected to the assembly 300, and a gray voltage generator connected to the data driver 500. (Not shown), and a signal controller (not shown) for controlling the assembly 300 and the data driver 500.

The liquid crystal panel assembly 300 includes a thin film transistor array panel (not shown) facing each other, a common electrode panel (not shown), and a liquid crystal layer between the two display panels. The thin film transistor array panel includes a display area DA directly related to an image display and a driving area CA related to a gate driver.

The display area DA includes a plurality of gate lines G1 -Gn, a plurality of data lines D1 -Dm, a plurality of sustain electrode lines (not shown), a plurality of pixel electrodes (not shown), and a plurality of thin film transistors. Etc. are formed.

In the driving area CA, a gate driver for generating a gate signal and a plurality of signal transmission lines (not shown) for transmitting various signals from the outside to the gate driver are formed. The gate driver may be a shift register including a plurality of stages (not shown) connected in turn.

An example of the thin film transistor array panel of the liquid crystal display shown in FIG. 28 will be described in detail with reference to FIGS. 29 to 31.

FIG. 29 is an example of a layout view of a portion of a display area in the thin film transistor array panel of the liquid crystal display illustrated in FIG. 28, and FIG. 30 illustrates a portion of a driving region in the thin film transistor array panel of the liquid crystal display illustrated in FIG. 28. FIG. 31 is a cross-sectional view of the thin film transistor array panel of FIGS. 30 and 29 taken along the line XXXI-XXXI'-XXXI ''-XXXI '' '.

Since the display unit DA has a stacked structure similar to that shown in FIGS. 1 and 2, the display unit DA will be described in detail with reference to the driving area CA.

Referring to FIG. 30, a plurality of circuit parts 610 (corresponding to one stage of a shift register) generating a gate signal and a plurality of signal transmission lines transmitting various signals to the circuit part 610 are provided in the driving area CA. a transmission line is formed. The circuit unit 610 includes a plurality of thin film transistors (not shown) and a plurality of connection lines (not shown) that connect them to each other or to a signal transmission line.

Next, the specific layer structure of the thin film transistor array panel will be described in detail.

A plurality of gate lines 121 and a plurality of storage electrode lines 131 of the display area DA and a plurality of gate-layer signal transmission lines of the driving area CA on the insulating substrate 110 ( 125, 126, 127, and 128 are formed.

Each gate line 121 includes a plurality of gate electrodes 124 and extends into the driving area CA to be directly connected to the circuit unit 610 so that there is no gate pad.

The gate layer signal transmission lines 125-128 are required to drive the circuit unit 610 and transmit various signals such as a voltage coming from the outside and mainly extend in the vertical direction.

The gate line 121, the storage electrode line 131, and the gate layer signal transmission lines 125-128 have a double layer structure including a lower layer and an upper layer thereon, as shown in FIGS. 1 and 2. In FIG. 31, reference numerals p and q are added to the lower layer and the upper layer, respectively.

The gate insulating layer 140 is formed on the gate line 121, the storage electrode line 131, and the gate layer signal transmission lines 125-128. A plurality of contact holes 142a, 142b, and 142c exposing portions of the gate layer signal transmission lines 125, 127, and 128 are formed in the gate insulating layer 140.

On the gate insulating layer 140, the display area DA is formed with a plurality of linear semiconductors 151 including a projection 154, and a plurality of linear ohmic contacts including the protrusion 163 thereon. 161 and the plurality of island resistive contact members 165 are formed.

On the ohmic contacts 161 and 165 and the gate insulating layer 140, a plurality of data lines 171 of the display area DA and a plurality of data layer signal transmission lines of the drain electrodes 175 and the driving area CA. (data-layer signal transmission lines) 172a, 172b, and 172c are formed.

Each data line 171 includes a plurality of source electrodes 173 and a data pad 179.

Like the gate layer signal transmission lines 125-128, the data layer signal transmission lines 172a-172c are required to drive the circuit unit 610 and transmit various signals such as a voltage coming from the outside. Stretched. The data layer signal transmission lines 172a-172c extend toward the contact holes 142a-142c and are connected to the gate layer signal transmission lines 125, 127, and 128 through the contact holes 142a-142c. 172a1, 172b1, 172c1). Some data layer signal transmission lines 172a and 172b include a plurality of extensions 172a2 and 172b2 extending toward the circuit unit 610 and connected to the circuit unit 610.

The passivation layer 180 is formed on the data line 171, the drain electrode 175, the data layer signal transmission lines 172a-172c, and the exposed semiconductor 151. The passivation layer 180 has a plurality of contact holes 182 and 185 exposing the data pad 179 and the drain electrode 175, respectively. In the passivation layer 180 and the gate insulating layer 140, a plurality of contact holes 183a exposing a part of the lower layer 133ap of the storage electrode line 131 near the fixed end of the first storage electrode 133a, and the first storage electrode ( 133a) A plurality of contact holes 183b exposing the lower film 133bp of the free end protrusion are formed.

A plurality of pixel electrodes 191, a plurality of connection legs 84, and a plurality of contact assistants 82 are formed on the passivation layer 180.

As described above, the thin film transistor and the connection line are formed in the circuit unit 610, and the thin film transistor may have a layer structure substantially the same as that of the thin film transistor in the display area DA, and the connection line may be the gate line 121 or the like. It may be made of the same layer as the data line 171. The gate layer connection line and the data layer connection line may be connected to each other through a contact hole (not shown) formed in the gate insulating layer 140.

As such, the gate layer signal transmission lines 125, 127, and 128 and the data layer signal transmission lines 172a through 177c do not pass through separate connection members made of the same material as the pixel electrode 191. Since it is directly connected through 181c, no defects are caused by the direct contact of ITO or IZO with aluminum or an aluminum alloy.

Various features of the thin film transistor array panel illustrated in FIGS. 1 and 2 may also be applied to the thin film transistor array panels illustrated in FIGS. 29 to 31.

Next, a method of manufacturing the thin film transistor array panel illustrated in FIGS. 29 to 31 will be described in detail with reference to FIGS. 32 to 36.

32, 33, 35, and 36 are cross-sectional views at intermediate stages of a method of manufacturing the thin film transistor array panel shown in FIGS. 29 to 31 according to an embodiment of the present invention, and FIGS. 34A to 34F are FIGS. 33 is a cross-sectional view illustrating a process of forming the thin film transistor array panel of FIG. 33.

Referring to FIG. 32, a plurality of gate lines 121 including a gate electrode 124 and a gate pad 129 and a plurality of storage electrode lines 131 including sustain electrodes 133a and 133b are disposed on an insulating substrate 110. And gate layer signal transmission lines 125, 126, 127, and 128. The gate line 121, the sustain electrode line 131, and the gate layer signal transmission lines 125-128 each include a lower layer and an upper layer, and p is attached to the lower layer and q is attached to the upper layer.

Next, as shown in FIG. 33, the gate insulating layer 140 having the contact hole 141, the plurality of linear intrinsic semiconductors 151 including the protrusions 154, and the plurality of linear impurity semiconductors 164 are formed. do.

Next, a process of forming the intermediate structure of the thin film transistor array panel illustrated in FIG. 33 will be described in detail with reference to FIGS. 34A to 34F.

Referring to FIG. 34A, the gate insulating layer 140, the intrinsic amorphous silicon layer 150, and the impurity amorphous silicon layer 160 are successively stacked by chemical vapor deposition, and the photoresist film 400 is coated thereon.

As shown in FIG. 34B, when the photosensitive film 400 is irradiated with light through the exposure mask 60 and developed, the developed photosensitive film 400 includes a light transmitting area A, a semi-transmissive area B, and a light blocking area. It has a different thickness according to (C).

Next, as shown in FIG. 34C, the impurity amorphous silicon layer 160, the intrinsic amorphous silicon layer 150, and the gate insulating layer 140 are etched using the remaining photoresist layer 400 as an etching mask. Contact holes 142a to 142c exposing portions of the signal lines 125, 127 and 128 are formed.

Next, referring to FIG. 34D, the photoresist layer 400 is ashed to remove portions of the photoresist layer 400 remaining in the semi-transmissive region B and are disposed in the light shielding region C. Reduce the height of the part.

Thereafter, as shown in FIG. 34E, the impurity amorphous silicon layer 160 and the intrinsic amorphous silicon layer 150 are etched using the photoresist film 400 remaining in the light shielding region C as an etching mask. The linear impurity semiconductor 164 and the linear intrinsic semiconductor 151 are formed.

Finally, as shown in FIG. 34F, a portion of the photoresist film 400 remaining in the light blocking region C is removed by ashing or the like.

Next, referring to FIG. 35, a plurality of data lines 171 including a source electrode 173 and a data pad 179, a plurality of drain electrodes 175, and a plurality of data layers of the gate driver 600 are provided. Signal transmission lines 172a, 172b, and 172c are formed. In this case, the protrusions 172a1, 172b1, and 172c1 of the data signal lines 1772, 1774, and 1776 are connected to the gate signal lines 125, 127, and 128 exposed through the contact holes 142a-142c.

Subsequently, an exposed portion of the linear impurity semiconductor 164 that is not covered by the data line 171 and the drain electrode 175 is removed, and the plurality of linear ohmic contacts 161 including the protrusions 163 and the plurality of island types are removed. While completing the ohmic contact 165, the portion of the intrinsic semiconductor 154 beneath it is exposed.

As shown in FIG. 36, the passivation layer 180 is stacked and patterned together with the gate insulation layer 140 to be photographed (etched), so that the sustain electrode line near the fixed end of the data pad 179 and the first sustain electrode 133a. A plurality of contact holes 182, 183a, 183b, and 185 exposing a portion, a portion of the free end protrusion of the first storage electrode 133a, and a drain electrode 175 are formed.

Finally, as illustrated in FIGS. 29 and 31, a plurality of pixel electrodes 191, a plurality of contact auxiliary members 82, and a plurality of connection legs 83 are formed on the passivation layer 180. Next, another example of the thin film transistor array panel for the liquid crystal display device illustrated in FIG. 28 will be described with reference to FIGS. 37 to 39.

FIG. 37 is another example of a layout view of a portion of the display area of the thin film transistor array panel of the liquid crystal display of FIG. 28, and FIG. 38 is a diagram illustrating a driving area of the thin film transistor array panel of the liquid crystal display of FIG. 28. FIG. 39 is a cross-sectional view of the thin film transistor array panel of FIGS. 38 and 37 taken along the line XXXIX-XXXIX'-XXXIX ''-XXXIX '' '.

The layer structure of the thin film transistor array panel according to the present embodiment is similar to the embodiment shown in FIGS. 29 to 31.

In the driving region CA, a plurality of circuit units 610 for generating gate signals and a plurality of signal transmission lines for transmitting various signals to the circuit units 610 are formed.

A plurality of gate lines 121, a plurality of storage electrode lines 131, and a plurality of gate layer signal transmission lines 125, 126, 127, and 128 of the display area DA are disposed on the substrate 110. It is formed.

The gate line 121 and the storage electrode line 131 have a single layer structure, and may be made of an aluminum alloy such as aluminum (Al) or aluminum-neodymium alloy (AlNd) having low specific resistance to reduce signal delay or voltage drop. have.

A plurality of contact holes 142a, 142b, and 142c exposing portions of the gate layer signal transmission lines 125, 127, and 128 over the gate line 121, the storage electrode line 131, and the gate layer signal transmission lines 125-128. A gate insulating layer 140 is formed, and a plurality of linear semiconductors 151 including projections 154 are formed in the display area DA on the gate insulating layer 140. A plurality of linear ohmic contacts 161 and a plurality of island-type ohmic contacts 165 including protrusions 163 are formed thereon.

On the ohmic contacts 161 and 165 and the gate insulating layer 140, a plurality of data lines 171 of the display area DA and a plurality of data layer signal transmission lines of the drain electrodes 175 and the driving area CA. 172a, 172b, and 172c are formed.

Each data line 171 includes a plurality of source electrodes 173 and data pads 179, and the data layer signal transmission lines 172a-172c extend toward the contact holes 142a-142c to contact the holes 142a-. A plurality of protrusions 172a1, 172b1, and 172c1 connected to the gate layer signal transmission lines 125, 127, and 128 through 142c are included.

A passivation layer 180 is formed on the data line 171, the drain electrode 175, the data layer signal transmission lines 172a-172c, and the exposed portion of the semiconductor 151. A plurality of contact holes 182 and 185 exposing the data pad 179 and the drain electrode 175 are formed in the passivation layer 180, and the first storage electrode 133a is formed in the passivation layer 180 and the gate insulating layer 140. A plurality of contact holes 183a exposing a part of the sustain electrode line 131 near the fixed end and a plurality of contact holes 183b exposing the free end protrusion of the first sustain electrode 133a are formed.

The passivation layer 180 may have a double layer structure of the lower inorganic layer 180p and the upper organic layer 180q, and the surface of the upper organic layer 180q may be flat. However, the passivation layer 180 may be formed of a single layer.

A plurality of pixel electrodes 191, a plurality of overpasses 84, and a plurality of contact assistants 82 are formed on the passivation layer 180.

However, unlike the thin film transistor array panels shown in FIGS. 29 to 31, the thin film transistor array panels illustrated in FIGS. 37 to 39 are disposed on the sustain electrodes 133a and 133b and formed of the same layer as the data line 171. Island-type resistive contact members 166a and 166b including the reinforcing members 176a and 176b, and having a planar shape substantially the same as the reinforcing members 176a and 176b below the reinforcing members 176a and 176b, and the island semiconductors thereunder. 156a, 156b. In addition, the linear semiconductor 151 has a planar shape substantially the same as the data line 171, the drain electrode 175, and the ohmic contacts 161 and 165 thereunder. However, the linear semiconductor 151 has an exposed portion between the source electrode 173 and the drain electrode 175, and not covered by the data line 171 and the drain electrode 175.

Various features of the thin film transistor array panel illustrated in FIGS. 29 to 31 may also be applied to the thin film transistor array panels illustrated in FIGS. 3 to 39.

The manufacturing method of the thin film transistor array panel according to the present embodiment is similar to the manufacturing method of the thin film transistor array panel shown in FIGS. 21 to 27.

However, the gate layer signal transmission lines 125-128 are formed in the same step as the gate line 121, and the data layer signal transmission lines 172a-172c are formed in the same step as the data line 171. In addition, when forming the contact holes 142a-142c, the same method as that used when forming the contact holes 141 shown in FIGS. 14 and 15 is used.

As described above, a contact hole is formed in which a contact hole is formed in the semiconductor and a contact hole is formed in the gate insulating film, and the gate pad or gate layer signal transmission line of the aluminum-based metal exposed through the contact hole is made of the same material as the data line. By covering and protecting the member or directly connecting the data layer signal transmission line, the ITO or IZO and the aluminum-based metal can be prevented from directly contacting each other, thereby effectively preventing corrosion of the aluminum or aluminum alloy by the direct contact. In addition, the manufacturing cost of the thin film transistor array panel can be reduced by patterning the semiconductor, the contact auxiliary member, the data line, and the like using one mask.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (20)

Board, A first signal line formed on the substrate, A gate insulating layer formed on the first signal line and having a first contact hole exposing a portion of the first signal line; A first semiconductor formed on the gate insulating film, A second signal line formed on the first semiconductor, A drain electrode formed on the first semiconductor and spaced apart from the second signal line, A conductor formed on the gate insulating layer and connected to the first signal line through the first contact hole; A passivation layer formed on the second signal line, the drain electrode and the conductor, and having a second contact hole exposing the drain electrode; A pixel electrode formed on the passivation layer and connected to the drain electrode through the second contact hole; Thin film transistor array panel comprising a. In claim 1, The protective film further has a third contact hole exposing a portion of the conductor, The thin film transistor array panel further includes a contact auxiliary member formed on the passivation layer and connected to the conductor through the third contact hole. The first signal line includes a gate electrode positioned below the first semiconductor. Thin film transistor display panel. In claim 1, A third signal line formed under the gate insulating layer and including a gate electrode under the first semiconductor, and A gate driving circuit connected to the conductor and the third signal line Thin film transistor display panel further comprising. The method according to any one of claims 1 to 3, And a second semiconductor formed between the exposed portion of the first signal line and the conductor, The second semiconductor has a fourth contact hole aligned with the first contact hole, The conductor is connected to the first signal line through the first and fourth contact holes. Thin film transistor display panel. In claim 4, The planar shape of the second semiconductor is substantially the same as the planar shape of the conductor except for the fourth contact hole. In claim 5, And the first semiconductor extends along the second signal line and the drain electrode, and the planar shape of the second signal line and the drain electrode is substantially the same as the planar shape of the first semiconductor portion underlying it. In claim 6, A storage electrode formed of the same layer as the first signal line and overlapping the pixel electrode; and A third semiconductor formed on the sustain electrode on the gate insulating film Thin film transistor display panel further comprising. The method according to any one of claims 1 to 3, The thin film transistor array panel of claim 1, wherein the first signal line comprises a first conductive layer made of aluminum or an aluminum alloy. In claim 8, The first signal line further includes a second conductive layer disposed under the first conductive layer and formed of chromium, molybdenum, chromium alloy, or molybdenum alloy. In claim 9, The exposed portion of the first signal line exposed through the first contact hole does not include the first conductive layer. In claim 10, The first contact hole exposes a boundary of the first signal line. Forming a first signal line on the substrate, Stacking a gate insulating film on the first signal line; Stacking an intrinsic amorphous silicon layer on the gate insulating film, Stacking an impurity amorphous silicon layer on the amorphous silicon layer, Forming a photoresist film on the impurity amorphous silicon layer, the photosensitive film having a different thickness and exposing a first portion of the impurity amorphous silicon layer; A first contact hole for patterning the impurity amorphous silicon layer, the intrinsic amorphous silicon layer, and the gate insulating film using the photosensitive film as a mask to form an impurity semiconductor and an intrinsic semiconductor, and simultaneously expose a portion of the first signal line in the gate insulating film Forming a step, Forming a conductor connected to the first signal line through the first contact hole while forming a second signal line and a drain electrode on the impurity semiconductor; Forming a protective film having a second contact hole exposing a part of the drain electrode on the data line, the drain electrode and the conductor; and Forming a pixel electrode connected to the drain electrode through the second contact hole on the passivation layer; Method of manufacturing a thin film transistor array panel comprising a. In claim 12, Forming the impurity semiconductor, the intrinsic semiconductor, and the first contact hole may include: Etching by removing the first portion of the impurity amorphous silicon layer, a portion of the intrinsic amorphous silicon layer and a gate insulating layer below the impurity amorphous silicon layer using the photoresist as an etching mask; Reducing the thickness of the photosensitive film to expose a second portion of the impurity amorphous silicon layer, Removing the second portion of the impurity amorphous silicon layer and the portion of the intrinsic amorphous silicon layer below it, and Removing the photoresist Containing Method of manufacturing a thin film transistor array panel. In claim 13, The photosensitive film forming step, Applying the photosensitive film, and Exposing the photosensitive film through a mask having a light transmissive area, a transflective area and a light shielding area Including; The light transmissive region corresponds to a first portion of the impurity amorphous silicon layer, and the translucent region corresponds to a second portion of the impurity amorphous silicon layer. Method of manufacturing a thin film transistor array panel. The method of claim 14, And the first contact hole is located under the first portion of the impurity amorphous silicon layer. In claim 12, The first signal line includes a first conductive film made of aluminum or an aluminum alloy. The method of claim 16, The first signal line is made of chromium, molybdenum, chromium alloy, or molybdenum alloy, and includes a second conductive layer disposed below the first conductive layer. After forming the first contact hole, removing the first conductive film portion of the first signal line portion exposed through the first contact hole. Method of manufacturing a thin film transistor array panel. The method according to any one of claims 12 to 17, The protective film further has a third contact hole exposing a portion of the conductor, The forming of the pixel electrode may include forming a contact auxiliary member connected to the conductor through the third contact hole. Method of manufacturing a thin film transistor array panel. Forming a first signal line on the substrate, Stacking a gate insulating film on the first signal line; Stacking an intrinsic amorphous silicon layer on the gate insulating film, Stacking an impurity amorphous silicon layer on the amorphous silicon layer, Etching the impurity amorphous silicon layer, the intrinsic amorphous silicon layer, and the gate insulating film to form a first contact hole exposing a part of the first signal line; Stacking a conductive layer on the impurity silicon layer, Stacking a photosensitive film having a different thickness according to a position on the conductive layer; Using the photoresist as a mask, the conductive layer, the impurity amorphous silicon layer, and the intrinsic amorphous silicon layer are patterned, and a conductor, a second signal line, a drain electrode connected to the first signal line through the first contact hole, and a lower portion thereof. Forming a contact auxiliary member and a semiconductor of the, Forming a protective film having a second contact hole exposing a part of the drain electrode on the data line, the drain electrode and the conductor; and Forming a pixel electrode connected to the drain electrode through the second contact hole on the passivation layer; Method of manufacturing a thin film transistor array panel comprising a. The method of claim 19, The protective film further has a third contact hole exposing a portion of the conductor, The forming of the pixel electrode may include forming a contact auxiliary member connected to the conductor through the third contact hole. Method of manufacturing a thin film transistor array panel.

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