KR100609996B1 - method for manufacturing semiconductor devices - Google Patents

method for manufacturing semiconductor devices Download PDF

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KR100609996B1
KR100609996B1 KR1019990037797A KR19990037797A KR100609996B1 KR 100609996 B1 KR100609996 B1 KR 100609996B1 KR 1019990037797 A KR1019990037797 A KR 1019990037797A KR 19990037797 A KR19990037797 A KR 19990037797A KR 100609996 B1 KR100609996 B1 KR 100609996B1
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copper
interlayer insulating
capping layer
insulating film
layer
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KR20010026464A (en
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윤중림
김영욱
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삼성전자주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체소자의 제조방법을 게시한다. 이에 의하면, 층간절연막의 다마신(damascene) 구조의 홈부들에만 채워진 구리배선들을 제외한 그 외측의 층간절연막 상에 감광막의 패턴을 형성한 후 감광막의 패턴과 구리배선들 상에 캐핑층을 함께 적층하고 이를 기계화학적 연마공정을 이용하여 구리배선들 외측의 층간절연막 상에 있는 캐핑층을 완전히 제거하고 구리배선들 상에만 캐핑층을 남긴다.The present invention discloses a method for manufacturing a semiconductor device. According to this, after forming a pattern of the photosensitive film on the interlayer insulating film outside the copper wirings filled only in the grooves of the damascene structure of the interlayer insulating film, the capping layer is laminated on the pattern of the photosensitive film and the copper wirings together. This is completely removed using a mechanochemical polishing process to remove the capping layer on the interlayer insulating film outside the copper wirings and to leave the capping layer only on the copper wirings.

따라서, 본 발명은 구리배선들 상에 캐핑층을 형성하면서도 이들 사이의 층간절연막 상에 캐핑층을 전혀 존재하지 않게 하여 구리배선들 사이의 프린지(fringe) 커패시턴스를 줄이고 나아가 RC지연시간을 단축하여 로직소자의 고속화를 이룬다.Accordingly, the present invention forms a capping layer on the copper wires, but does not have a capping layer on the interlayer insulating film therebetween, thereby reducing the fringe capacitance between the copper wires and further reducing the RC delay time. Speed up the device.

Description

반도체소자의 제조방법{method for manufacturing semiconductor devices} Method for manufacturing semiconductor devices             

도 1은 종래 기술에 의한 구리 다마신공정을 적용한 반도체소자를 나타낸 단면도.1 is a cross-sectional view showing a semiconductor device to which a copper damascene process according to the prior art is applied.

도 2 내지 도 8은 본 발명에 의한 반도체소자의 제조방법을 나타낸 단면 공정도.2 to 8 are cross-sectional process diagrams showing a method for manufacturing a semiconductor device according to the present invention.

본 발명은 반도체소자의 제조방법에 관한 것으로, 더욱 상세하게는 구리배선들 상에만 캐핑층을 선택적으로 형성하여 이들 사이의 프린지 커패시턴스(fringe capacitance)를 줄여줌으로써 동작속도의 고속화를 이룩하도록 한 반도체소자의 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a semiconductor device that can form a capping layer only on copper wirings to reduce the fringe capacitance therebetween, thereby increasing the operation speed. It relates to a manufacturing method of.

일반적으로, 반도체소자의 고집적화와 더불어 고성능화가 지속적으로 진행되어 왔고 이에 추가하여 반도체소자의 고속화도 진행되어 왔다. 고성능 로직소자의 경우, 게이트 산화막의 두께감소와 게이트전극의 길이축소가 동작속도의 개선에 영 향을 주지만, 배선저항과 층간절연막의 커패시턴스에 의한 RC지연이 동작속도의 악화에 더 많은 영향을 주고 있는 실정이다.In general, high performance has been continuously progressed along with high integration of semiconductor devices, and in addition, high speed semiconductor devices have been advanced. In the case of high-performance logic devices, the reduction of the thickness of the gate oxide and the reduction of the length of the gate electrode affect the improvement of the operating speed, but the RC delay caused by the wiring resistance and the capacitance of the interlayer dielectric film has more influence on the deterioration of the operating speed. There is a situation.

이러한 RC지연을 개선하기 위하여 여러 가지 방법들이 제안되어 왔고 그 중에서 구리(Cu)와 저유전 막질을 도입하는 방법이 현재 추진중에 있다. 구리(Cu)는 비저항 2.62Ωμ㎝의 알루미늄에 비하여 약 35%의 낮은 1.69Ωμ㎝의 비저항을 갖고, 또한 재료가격이 값싸고, 일렉트로마이그레이션(electromigration) 수명도 길어서 차세대 배선재료로서 많은 업체에서 채용하고 있다.In order to improve the RC delay, various methods have been proposed. Among them, a method of introducing copper (Cu) and low dielectric film quality is currently being promoted. Copper has a specific resistance of 1.69Ωμcm, which is about 35% lower than that of aluminum with a specific resistance of 2.62Ωμcm, low cost of materials, and long electromigration life. have.

구리배선을 형성함에 있어서, 현재 구리배선의 식각이 어려움이 있기 때문에 다마신(damascene)공정이 많이 연구되고 있다.In forming copper wiring, the damascene process has been studied a lot because of difficulty in etching copper wiring.

종래의 구리 다마신공정에 의한 반도체소자는 도 1에 도시된 바와 같이, 구성된다. 즉, 도 1에 도시된 바와 같이, 반도체기판(10) 상에 제 1 도전체(11)가 형성되고, 층간절연막(13)이 제 1 도전체(11)를 포함한 반도체기판(10) 상에 형성되며 층간절연막(13)에 제 1 도전체(11)의 일부 영역을 각각 노출시키는, 일정 간격을 두고 이격된 다마신구조의 홈부들이 형성된다. 상기 홈부들 내의 층간절연막(13)의 표면 상에만 장벽층(17)이 형성되고, 상기 홈부들을 채우며 그 내부에만 구리배선(21)이 형성되고, 구리배선들(21)의 상부면으로터의 구리확산을 방지하기 위해 상기 홈부들 외측의 층간절연막(13)을 포함한 구리배선(21) 상에 캐핑층(capping layer)(23)이 함께 형성된다.The semiconductor device by the conventional copper damascene process is constructed, as shown in FIG. That is, as shown in FIG. 1, the first conductor 11 is formed on the semiconductor substrate 10, and the interlayer insulating film 13 is formed on the semiconductor substrate 10 including the first conductor 11. Groove portions of the damascene structure spaced apart from each other are formed on the interlayer insulating layer 13 to expose portions of the first conductor 11, respectively. The barrier layer 17 is formed only on the surface of the interlayer insulating film 13 in the grooves, the copper wirings 21 are formed only in the grooves, and the upper surface of the copper wirings 21 is formed. A capping layer 23 is formed together on the copper wiring 21 including the interlayer insulating layer 13 outside the grooves to prevent copper diffusion.

그러나, 종래에는 구리배선들(21)의 상측부 사이의 이격 간격 W1이 구리배선들(21)의 하측부 사이의 이격 간격 W2보다 상당히 좁다. 또한 캐핑층(23)이 주로 큰 유전율의 질화막으로 이루어지고, 구리배선들(21)은 물론 구리배선들(21) 사이의 층간절연막(13) 상에도 함께 존재한다. However, conventionally, the spacing W1 between the upper portions of the copper wirings 21 is considerably narrower than the spacing W2 between the lower portions of the copper wirings 21. In addition, the capping layer 23 is mainly composed of a nitride film having a large dielectric constant, and is present on the interlayer insulating film 13 between the copper wires 21 as well as the copper wires 21.

이로 인해, 구리배선들(21)과, 이들 사이의 층간절연막(13) 상에 위치한 캐핑층(23)이 구리배선들(21) 사이의 프린지 커패시턴스(fringe capacitance)를 증가시키는 작용을 한다. 이는 구리배선들(21) 사이의 커패시턴스를 증가시키고 나아가 RC의 값을 증가시킨다. 그 결과 RC지연시간(τ)이 길어지므로 고성능 로직소자의 고속화가 어려워질 수밖에 없다.Thus, the copper wirings 21 and the capping layer 23 positioned on the interlayer insulating film 13 therebetween act to increase the fringe capacitance between the copper wirings 21. This increases the capacitance between the copper wirings 21 and further increases the value of RC. As a result, the RC delay time τ is long, which makes it difficult to speed up the high performance logic device.

따라서, 본 발명의 목적은 근접한 구리배선들의 상부면으로부터의 구리확산을 억제하면서도 이들 구리배선들 사이의 프린지 커패시턴스를 줄여 반도체소자의 고속화를 이룩하도록 한 반도체소자의 제조방법을 제공하는데 있다.
Accordingly, it is an object of the present invention to provide a method for manufacturing a semiconductor device in which copper diffusion from the upper surfaces of adjacent copper wires is suppressed while fringe capacitance between the copper wires is reduced to achieve high speed of the semiconductor device.

이와 같은 목적을 달성하기 위한 본 발명에 의한 반도체소자의 제조방법은The semiconductor device manufacturing method according to the present invention for achieving the above object is

반도체기판 상에 제 1 도전체를 형성하는 단계;Forming a first conductor on the semiconductor substrate;

상기 제 1 도전체의 일부 영역을 노출시키는, 일정 간격을 두고 이격된 다마신구조의 홈부들을 갖는 층간절연막을 상기 반도체기판 상에 형성하는 단계;Forming an interlayer insulating film on the semiconductor substrate having groove portions having a damascene structure spaced apart from each other by exposing a portion of the first conductor;

상기 제 1 도전체로의 구리 확산을 방지하기 위해 상기 노출된 제 1 도전체 및 상기 홈부들 내의 층간절연막의 표면에 장벽층을 형성한 후 상기 홈부들 내에만 채워진 구리배선들을 형성하는 단계; Forming a barrier layer on the surfaces of the exposed first conductor and the interlayer insulating film in the grooves to prevent copper diffusion into the first conductor, and then forming copper wirings filled only in the grooves;

상기 구리배선의 외곽을 둘러싸면서 상기 구리배선을 선택적으로 노출시키고 상기 홈부들 외측의 층간절연막 상에서 소정의 단차를 갖는 마스크층을 형성하는 단계;
상기 마스크층을 포함한 구리배선들 상에 캐핑층을 적층하는 단계; 그리고
상기 구리배선 상의 상기 캐핑층만 남을 수 있도록 상기 마스크층 및 상기 마스크층 상의 상기 캐핑층을 선택적으로 제거하는 단계를 포함하는 것을 특징으로 한다.Selectively exposing the copper wiring while surrounding an outer portion of the copper wiring and forming a mask layer having a predetermined step on the interlayer insulating film outside the grooves;
Depositing a capping layer on copper wires including the mask layer; And
And selectively removing the mask layer and the capping layer on the mask layer so that only the capping layer on the copper wiring remains.

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따라서, 본 발명은 다마신 구조의 홈부들 내에만 채워진 구리배선 상에 캐핑층을 선택적으로 형성하여 근접한 구리배선들 사이의 프린지 커패시턴스를 줄이고 나아가 RC지연시간을 단축하여 로직소자의 고속화를 이룬다.Accordingly, the present invention selectively forms a capping layer on the copper wirings filled only in the grooves of the damascene structure, thereby reducing the fringe capacitance between adjacent copper wirings, and further shortening the RC delay time, thereby speeding up the logic device.

이하, 본 발명에 의한 반도체소자의 제조방법을 첨부된 도면을 참조하여 상세히 설명하기로 한다. 종래의 부분과 동일한 기능 및 동일한 구성을 갖는 부분에는 동일한 부호를 부여한다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. The same code | symbol is attached | subjected to the part which has the same function and the same structure as the conventional part.

도 2 내지 도 8은 본 발명에 의한 반도체소자의 제조방법을 나타낸 공정도이다.2 to 8 are process charts showing a method for manufacturing a semiconductor device according to the present invention.

도 2에 도시된 바와 같이, 먼저, 반도체기판(10), 예를 들어 실리콘기판 상 에 제 1 도전체(11)를 형성하고 나서 제 1 도전체(11)를 포함한 반도체기판(10)의 표면 상에 층간절연막(13)으로서 P-TEOS 재질의 절연막을 적층한다.As shown in FIG. 2, first, a first conductor 11 is formed on a semiconductor substrate 10, for example, a silicon substrate, and then the surface of the semiconductor substrate 10 including the first conductor 11. As an interlayer insulating film 13, an insulating film made of P-TEOS material is laminated.

여기서, 제 1 도전체(11)로는 알루미늄 재질의 배선이거나, 콘택홀 내에 채워진 텅스텐과 같은 금속층이 적용될 수 있다.Here, the first conductor 11 may be an aluminum wire or a metal layer such as tungsten filled in the contact hole.

한편, 반도체기판에는 설명의 편의상 설명의 간단함과 단순함을 위하여 반도체소자를 위한 트랜지스터의 확산영역과 게이트전극, 커패시터, 저항 등의 다양한 소자들을 도면에 도시하지 않았지만, 이들이 반도체기판에 형성되어 있음은 자명한 사실이다.On the other hand, for convenience of description, various elements such as a diffusion region, a gate electrode, a capacitor, and a resistor for a semiconductor device are not illustrated in the drawings for convenience of description, but they are formed on the semiconductor substrate. It is self-evident.

도 3에 도시된 바와 같이, 공지된 사진식각공정을 이용하여 층간절연막(13)의 일부 영역들에 다마신구조의 홈부들(15)을 각각 일정 거리 이격하여 형성한다.As shown in FIG. 3, grooves 15 having a damascene structure are formed in a predetermined distance from each other in a portion of the interlayer insulating layer 13 by using a known photolithography process.

이를 좀 더 상세히 언급하면, 제 1 사진식각공정을 이용하여 후속의 구리배선들(21)의 패턴을 위한, 넓은 폭과 얕은 깊이의 제 1 식각홈들(115)을 층간절연막(13)의 표면에 각각 이격하여 형성하고 나서 제 2 사진식각공정을 이용하여 제 1 식각홈들(115)의 저면 일부영역을 좁은 폭으로 제 1 도전체(11)의 표면 일부영역이 노출될 때까지 식각하여 제 2 식각홈들(215)을 형성한다. 따라서, 층간절연막(13)에 다마신구조의 홈부들(15)이 완성된다.In more detail, the first etch grooves 115 having a wide width and a shallow depth for the pattern of the subsequent copper wirings 21 are formed by using a first photolithography process on the surface of the interlayer insulating film 13. And forming a portion of the bottom surface of the first etching grooves 115 in a narrow width until the portion of the surface of the first conductor 11 is exposed by using a second photolithography process. Two etching grooves 215 are formed. Thus, the groove portions 15 of the damascene structure are completed in the interlayer insulating film 13.

여기서, 제 1 식각홈들(115) 사이의 이격 간격 W1이 제 2 식각홈들(215) 사이의 이격 간격 W2 보다 좁다.Here, the separation interval W1 between the first etching grooves 115 is smaller than the separation interval W2 between the second etching grooves 215.

물론, 좁은 폭으로 제 1 도전체(11)의 표면 일부가 노출될 때까지 식각된 깊이의 제 1 식각홈들을 층간절연막(13)의 표면에 각각 이격하여 형성하고 나서 제 1 식각홈들의 상측부에 해당하는 층간절연막의 표면에 넓은 폭과 얕은 깊이의 제 2 식각홈들을 각각 형성하여 도면에 도시된 동일한 다마신구조의 홈부들(15)을 형성하는 방법도 가능하다.Of course, first etching grooves having an etched depth are formed on the surface of the interlayer insulating layer 13 until the portions of the surface of the first conductor 11 are exposed in a narrow width, and then upper portions of the first etching grooves are formed. It is also possible to form grooves 15 having the same damascene structure as shown in the drawings by forming second etch grooves having a wide width and a shallow depth, respectively, on the surface of the interlayer insulating film corresponding thereto.

도 4에 도시된 바와 같이, 이어서, 후속의 공정에서 형성될 구리배선(21)의 구리가 제 1 도전체(11)로 확산하는 것을 방지하기 위해 홈부들(15) 내의 노출된 제 1 도전체(11)를 포함한 층간절연막(13)의 표면 상에 장벽층(17), 예를 들어 TaN층을 증착한다.As shown in FIG. 4, the exposed first conductor in the grooves 15 is then prevented from diffusing into the first conductor 11 the copper of the copper wiring 21 to be formed in a subsequent process. A barrier layer 17, for example a TaN layer, is deposited on the surface of the interlayer insulating film 13 including (11).

그리고 나서, 상기 구조의 전면 상에 홈부들(15)을 완전히 채울 정도의 두꺼운 두께로 구리층(19)을 적층한다.Then, the copper layer 19 is laminated to a thickness thick enough to completely fill the grooves 15 on the front surface of the structure.

도 5에 도시된 바와 같이, 이후, 기계화학적 연마(chemical mechanical polishing) 공정을 이용하여 홈부들(15) 외측의 층간절연막(13) 상에 위치한 구리층(19)과 그 아래의 장벽층(17)을 완전히 제거하고 홈부들(15) 내에만 구리층(19)을 남긴다. 따라서 구리배선들(21)의 패턴이 형성된다.As shown in FIG. 5, the copper layer 19 located on the interlayer insulating film 13 outside the grooves 15 and the barrier layer 17 thereunder are then subjected to a chemical mechanical polishing process. ) Is completely removed leaving the copper layer 19 only in the grooves 15. Therefore, the pattern of the copper wirings 21 is formed.

이때, 기계화학적 연마용액에 의한 구리층(19)의 식각률이 층간절연막(13)과 식각률보다 크므로 구리배선들(21)의 표면이 층간절연막(13)의 표면 보다 낮아진다. 이는 구리배선들(21)의 표면 상에 배치될 도 8의 선택적 캐핑층(27)이 구리배선층(21)의 상부면으로부터의 구리확산을 방지하기 위한 역할을 할 수 있을 정도의 두께를 갖도록 하기 위함이다.At this time, since the etching rate of the copper layer 19 by the mechanochemical polishing solution is greater than the interlayer insulating film 13 and the etching rate, the surface of the copper wirings 21 is lower than the surface of the interlayer insulating film 13. This allows the optional capping layer 27 of FIG. 8 to be disposed on the surface of the copper wirings 21 to have a thickness sufficient to serve to prevent copper diffusion from the upper surface of the copper wiring layer 21. For sake.

도 6에 도시된 바와 같이, 이어서, 사진공정을 이용하여 식각홈들 외측의 층간절연막(13)의 표면 상에 마스크층, 예를 들어 감광막(25)의 패턴을 형성한다. 여 기서, 마스크층은 이외에도 패턴 가능한 재질이거나 산화막 재질로 물질로 이루어져도 무방하다.As shown in FIG. 6, a pattern of a mask layer, for example, a photoresist layer 25, is formed on the surface of the interlayer insulating layer 13 outside the etching grooves using a photolithography process. Here, the mask layer may be made of a patternable material or an oxide film.

도 7에 도시된 바와 같이, 그런 다음, 구리배선들(21)의 상부면으로터의 구리확산을 방지하기 위해 감광막(25)의 패턴을 포함한 구리배선들(21) 상에 캐핑층(27)을 적층한다. 여기서, 캐핑층(27)으로는 유전율이 큰 질화막이 주로 사용된다.As shown in FIG. 7, the capping layer 27 is then formed on the copper wirings 21 including the pattern of the photosensitive film 25 to prevent copper diffusion from the upper surface of the copper wirings 21. Laminated. Here, a nitride film having a high dielectric constant is mainly used as the capping layer 27.

도 8에 도시된 바와 같이, 마지막으로, 기계화학적 연마공정을 이용하여 캐핑층(27)을 감광막(25)의 패턴이 노출될 때까지 연마한다. 이어서, 감광막(25)의 패턴을 유기 스트립퍼(stripper) 용액에 의해 제거한다. 그 다음에 다시 한번 기계화학적 연마공정을 이용하여 남은 캐핑층(27)을 연마하여 구리배선들(21) 상에만 캐핑층(27)을 남기고 구리배선들(21) 외측의 층간절연막(13) 상에는 캐핑층(27)을 완전히 제거한다. 이때, 남은 캐핑층(27)과 층간절연막(13)의 표면이 평탄화를 이룬다.As shown in FIG. 8, finally, the capping layer 27 is polished until the pattern of the photosensitive film 25 is exposed using a mechanical chemical polishing process. Next, the pattern of the photosensitive film 25 is removed by an organic stripper solution. Then, the remaining capping layer 27 is polished again using a mechanical chemical polishing process to leave the capping layer 27 only on the copper wirings 21 and on the interlayer insulating film 13 outside the copper wirings 21. The capping layer 27 is completely removed. At this time, the remaining capping layer 27 and the surface of the interlayer insulating film 13 are planarized.

따라서, 본 발명은 구리배선들 사이의 층간절연막 상에 캐핑층이 전혀 존재하지 않으므로 구리배선들 사이의 층간절연막 상에 캐핑층이 존재하는 종래에 비하여 구리배선들 사이의 프린지 커패시턴스가 상당히 감소한다.Therefore, in the present invention, since there is no capping layer on the interlayer insulating film between the copper wirings, the fringe capacitance between the copper wirings is considerably reduced as compared with the conventional case in which the capping layer is present on the interlayer insulating film between the copper wirings.

이상에서 살펴본 바와 같이, 본 발명에 의하면, 층간절연막의 다마신 구조의 홈부들에만 채워진 구리배선들을 제외한 그 외측의 층간절연막 상에 감광막의 패턴 을 형성한 후 감광막의 패턴과 구리배선들 상에 캐핑층을 함께 적층하고 이를 기계화학적 연마공정을 이용하여 구리배선들 외측의 층간절연막 상에 있는 캐핑층을 완전히 제거하고 구리배선들 상에만 캐핑층을 남긴다.As described above, according to the present invention, after forming a pattern of the photoresist film on the interlayer insulating film outside the copper wirings filled only in the grooves of the damascene structure of the interlayer insulating film and then on the pattern of the photoresist film and the copper wirings The ping layers are laminated together and this is removed using a mechanochemical polishing process to completely remove the capping layer on the interlayer insulating film outside the copper wirings and leave the capping layer only on the copper wirings.

따라서, 본 발명은 구리배선들 상에 캐핑층을 형성하면서도 이들 사이의 층간절연막 상에 캐핑층을 전혀 존재하지 않게 하여 구리배선들 사이의 프린지 커패시턴스를 줄이고 나아가 RC지연시간을 단축하여 로직소자의 고속화를 이룬다.Accordingly, the present invention forms a capping layer on the copper wirings, but does not have a capping layer on the interlayer insulating film therebetween, thereby reducing the fringe capacitance between the copper wirings and further reducing the RC delay time to speed up the logic device. To achieve.

한편, 본 발명은 도면에 도시된 바람직한 예를 기준으로 기술하고 있으나 이에 한정되지 않으며 발명의 사상을 벗어나지 않는 범위 내에서 본 발명이 속하는 분야에서 통상의 지식을 갖는 자에 의해 다양한 변형과 개량이 가능함은 당연하다.On the other hand, the present invention is described based on the preferred example shown in the drawings, but not limited to this and various modifications and improvements are possible by those skilled in the art to which the present invention belongs without departing from the spirit of the invention. Of course.

Claims (4)

반도체기판 상에 제 1 도전체를 형성하는 단계;Forming a first conductor on the semiconductor substrate; 상기 제 1 도전체의 일부 영역을 노출시키는, 일정 간격을 두고 이격된 다마신구조의 홈부들을 갖는 층간절연막을 상기 반도체기판 상에 형성하는 단계;Forming an interlayer insulating film on the semiconductor substrate having groove portions having a damascene structure spaced apart from each other by exposing a portion of the first conductor; 상기 제 1 도전체로의 구리 확산을 방지하기 위해 상기 노출된 제 1 도전체 및 상기 홈부들 내의 층간절연막의 표면에 장벽층을 형성한 후 상기 홈부들 내에만 채워진 구리배선들을 형성하는 단계; Forming a barrier layer on the surfaces of the exposed first conductor and the interlayer insulating film in the grooves to prevent copper diffusion into the first conductor, and then forming copper wirings filled only in the grooves; 상기 구리배선의 외곽을 둘러싸면서 상기 구리배선을 선택적으로 노출시키고 상기 홈부들 외측의 층간절연막 상에서 소정의 단차를 갖는 마스크층을 형성하는 단계;Selectively exposing the copper wiring while surrounding the outer portion of the copper wiring and forming a mask layer having a predetermined step on the interlayer insulating film outside the grooves; 상기 마스크층을 포함한 구리배선들 상에 캐핑층을 적층하는 단계; 그리고Depositing a capping layer on copper wires including the mask layer; And 상기 구리배선 상의 상기 캐핑층만 남을 수 있도록 상기 마스크층 및 상기 마스크층 상의 상기 캐핑층을 선택적으로 제거하는 단계를 포함하는 것을 특징으로 하는 반도체소자의 제조방법.And selectively removing the mask layer and the capping layer on the mask layer so that only the capping layer on the copper wiring remains. 삭제delete 제 1 항에 있어서, 상기 마스크층 및 상기 마스크층 상의 상기 캐핑층을 제거하는 단계는The method of claim 1, wherein removing the mask layer and the capping layer on the mask layer comprises: 상기 캐핑층을 기계화학적 연마공정에 의해 상기 마스크층이 노출될 때까지 연마하는 단계;Polishing the capping layer until the mask layer is exposed by a mechanical chemical polishing process; 상기 마스크층을 선택적으로 제거하는 단계;Selectively removing the mask layer; 상기 남은 캐핑층을 기계화학적 연마공정에 의해 연마하여 상기 캐핑층을 상기 홈부들 내의 구리배선들 상에만 남기고 아울러 상기 홈부들 외측의 층간절연막과 평탄화를 이루는 단계를 포함하는 것을 특징으로 하는 반도체소자의 제조방법.Polishing the remaining capping layer by a mechanical chemical polishing process to leave the capping layer only on copper wirings in the grooves, and to planarize the interlayer insulating film outside the grooves. Manufacturing method. 제 3 항에 있어서, 상기 마스크층을 감광막의 패턴으로 구성하는 것을 특징으로 하는 반도체소자의 제조방법. The method of manufacturing a semiconductor device according to claim 3, wherein said mask layer is formed in a pattern of a photosensitive film.
KR1019990037797A 1999-09-07 1999-09-07 method for manufacturing semiconductor devices KR100609996B1 (en)

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US10340204B2 (en) 2016-03-03 2019-07-02 Samsung Electronics Co., Ltd. Semiconductor devices having through electrodes and methods for fabricating the same
US10950523B2 (en) 2016-03-03 2021-03-16 Samsung Electronics Co., Ltd. Semiconductor devices having through electrodes and methods for fabricating the same
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