KR100601163B1 - Thin film transistor substrate for liquid crystal display device and manufacturing method thereof - Google Patents

Abstract

In manufacturing a thin film transistor substrate for a liquid crystal display device, a gate line is formed in a horizontal direction on an insulating substrate, a gate insulating film is formed thereon, and a data line is spaced at both sides of the data line along the data line in a vertical direction on the gate insulating film. Form an alignment pattern to retain. On top of this, a protective film is stacked, and a contact hole for exposing the drain electrode of the thin film transistor and an opening for exposing side surfaces of the alignment line with the data line are formed in the protective film, and then a pixel electrode is formed and exposed through the opening. Etch out the data lines and alignment patterns. In this way, the coupling capacitance between the data line and the pixel electrode can be made constant over the entire screen to prevent stitch defects, and the openings can be prevented from shorting the alignment pattern and the data line.

Description

Thin film transistor substrate for liquid crystal display device and manufacturing method thereof

The present invention relates to a thin film transistor substrate for a liquid crystal display device.

Next, a thin film transistor substrate for a liquid crystal display device will be described with reference to the drawings.

1 is a layout view of a conventional thin film transistor substrate for a liquid crystal display device, and FIG. 2 is a cross-sectional view taken along line II-II ′ of FIG. 1.

The gate line 2 extends in the horizontal direction on the substrate 1, and the storage capacitor electrode 21 is formed in the shape of a protrusion in the gate line 2. The gate insulating film 3 is stacked thereon, the data line 6 extends in the vertical direction on the gate insulating film 3, and the amorphous silicon pattern 4 is formed on the gate insulating film 3 above the gate line 2. have. On the amorphous silicon pattern 4, contact layers 51 and 52 made of amorphous silicon doped with n-type impurities are formed on both sides of the gate line 2 so as to be separated from each other. On the top, a source electrode 61 which is a branch of the data line 6 and a drain electrode 62 connected to the pixel electrode 8 are formed. The passivation layer 7 is stacked on the data line 6, the source electrode 61, and the drain electrode 62. On the passivation layer 7, the pixel electrode 8 is adjacent to two adjacent gate lines 2. It is formed so as to occupy most of the pixel area defined as the area where the data lines 6 intersect. The pixel electrode 8 is connected to the drain electrode 61 through the contact hole 71 formed in the protective film 7.

However, when the liquid crystal display is driven, the pixel electrode 8 may remain in a floating state until the next signal is applied after the image signal voltage transmitted through the data line 6 is once applied through the thin film transistor. However, the image signal voltages of the other rows are continuously applied to the data line 6 adjacent to the pixel electrode 8. Accordingly, the voltage of the data line 6 varies the potential of the pixel electrode 8 in the floating state, which causes an unwanted image to appear on the liquid crystal display. This phenomenon is more severe as the coupling capacitance generated in the arrangement relationship between the pixel electrode 8 and the data line 6 increases.

In addition, in the manufacturing process, the data line 6 and the pixel electrode 8 are formed by different photolithography processes. When the mask misalignment occurs in the photolithography process, the coupling capacitance changes. . In particular, when manufacturing a liquid crystal display of a large screen, since the screen is divided into several parts during the photo process, the degree of misalignment is changed between the divided planes, resulting in a stitch having different brightness between the divided planes. Such stitch defects become more severe when the liquid crystal display is driven by column inversion driving or dot inversion driving.

The technical problem to be achieved by the present invention is to prevent the stitch failure.

In order to solve the above technical problem, in the present invention, an alignment pattern is formed on both sides of the data line in parallel with the data line when the data line is formed, and the side surfaces of the data line and the alignment pattern face each other when the contact hole for exposing the drain electrode is formed. The exposed opening is further formed, and the exposed data line and the alignment pattern are etched and removed.

Specifically, the gate line is formed in the horizontal direction on the insulating substrate, the gate insulating film is stacked on the gate line, and the alignment pattern is formed in the vertical direction on the gate insulating film to maintain a constant distance from the data line and the data line. It is. An amorphous silicon pattern is formed on the gate insulating film, a drain electrode is formed on the amorphous silicon pattern, a source electrode connected to the data line is formed separately from the drain electrode on the amorphous silicon pattern, and exposes the drain electrode. Is formed on the data line, the alignment pattern, the source electrode and the drain electrode, and is connected to the drain electrode through the contact hole, and partially overlaps the alignment pattern. Among the boundary lines, a pixel electrode farther from the data line than the boundary line adjacent to the data line is formed on the passivation layer.

Alternatively, a gate line is formed in the horizontal direction on the insulating substrate, a gate insulating film is stacked on the gate line, and an alignment pattern is formed in the vertical direction on the gate insulating film to maintain a constant distance from the data line and the data line. . The amorphous silicon pattern is formed on the gate insulating film, the source electrode connected to the drain electrode and the data line is formed on the amorphous silicon pattern, and overlaps and contacts the drain electrode and part of the alignment pattern, and the boundary line adjacent to the data line is aligned. Among the boundary lines of the pattern, a pixel electrode farther from the data line than the boundary line adjacent to the data line is formed on the gate insulating film, and a structure in which the protective film is formed on the pixel electrode is also possible.

In this case, a contact layer may be further formed between the source electrode and the drain electrode and the amorphous silicon layer, or an opening may be formed in the protective film and the gate insulating film to expose the insulating substrate between the data line and the alignment pattern.

The thin film transistor substrate may include forming a gate line on the substrate, stacking a gate insulating film, an amorphous silicon layer, forming an amorphous silicon pattern, forming a data line, an alignment pattern, a source electrode, and a drain electrode, and a protective film. Stacking the semiconductor substrate; forming a contact hole exposing the drain electrode in the passivation layer; and forming an opening exposing side surfaces adjacent to each other of the data line and the alignment pattern; forming a pixel electrode; and forming the data line and the alignment pattern exposed through the opening. It is prepared through a process including the step of etching to remove.

Or forming a gate line on the substrate, laminating a gate insulating film, an amorphous silicon layer, forming an amorphous silicon pattern, forming a data line, an alignment pattern, a source electrode, a drain electrode, and one of the alignment patterns. Forming a pixel electrode to overlap the side and part of the drain electrode, laminating a protective film, forming a contact hole for exposing the drain electrode to the protective film and an opening for exposing adjacent sides of the data line and the alignment pattern, the opening It may be manufactured through a process including the step of etching by removing the data line and the alignment pattern exposed through.

An embodiment of the present invention will now be described in detail with reference to the drawings.

3 is a layout view of a thin film transistor substrate for a liquid crystal display according to a first exemplary embodiment of the present invention, and FIG. 4 is a cross-sectional view taken along line IV-IV ′ of FIG. 3.

The gate line 12 is formed in the horizontal direction on the transparent insulating substrate 11, the gate insulating layer 13 is stacked thereon, and the data line 16 is formed in the vertical direction on the gate insulating layer 13. On both sides of (16), an alignment pattern 163 separated from the data line 16 is formed in parallel with the data line 16. Since the alignment pattern 163 is formed together in the data line 16 forming step, there is no possibility of an alignment error with the data line 16. In addition, an amorphous silicon pattern 14 for forming a thin film transistor is formed on the gate insulating layer 13, and contact layers 151 and 152 separated on both sides of the amorphous silicon pattern 14 about the gate line 12. ) And a source electrode 161 and a drain electrode 162 are formed on the contact layers 151 and 152. The passivation layer 17 is stacked on the data line 16, the alignment pattern 163, the source electrode 161, and the drain electrode 162, and the pixel electrode 18 is arranged on the passivation layer 17. It is formed so as not to be adjacent to the data line 16, but overlapping. The pixel electrode 18 is connected to the drain electrode 162 through a contact hole 171 formed in the passivation layer 17.

In this way, the capacitance C ₁ between the pixel electrode 18 and the data line 16 is mostly between the capacitance C ₂ and the alignment pattern 163 between the pixel electrode 18 and the alignment pattern 163. The capacitance C ₃ between the data lines 16 is represented by the capacitance connected in series. In other words,

C ₁ = (C ₂ × C ₃ ) / (C ₂ + C ₃ ) (1)

to be. At this time, the distance between the alignment pattern 163 and the data line 16 is between 3 μm and 5 μm, while the distance between the alignment pattern 163 and the pixel electrode 18 is about 0.2 μm, and the capacitance between the pixel electrode 18 is partly nested in the pixel electrode 18 and the alignment pattern 163, the capacitance (C _2), the alignment pattern 163 and the data line 16 as compared to between the (C ₃ ) Is very small. By the way, the size of the capacitance (C ₃₎ between the pixel electrode 18 and the alignment pattern 163, the capacitance (C ₂₎ than the alignment pattern 163 and the data line 16 between the very small in formula (1) In other words, the coupling capacitance C ₁ between the pixel electrode 18 and the data line 16 is approximately equal to the capacitance C ₃ between the alignment pattern 163 and the data line 16. As a result, the coupling capacitance C ₁ between the pixel electrode 18 and the data line 16 is determined by the capacitance C ₃ between the alignment pattern 163 and the data line 16. However, since there is no room for alignment error between the data line 16 and the alignment pattern 163, the coupling capacitance between the data line 16 and the pixel electrode 18 is constant over the entire surface of the substrate 11. Stitch defects do not occur.

FIG. 5 is a layout view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention, and FIG. 6 is a cross-sectional view taken along line VI-VI ′ of FIG. 5.

The second embodiment has a structure substantially the same as that of the first embodiment. The difference is that the protective film 27 and the gate insulating film 23 between the data line 26 and the alignment pattern 263 are removed to form the opening 272 exposing the substrate 21.

The opening 272 is formed to etch the data line 26 and the alignment pattern 263. Since the gap between the data line 26 and the alignment pattern 263 is determined by the opening 272, the coupling capacitance is determined. In addition, since the contaminant particles are present between the data line 26 and the alignment pattern 263, the short circuit of the data line 26 and the alignment pattern 263 can be removed later.

7 is a layout view of a thin film transistor substrate for a liquid crystal display according to a third exemplary embodiment of the present invention, and FIG. 8 is a cross-sectional view taken along the line 'VIII' of FIG. 7.

The gate line 32, the gate insulating film 33, the amorphous silicon pattern 34, the contact layers 351 and 352, the data line 36, the alignment pattern 363, the source electrode 361 and the drain of the third embodiment The electrode 362 has the same structure as in the second embodiment. The difference is that the pixel electrode 38 is formed on the gate insulating film 33 so that the drain electrode 362 and the alignment pattern 363 partially overlap and are in direct contact. The protective film 37 is disposed on the pixel electrode 38. It is stacked. Here, the opening 372 may not be formed.

In this case, since no capacitance is generated between the alignment pattern 363 and the pixel electrode 38, the capacitance between the data line 36 and the pixel electrode 38 is reduced between the data line 36 and the alignment pattern 363. Exactly equal to the capacitance. Therefore, the stitch defect can be completely eliminated.

A method of manufacturing a thin film transistor substrate for a liquid crystal display device according to a second and a third embodiment of the present invention will now be described with reference to the drawings.

9A and 9B are cross-sectional views taken along line VI-VI 'of FIG. 5 according to a manufacturing process sequence.

Referring to FIG. 9A, a gate conductive material is deposited and patterned on a substrate to form a gate line 22, and then a gate insulating film 23, an amorphous silicon layer, and a doped amorphous silicon layer are sequentially deposited thereon, followed by amorphous silicon. The layer and the doped amorphous silicon layer are patterned to form contact layers 251 and 252 that are not separated from both sides of the amorphous silicon pattern 24. Next, a data conductive material is deposited and patterned to form a data line 26, an alignment pattern 263, a source electrode 261 and a drain electrode 262, and mask the source electrode 261 and the drain electrode 262. The contact layers 251 and 252 are etched and separated into two pieces.

Subsequently, as shown in FIG. 9B, the protective layer 27 is deposited and patterned to expose the contact hole 271 exposing the drain electrode 262, and the adjacent side surfaces of the data line 26 and the alignment pattern 263. After the openings 272 are formed, a conductive material such as indium tin oxide (ITO) is deposited and patterned to form the pixel electrode 28. Here, the patterning of the protective film 27 is performed by a dry etching method.

Finally, the data line 26 and the alignment pattern 263 exposed through the opening 272 are etched and removed using the passivation layer 27 as a mask.

When the thin film transistor substrate is manufactured in this manner, the gap between the data line 26 and the alignment pattern 263 is determined by the opening 272, so that the gap between the data line 26 and the alignment pattern 263 is constant. It is easy to make, and the data line 26 and the alignment pattern 263 can be prevented from being shorted.

10A and 10B are cross-sectional views taken along line VII-VII 'of FIG. 7 according to a manufacturing process sequence.

10A, the second embodiment shown in FIG. 9A is formed until the contact layers 251 and 252 are etched and separated on both sides using the source electrode 361 and the drain electrode 362 as masks. Same as the example. Subsequently, a conductive material such as ITO is deposited and patterned on the gate insulating film 33 to form the pixel electrode 38 so as to overlap and contact a part of the drain electrode 362 and a part of the alignment pattern 363.

Next, as shown in FIG. 10B, the protective film 37 is deposited and patterned to form an opening 372 exposing a portion of the data line 36 and the alignment pattern 363.

Finally, the data line 36 and the alignment pattern 363 exposed through the opening 372 are etched and removed.

As described above, when the alignment pattern is formed together with the data line, the coupling capacitance between the data line and the pixel electrode can be made constant over the entire screen to prevent stitch defects, and by forming the openings, the alignment pattern and the data line are short-circuited. Can be prevented.

1 is a layout view of a thin film transistor substrate for a conventional liquid crystal display device,

FIG. 2 is a cross-sectional view taken along line II-II ′ of FIG. 1;

3 is a layout view of a thin film transistor substrate for a liquid crystal display according to a first embodiment of the present invention;

4 is a cross-sectional view taken along line IV-IV 'of FIG. 3,

5 is a layout view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

FIG. 6 is a cross-sectional view taken along line VI-VI ′ of FIG. 5;

7 is a layout view of a thin film transistor substrate for a liquid crystal display according to a third exemplary embodiment of the present invention.

FIG. 8 is a cross-sectional view taken along line VII-VII 'of FIG. 7,

9A and 9B are cross-sectional views taken along line VI-VI 'of FIG. 5 according to a manufacturing process sequence.

10A and 10B are cross-sectional views taken along line VII-VII 'of FIG. 7 according to a manufacturing process sequence.

Claims (10)

A gate line formed over the insulating substrate, A gate insulating film stacked on the gate line, A data line formed on the gate insulating film and crossing the gate line; An alignment pattern formed on the gate insulating layer and spaced apart from the data line and positioned on both sides of the data line; An amorphous silicon pattern formed on the gate insulating film, A drain electrode formed on the amorphous silicon pattern, A source electrode formed on the amorphous silicon pattern and separated from the drain electrode and connected to the data line; A protective film stacked on the data line, the alignment pattern, the source electrode, and the drain electrode and having a contact hole for exposing the drain electrode; A boundary line formed on the passivation layer, connected to the drain electrode through the contact hole, and partially overlapping the alignment pattern, and a boundary line adjacent to the data line is larger than the boundary line adjacent to the data line among the boundary lines of the alignment pattern. Away from the pixel electrode Thin-film transistor substrate for liquid crystal display devices containing. In claim 1, The thin film transistor substrate of claim 1, further comprising a contact layer between the source electrode and the drain electrode, and the amorphous silicon layer. The method of claim 1 or 2, The protective film and the gate insulating film are formed in the thin film transistor substrate for the liquid crystal display device openings are formed to expose the insulating substrate between the data line and the alignment pattern. A gate line formed over the insulating substrate, A gate insulating film stacked on the gate line, A data line formed on the gate insulating layer and crossing the gate line; An alignment pattern formed on the gate insulating layer and spaced apart from the data line and positioned on both sides of the data line; An amorphous silicon pattern formed on the gate insulating film, A train electrode formed on the amorphous silicon pattern, A source electrode formed on the amorphous silicon pattern and separated from the drain electrode and connected to the data line; A pixel electrode formed on the gate insulating layer and overlapping and in contact with the drain electrode and a part of the alignment pattern, wherein a boundary line adjacent to the data line is farther from the data line than a boundary line adjacent to the data line among the boundary lines of the alignment pattern; , A protective film formed on the pixel electrode, data line, alignment pattern, source electrode, and drain electrode. Thin film transistor substrate for a liquid crystal display device comprising a. In claim 4, A thin film transistor substrate for liquid crystal display devices, wherein a contact layer is further formed between the source electrode and the drain electrode and the amorphous silicon layer. The method of claim 4 or 5, The protective film and the gate insulating film are formed in the thin film transistor substrate for the liquid crystal display device openings are formed to expose the insulating substrate between the data line and the alignment pattern. Forming a gate line on the substrate, Sequentially forming a gate insulating film and an amorphous silicon layer covering the gate line, Forming a data line, a source electrode, a drain electrode, and an alignment pattern on the substrate; Stacking a protective layer on the substrate to cover the data line, the source electrode, the drain electrode, and the alignment pattern; Forming a contact hole for exposing the drain electrode and an opening for exposing adjacent sides of the data line and the alignment pattern to the passivation layer; Forming a pixel electrode, Etching and removing the data line and the alignment pattern exposed through the opening. A thin film transistor substrate manufacturing method for liquid crystal display devices comprising. In claim 7, Laminating the amorphous silicon layer, and further comprising laminating a doped amorphous silicon layer, and in forming the amorphous silicon pattern, etching the amorphous silicon layer together to form a contact layer, wherein the source electrode is formed. And forming a drain electrode, and then separating the contact layer into two sides. Forming a gate line on the substrate, Sequentially forming a gate insulating film and an amorphous silicon layer covering the gate line, Forming a data line, an alignment pattern, a source electrode, and a drain electrode on the substrate; Forming a pixel electrode to overlap one side of the alignment pattern and a part of the drain electrode; Stacking a passivation layer covering the pixel electrode; Forming a contact hole for exposing the drain electrode and an opening for exposing adjacent sides of the data line and the alignment pattern to the passivation layer; Etching and removing the data line and the alignment pattern exposed through the opening. A thin film transistor substrate manufacturing method for liquid crystal display devices comprising. In claim 9, Laminating the amorphous silicon layer, and further comprising laminating a doped amorphous silicon layer, and in forming the amorphous silicon pattern, etching the amorphous silicon layer together to form a contact layer, wherein the source electrode is formed. And forming a drain electrode, and then separating the contact layer into two sides.