KR20070091730A - Display substrate and method for manufacturing the same - Google Patents

Abstract

A display substrate and a manufacturing method thereof are provided to reduce a gap between a storage common line and a storage electrode unit by forming a contact hole on a color filter corresponding to the storage common line, thereby charging more storage capacitances. A display substrate comprises the followings: plural gate lines; plural source lines(DL) crossing the gate lines; plural pixel units(P) defined by the gate lines and the source lines; a TFT(Thin Film Transistor) which is formed at each pixel unit, and includes a gate electrode(120) connected to the gate lines, a source electrode(154) connected to the source lines and a drain electrode(156) spaced from the source electrode; a storage common line(STL) which is formed in the pixel unit and is in parallel to the gate lines; a color filter(170) which is formed in the pixel unit, and has a first contact hole(172) corresponding to one end part of the drain electrode and a second contact hole(174) corresponding to the storage common line; and a pixel electrode(180) which is formed on the color filter, is connected to the drain electrode through the first contact hole and faces the storage common line through the second contact hole.

Description

DISPLAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME}

1 is a plan view illustrating a display substrate according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along line II ′ of FIG. 1.

3 to 12 are manufacturing process diagrams illustrating a method of manufacturing the display substrate illustrated in FIG. 2.

<Description of the symbols for the main parts of the drawings>

100: display substrate 110: base substrate

120 gate electrode 130 gate insulating film

154: source electrode 156: drain electrode

160: passivation film 170: color filter

172: first contact hole 174: second contact hole

180: pixel electrode 192: storage electrode

The present invention relates to a display substrate and a method of manufacturing the same, and more particularly, to a display substrate and a method of manufacturing the same for reducing the manufacturing cost.

In general, a liquid crystal display includes a thin film transistor (TFT) substrate, a color filter substrate coupled to face the TFT substrate, and a liquid crystal layer disposed between the two substrates.

The TFT substrate includes a signal wiring, a thin film transistor, a pixel electrode, and the like formed on an insulating substrate to independently drive a plurality of pixel portions. The color filter substrate includes a color filter layer made of color filters of red, green, and blue, and a common electrode facing the pixel electrode.

The liquid crystal display device is significantly influenced by the display quality depending on the bonding accuracy of the TFT substrate and the color filter substrate. When alignment miss occurs when the TFT substrate and the color filter substrate are combined, light leakage occurs on the display screen, thereby degrading the display quality of the liquid crystal display.

In order to prevent deterioration of the quality of the liquid crystal display due to misalignment, recently, a liquid crystal display having a color filter on array (COA) structure has been proposed. That is, in the liquid crystal display of the COA structure, each of the color filters of red, green, and blue is formed on the TFT substrate corresponding to each pixel portion. Generally, six or more exposure masks are used in the process of forming a TFT substrate of a COA structure. Since the exposure mask occupies a substantial part of the manufacturing cost, the reduction of the number of processes using the exposure mask has a great influence on the manufacturing cost reduction.

Accordingly, the technical problem of the present invention is focused on such a conventional point, and an object of the present invention is to provide a display substrate for reducing manufacturing costs.

Another object of the present invention is to provide a method for manufacturing the display substrate described above.

According to an embodiment of the present invention, a display substrate includes a plurality of gate lines, a plurality of source lines crossing the gate lines, and the gate lines and the source lines. A switching element formed in the pixel portion, the switching element including a plurality of pixel portions, a gate electrode connected to the gate wiring, a source electrode connected to the source wiring, and a drain electrode spaced apart from the source electrode; A color filter formed on the storage common line parallel to the gate line, the pixel portion, and a first contact hole corresponding to one end of the drain electrode and a second contact hole corresponding to the storage common line; And a color filter formed on the color filter and connected to the drain electrode through the first contact hole and through the second contact hole. Ridge includes opposed to the pixel electrode common wire.

According to another aspect of the present invention, there is provided a method of manufacturing a display substrate, including forming a first metal pattern including a gate wiring, a gate electrode, and a storage common wiring on the substrate; Forming a second metal pattern including a source wiring, a source electrode, and a drain electrode on the insulating film covering the pattern; and sequentially forming a passivation film and a color photoresist film on the entire surface of the insulating film on which the second metal pattern is formed. And a color filter including a first contact hole corresponding to one end of the drain electrode and a residual part corresponding to the storage common wiring by patterning the color photoresist layer to a pixel portion defined by the gate wiring and the source wiring. Forming a passivation layer and etching the passivation layer exposed through the first contact hole. Exposing one end of the electrode, removing the residual part to form a second contact hole corresponding to the storage common wiring, and electrically connecting the drain electrode, and through the second contact hole, the storage common wiring. And forming a pixel electrode facing the pixel electrode.

According to such a display substrate and a method of manufacturing the same, the color filter and the passivation film can be patterned using one exposure mask, thereby reducing the number of exposure masks used for manufacturing a display substrate having a color filter on array (COA) structure. .

Hereinafter, with reference to the accompanying drawings, it will be described in detail the present invention.

1 is a plan view illustrating a display substrate according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line II ′ of FIG. 1.

1 and 2, the display substrate 100 includes a base substrate 110, a gate wiring GL, a source wiring DL, a storage common wiring STL, a switching element TFT, and a passivation layer 160. ), A color filter 170, and a pixel electrode 180.

A plurality of gate lines GL extending in a first direction and a plurality of source lines DL extending in a second direction crossing the first direction are formed on the base substrate 110. The pixel portion P is defined in the base substrate 110 by the gate lines GL and the source lines DL.

The storage common line STL extends in the first direction between the gate lines GL.

The switching element TFT is formed in each pixel portion P, and is formed in an area where the source wiring DL and the gate wiring GL cross each other. The switching element TFT includes a gate electrode 120, a gate insulating layer 130, a source electrode 154, a drain electrode 156, and a channel portion 142. The gate electrode 120 extends from the gate line GL, and the gate line GL, the gate electrode 120, and the storage common line STL are formed in a first metal pattern on the same layout. .

The gate insulating layer 130 is formed on the base substrate 110 on which the first metal pattern is formed. The gate insulating layer 130 is formed of, for example, a silicon nitride layer (SiNx), and is formed by a chemical vapor deposition (Chemical Vapored Deposition) process.

The source electrode 154 is connected to the source wire DL and is formed to overlap a portion of the gate electrode 120 on the gate insulating layer 130. The source electrode 154 is, for example, formed in a U-shape. The drain electrode 156 is formed to be spaced apart from the source electrode 154 by a predetermined interval, and is formed to overlap a portion of the gate electrode 120 on the gate insulating layer 130. The source wiring DL, the source electrode 154 and the drain electrode 156 are formed in a second metal pattern.

A channel layer 140 patterned in the same manner as the second metal pattern is formed below the second metal pattern. The channel layer 140 preferably has a structure in which a semiconductor layer 140a made of amorphous silicon and an ohmic contact layer 140b made of n + amorphous silicon are stacked. Meanwhile, a channel portion 142 connected to the separation portion of the source electrode 154 and the drain electrode 156 from the channel layer 140 and exposing the semiconductor layer 140a of the channel layer 140 is provided. Is formed. The source electrode 154 and the drain electrode 156 are electrically connected to the channel layer 140. An electrical channel is formed in the channel layer 140 by a timing signal applied to the gate line GL. Therefore, the pixel voltage applied to the source wiring DL is output through the channel layer 140 and the drain electrode 156.

The passivation layer 160 is formed on the gate insulating layer 130 on which the switching element TFT is formed. The passivation layer 160 may be formed of, for example, a silicon nitride layer (SiNx) or a silicon oxide layer (SiOx), and may be formed using a plasma chemical vapor deposition method.

The color filter 170 is formed on the passivation layer 160 to correspond to each pixel portion P. Referring to FIG. The color filter 170 is made of, for example, a photosensitive organic composition of red, green, or blue, and is patterned to correspond to each pixel portion P through a photographic process. In addition, the color filter 170 may be formed to overlap a predetermined region with the gate line GL and the source line DL.

The passivation layer 160 and the color filter 170 may include a first contact hole 172 exposing one end of the drain electrode 156. In addition, the color filter 170 includes a second contact hole 174 formed corresponding to the storage common line STL.

Preferably, the planar area of the second contact hole 174 may be wider or narrower than the width of the storage common line STL formed in each pixel part P when viewed in plan view.

The pixel electrode 180 is formed on the color filter 170 corresponding to each pixel portion P, and is formed of a transparent conductive material through which light can pass. The transparent conductive material is made of, for example, ITO to IZO. The pixel electrode 180 contacts the drain electrode 156 through the first contact hole 172 and receives a pixel voltage from the drain electrode 156.

Meanwhile, a portion of the pixel electrode 180 that faces the storage common line STL is defined as the storage electrode unit 192. The storage capacitance is charged between the storage electrode unit 192 and the storage common line SLT to charge the pixel voltage for one frame. In particular, the second contact hole 174 may be formed in the color filter 170 to reduce the space between the storage common wiring STL and the storage electrode unit 192, thereby charging more storage capacitance.

Hereinafter, the manufacturing method of the display substrate according to the present invention will be described in detail.

3 to 12 are manufacturing process diagrams illustrating a method of manufacturing the display substrate illustrated in FIGS. 1 and 2.

1 and 3, a metal layer (not shown) is formed on the base substrate 110. The metal layer (not shown) may be formed of, for example, a metal such as chromium, aluminum, tantalum, molybdenum, titanium, tungsten, copper, silver, or an alloy thereof, and is deposited by a sputtering process. In addition, the metal layer (not shown) may be formed of two or more layers having different physical properties. Subsequently, the metal layer (not shown) is patterned by a photolithography process using a first mask MASK 1 to form a first metal pattern including a gate line GL, a gate electrode 120, and a storage common line STL. Form. The gate line GL extends in the first direction x. The gate electrode 120 is connected to the gate line GL. The storage common line STL extends in the first direction x between the gate lines GL.

Referring to FIG. 4, a gate insulating layer 130 made of silicon nitride (SiNx) using a plasma enhanced chemical vapor deposition (PECVD) method on a base substrate 110 on which the first metal pattern is formed, The active layer 140a made of amorphous silicon (a-Si: H) and the ohmic contact layer 140b doped with high concentration of n + ions are sequentially stacked.

Subsequently, a source metal layer 150 is formed on the ohmic contact layer 140b. The source metal layer 150 may be formed of, for example, a metal such as chromium, aluminum, tantalum, molybdenum, titanium, tungsten, copper, silver, or an alloy thereof, and may be deposited by a sputtering process. In addition, the source metal layer 150 may be formed of two or more layers having different physical properties. Subsequently, a photoresist film (not shown) is coated on the entire surface of the source metal layer 150. The photoresist film (not shown) includes, for example, a positive photoresist in which the exposed region is dissolved by a developer. The second mask MASK2 is aligned on the base substrate 110 on which the photoresist film (not shown) is formed. The second mask MASK2 includes a light blocking portion 10 and an opening 20, and a slit pattern Slit is formed in the light blocking portion 10. The light blocking unit 10 blocks light, the opening 20 transmits light, and a slit pattern Slit formed in the light blocking unit 10 diffracts light.

1 and 4, the light blocking portion 10 is formed to correspond to the source wiring DL, the source electrode 154, the channel portion 142, and the drain electrode 156. In this case, the slit pattern Slit is formed in a U-shape corresponding to the channel portion 142. The opening portion 20 is disposed in the remaining region except for the light blocking portion 10. Meanwhile, in the embodiment of the present invention, the channel portion 142 is formed in a U-shape, but the shape of the channel portion 142 is not limited to the U-shape.

Subsequently, the photoresist film (not shown) is exposed using the second mask MASK2. When the light passing through the opening 20 is called the first light, since the light is diffracted in the slit pattern Slit, the second light, which is about half of the first light, passes.

Therefore, when the exposed photoresist film (not shown) is developed, all of the areas exposed by the openings 20 are removed, and only the photoresist film (not shown) in the area corresponding to the light blocking part 10 remains. . In this case, a region corresponding to the slit pattern Slit is exposed by the second light, and thus remains in a relatively thin thickness. Accordingly, the first pattern portion 12 formed corresponding to the light blocking portion 10 and the second pattern portion 14 having a thickness thinner than the first pattern portion 12 corresponding to the slit pattern Slit. Is formed. Preferably, the second pattern portion 14 is formed to a thickness of about half of the first pattern portion 12.

  The first pattern part 12 is a pattern part corresponding to the source wiring DL and the source electrode 154 and the drain electrode 156 of the switching element TFT. The second pattern portion 14 is a pattern portion corresponding to the channel portion 142 of the switching element TFT.

1 and 5, the source metal layer 150 is etched using the first and second pattern portions 12 and 14. As a result, the source wiring DL and the electrode pattern 152 are formed. The source line DL extends in a second direction crossing the first direction, and a plurality of pixel portions P are defined in an area where the gate lines GL and the source line DL intersect.

 Although not shown in plan view, the electrode pattern 152 has a shape in which the source electrode 154 and the drain electrode 156 are connected on the channel portion 142. That is, the electrode pattern 152 has a shape before separating the source electrode 154 and the drain electrode 156.

Subsequently, the semiconductor layer 140a and the ohmic contact layer 140b are etched using the electrode pattern 152 and the source wiring DL as an etching mask. The etching of the semiconductor layer 140a and the ohmic contact layer 140b is performed by dry etching as an example. Accordingly, a channel layer 140 patterned in the same manner as the electrode pattern 152 and the source wiring DL is formed under the electrode pattern 152 and the source wiring DL.

Referring to FIG. 6, a first ashing process of removing a predetermined thickness of the first pattern portion 12 and the second pattern portion 14 using an oxygen plasma is performed. Accordingly, the second pattern portion 14, which has been formed to a thickness thinner than the first pattern portion 12, is removed, and the first pattern portion 12 remains at a predetermined thickness. The electrode pattern 152 is exposed in a region where the second pattern portion 14 is removed.

6 and 7, the electrode pattern 152 is etched using the remaining first pattern part 12. Accordingly, the source electrode 154 and the drain electrode 156 spaced apart from the source electrode by a predetermined interval are formed. That is, the source wiring DL, the source electrode 154, and the drain electrode 156 are second metal patterns formed by etching the source metal layer.

Subsequently, a second ashing process of removing the remaining first pattern portion 12 is performed using oxygen plasma. Next, the ohmic contact layer 140b of the channel layer 140 is dry etched using the source electrode 154 and the drain electrode 156 as an etching mask. Accordingly, a channel portion 142 exposing the semiconductor layer 140a is formed between the source electrode 154 and the drain electrode 156. Accordingly, each pixel portion P includes a switching element TFT including a gate electrode 120, a source electrode 154, a drain electrode 156, and a channel portion 142.

Meanwhile, the second ashing process may be performed after the dry etching process for forming the channel part 142.

Referring to FIG. 8, the passivation layer 160 is coated on the gate insulating layer 130 on which the switching element TFT is formed. The passivation layer 160 may be formed of, for example, a silicon nitride layer (SiNx) or a silicon oxide layer (SiOx), and may be formed using a plasma chemical vapor deposition method.

Subsequently, a color photoresist film CPR having any one color selected from red, green, and blue is coated on the passivation film 160. The color photoresist film CPR is, for example, made of a negative photoresist in which a shielded area is dissolved by a developer. The color photoresist film CPR is a material for forming a color filter and may be formed in a color such as red, green, and blue. The third mask MASK3 is aligned on the base substrate 110 to which the color photoresist film CPR is applied.

9 is a plan view illustrating a third mask.

8 and 9, a light source LIGHT SOURCE is disposed on an upper surface of the third mask MASK3, and light having a first light amount is emitted from the light source.

The third mask MASK3 includes a transparent substrate 20, a first metal pattern 32, a second metal pattern 34, and a second metal pattern 36.

The transparent substrate 20 transmits light having the first amount of light. Since the color photoresist film CPR corresponding to the transparent substrate 20 is exposed by the first light amount, the color photoresist film CPR remains at the same thickness after development.

The first metal pattern 32, the second metal pattern 34, and the second metal pattern 36 are formed on the transparent substrate 20.

The first metal pattern 32 is formed corresponding to the pixel portion adjacent to the pixel portion P to be exposed and blocks light. For example, the first metal pattern 32 may be formed to correspond to the pixel portions P to be exposed and the pixel portions adjacent to each other in the first direction x. Therefore, since the exposure of the color photoresist film applied on the pixel portions adjacent in the first direction x is prevented, it is removed by the developer. Similarly, the first metal pattern 32 may be formed to correspond to the adjacent pixel parts in the second direction x.

The second metal pattern 34 is formed corresponding to one end of the drain electrode 156, and the third metal pattern 36 is formed corresponding to the storage wiring STL formed in the pixel portion P. .

The second metal pattern 34 and the third metal pattern 36 include predetermined opening patterns. Therefore, the light emitted from the light source is shielded or diffracted in the second and second metal patterns 34 and 36.

In detail, the second metal pattern 34 is formed on the transparent substrate 20 and includes a first opening pattern S1.

In plan view, the second metal pattern 34 is formed in a rectangular shape, for example. The first opening patterns S1 may have a rectangular closed loop shape and may be formed in plural. Meanwhile, the first opening pattern S1 is formed on the outer portion of the metal pattern 22a to diffract light.

Accordingly, light is blocked at the central portion of the second metal pattern 34, and light corresponding to the second light amount corresponding to about half of the first light amount is transmitted at the outer portion.

Accordingly, when the color photoresist film CPR exposed by the second metal pattern 34 is developed, the first contact hole 172 having a two-step step corresponding to one end of the drain electrode 156 may be formed. Is formed.

That is, when viewed in a plan view, the first contact hole 172 is connected to the first opening 172a having the first area and the first opening 172a and has a second area smaller than the first area. Opening 172b. Meanwhile, the passivation layer 160 is exposed in the first contact hole 172.

The third metal pattern 36 is formed on the transparent substrate 20 and includes a plurality of second opening patterns S2. The plurality of second opening patterns S2 may be formed in a stripe shape and spaced apart from each other to be parallel to each other. In this case, the width of the second opening pattern S2 is formed to be narrower than that of the first opening pattern S1. Alternatively, the second opening pattern S2 is formed to have a width similar to that of the first opening pattern S1, and is formed at a lower density than the first opening pattern S1.

Accordingly, light corresponding to the third light amount smaller than the second light amount is transmitted through the third metal pattern 36.

Therefore, when the color photoresist film CPR exposed by the third metal pattern 36 is developed, a remaining portion RP is formed corresponding to the storage wiring STL. In this case, the thickness of the remaining portion RP may be substantially the same as the thickness of the passivation layer 160. The residual part RP prevents the passivation layer 160 corresponding to the storage common wiring STL from being etched in the dry etching process described later.

When the passivation layer 160 corresponding to the storage common wiring STL is etched, it is impossible to accurately control the capacity of the storage capacitance at the storage electrode unit described later, resulting in a poor image quality such as flicker or afterimage. Can be.

However, such a problem may be solved by forming the remaining portion RP on the passivation layer 160 corresponding to the storage common line STL.

Subsequently, a curing process is performed on the color photoresist film CPR remaining after the development.

Accordingly, referring to FIGS. 1 and 10, a color filter 170 made of color photoresist is formed on the pixel portion P. Referring to FIG. Meanwhile, the above-described process of forming the color filter 170 may be repeatedly performed according to the number of colors of the color filter to be formed on the display substrate.

Subsequently, the passivation layer 160 exposed through the first contact hole 172 is etched using the color filter 170 as an etching mask. Accordingly, the first contact hole 172 extends on the passivation layer 160. In addition, one end of the drain electrode 156 is exposed in the first contact hole 172. That is, the color filter 170 corresponding to each pixel part is patterned using the third mask, and the passivation layer 160 is patterned using the color filter 170 to display a color filter on array (COA) structure. The number of exposure masks used during the manufacturing process of the substrate can be reduced.

Referring to FIG. 11, a third ashing process is performed to remove the residual part RP using an oxygen plasma. Accordingly, a second contact hole 174 is formed in the color filter 170 to expose the passivation layer 160 on the storage common line STL.

1 and 12, a transparent conductive material (not shown) is coated on the base substrate 110 on which the color filter 170 is formed. The transparent conductive material may be formed of, for example, ITO or IZO. Subsequently, the transparent conductive material is patterned by a photolithography process using a fourth mask MASK4 to form pixel electrodes 180 corresponding to the pixel portions P. Referring to FIG. Thus, the display substrate 100 according to the present invention is completed.

Meanwhile, a portion of the pixel electrode 180 that faces the storage common line STL is defined as the storage electrode unit 192. The storage capacitance is charged between the storage electrode unit 192 and the storage common line SLT to charge the pixel voltage for one frame. In particular, the second contact hole 174 may be formed in the color filter 170 to reduce the space between the storage common wiring STL and the storage electrode unit 192, thereby charging more storage capacitance.

Meanwhile, in the exemplary embodiment of the present invention, the color filter is formed using the negative photoresist, but the color filter may be formed using the positive photoresist. It will be apparent to those skilled in the art that when the color filter is formed using the positive photoresist, the third mask will be formed so that the exposed area and the shielded area are opposite to each other.

As described above, according to the present invention, the contact hole is formed on the color filter corresponding to the storage wiring in the display substrate having the COA structure, thereby reducing the distance between the storage common wiring and the storage electrode portion. As a result, more storage capacitance can be charged. In addition, since the color filter and the passivation film can be patterned using one exposure mask, the number of exposure masks used in the display substrate manufacturing process can be reduced. Accordingly, the manufacturing cost of the display substrate can be reduced.

Although described above with reference to the embodiments, those skilled in the art can be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below. I can understand.

Claims (8)

A plurality of gate wirings; A plurality of source wirings crossing the gate wirings; A plurality of pixel portions defined by the gate lines and source lines; A switching element formed in each pixel unit and including a gate electrode connected to the gate wiring, a source electrode connected to the source wiring, and a drain electrode spaced apart from the source electrode; A storage common line formed in the pixel portion and parallel to the gate line; A color filter formed in the pixel portion and having a first contact hole corresponding to one end of the drain electrode and a second contact hole corresponding to the storage common wiring; And And a pixel electrode formed on the color filter and connected to the drain electrode through the first contact hole and facing the storage common line through the second contact hole. The display substrate of claim 1, wherein a gate insulating layer and a passivation layer are formed between the pixel electrode and the storage common line. The display substrate of claim 1, further comprising a channel layer formed under the source wiring, the source electrode, and the drain electrode. The second contact hole of claim 1, wherein the second contact hole includes a first opening having a first area and a second opening connected to the first opening and having a second area narrower than the first area when viewed in a plan view. Display substrate, characterized in that. The display substrate of claim 4, wherein the height of the second opening is half the thickness of the color filter. Forming a first metal pattern on the substrate, the first metal pattern including a gate wiring, a gate electrode, and a storage common wiring; Forming a second metal pattern including a source wiring, a source electrode, and a drain electrode on the insulating layer covering the first metal pattern; Sequentially forming a passivation film and a color photoresist film on an entire surface of the insulating film on which the second metal pattern is formed; Patterning the color photoresist film to form a color filter including a first contact hole corresponding to one end of the drain electrode and a residual part corresponding to the storage common wiring, to a pixel part defined by the gate wiring and the source wiring; step; Etching the passivation film exposed through the first contact hole to expose one end of the drain electrode; Removing the residual part to form a second contact hole corresponding to the storage common wiring; And And forming a pixel electrode electrically connected to the drain electrode and facing the storage common line through the second contact hole. The method of claim 6, further comprising forming a channel layer between the insulating layer and the second metal pattern. The method of claim 7, wherein the forming of the second metal pattern Sequentially forming a semiconductor layer, an ohmic contact layer, and a source metal layer on the insulating layer; Patterning the source metal layer into an electrode pattern partially overlapping the source wiring and the gate electrode using a photoresist pattern; Etching the semiconductor layer and the ohmic contact layer using the source wiring and the electrode pattern as an etch mask to form the channel layer; Removing a predetermined thickness of the photoresist pattern to expose a portion of the electrode pattern; And And etching the exposed electrode pattern to form the source electrode and the drain electrode.

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