KR100592051B1 - 논리회로와그작성방법 - Google Patents

논리회로와그작성방법 Download PDF

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Publication number
KR100592051B1
KR100592051B1 KR1019980051132A KR19980051132A KR100592051B1 KR 100592051 B1 KR100592051 B1 KR 100592051B1 KR 1019980051132 A KR1019980051132 A KR 1019980051132A KR 19980051132 A KR19980051132 A KR 19980051132A KR 100592051 B1 KR100592051 B1 KR 100592051B1
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KR
South Korea
Prior art keywords
circuit
logic circuit
selector
delay time
input
Prior art date
Application number
KR1019980051132A
Other languages
English (en)
Korean (ko)
Other versions
KR19990045623A (ko
Inventor
야스히코 사사키
카즈오 야노
슈운조 야마시타
Original Assignee
가부시키가이샤 히타치세이사쿠쇼
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Publication of KR19990045623A publication Critical patent/KR19990045623A/ko
Application granted granted Critical
Publication of KR100592051B1 publication Critical patent/KR100592051B1/ko

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1737—Controllable logic circuits using multiplexers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
KR1019980051132A 1997-11-28 1998-11-27 논리회로와그작성방법 KR100592051B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP32753697A JP3701781B2 (ja) 1997-11-28 1997-11-28 論理回路とその作成方法
JP97-327536 1997-11-28

Publications (2)

Publication Number Publication Date
KR19990045623A KR19990045623A (ko) 1999-06-25
KR100592051B1 true KR100592051B1 (ko) 2006-12-01

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019980051132A KR100592051B1 (ko) 1997-11-28 1998-11-27 논리회로와그작성방법

Country Status (4)

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US (5) US6124736A (US06696864-20040224-M00004.png)
JP (1) JP3701781B2 (US06696864-20040224-M00004.png)
KR (1) KR100592051B1 (US06696864-20040224-M00004.png)
TW (1) TW461181B (US06696864-20040224-M00004.png)

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US7129755B2 (en) * 2004-04-09 2006-10-31 Broadcom Corporation High-fanin static multiplexer
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US7956421B2 (en) 2008-03-13 2011-06-07 Tela Innovations, Inc. Cross-coupled transistor layouts in restricted gate level layout architecture
US7908578B2 (en) 2007-08-02 2011-03-15 Tela Innovations, Inc. Methods for designing semiconductor device with dynamic array section
US7763534B2 (en) 2007-10-26 2010-07-27 Tela Innovations, Inc. Methods, structures and designs for self-aligning local interconnects used in integrated circuits
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US8541879B2 (en) 2007-12-13 2013-09-24 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US8653857B2 (en) 2006-03-09 2014-02-18 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US7446352B2 (en) 2006-03-09 2008-11-04 Tela Innovations, Inc. Dynamic array architecture
US8448102B2 (en) 2006-03-09 2013-05-21 Tela Innovations, Inc. Optimizing layout of irregular structures in regular layout context
US8658542B2 (en) 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US9009641B2 (en) 2006-03-09 2015-04-14 Tela Innovations, Inc. Circuits with linear finfet structures
US9035359B2 (en) 2006-03-09 2015-05-19 Tela Innovations, Inc. Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
US7741879B2 (en) * 2007-02-22 2010-06-22 Avago Technologies Enterprise IP (Singapore) Pte. Ltd. Apparatus and method for generating a constant logical value in an integrated circuit
US8667443B2 (en) 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US8453094B2 (en) 2008-01-31 2013-05-28 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US7939443B2 (en) 2008-03-27 2011-05-10 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
KR100933668B1 (ko) * 2008-04-30 2009-12-23 주식회사 하이닉스반도체 출력회로
MY152456A (en) 2008-07-16 2014-09-30 Tela Innovations Inc Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US9122832B2 (en) 2008-08-01 2015-09-01 Tela Innovations, Inc. Methods for controlling microloading variation in semiconductor wafer layout and fabrication
US8661392B2 (en) 2009-10-13 2014-02-25 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the Same
US9159627B2 (en) 2010-11-12 2015-10-13 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same
US8461902B2 (en) * 2011-01-27 2013-06-11 Advanced Micro Devices, Inc. Multiplexer circuit with load balanced fanout characteristics
US10151182B2 (en) 2013-02-22 2018-12-11 Samson Pump Company, Llc Modular top loading downhole pump with sealable exit valve and valve rod forming aperture
US8904322B2 (en) * 2013-03-26 2014-12-02 International Business Machines Corporation Structure for stacked CMOS circuits
US9122823B2 (en) 2013-12-20 2015-09-01 International Business Machines Corporation Stacked multiple-input delay gates

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JPH0818438A (ja) * 1994-06-29 1996-01-19 Nec Commun Syst Ltd ゲートアレー構成半導体装置
JPH0851355A (ja) * 1994-06-30 1996-02-20 Texas Instr Inc <Ti> 結合された異質のフィールドプログラマブル・ゲートアレイ論理モジュールのシステムとその形成方法
JPH0851354A (ja) * 1994-08-08 1996-02-20 Hitachi Ltd パストランジスタ型セレクタ回路及び論理回路
JPH0879039A (ja) * 1994-09-01 1996-03-22 Mitsubishi Denki Eng Kk 選択回路およびそれを用いた加算回路
JPH09121026A (ja) * 1995-08-18 1997-05-06 Chip Express Israel Ltd カスタマイズ可能な高速論理アレイ・デバイス

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Patent Citations (5)

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JPH0818438A (ja) * 1994-06-29 1996-01-19 Nec Commun Syst Ltd ゲートアレー構成半導体装置
JPH0851355A (ja) * 1994-06-30 1996-02-20 Texas Instr Inc <Ti> 結合された異質のフィールドプログラマブル・ゲートアレイ論理モジュールのシステムとその形成方法
JPH0851354A (ja) * 1994-08-08 1996-02-20 Hitachi Ltd パストランジスタ型セレクタ回路及び論理回路
JPH0879039A (ja) * 1994-09-01 1996-03-22 Mitsubishi Denki Eng Kk 選択回路およびそれを用いた加算回路
JPH09121026A (ja) * 1995-08-18 1997-05-06 Chip Express Israel Ltd カスタマイズ可能な高速論理アレイ・デバイス

Also Published As

Publication number Publication date
US20030071658A1 (en) 2003-04-17
US6400183B2 (en) 2002-06-04
US6124736A (en) 2000-09-26
US6486708B2 (en) 2002-11-26
KR19990045623A (ko) 1999-06-25
US20020149394A1 (en) 2002-10-17
US6323690B1 (en) 2001-11-27
JPH11161470A (ja) 1999-06-18
JP3701781B2 (ja) 2005-10-05
US6696864B2 (en) 2004-02-24
US20010054916A1 (en) 2001-12-27
TW461181B (en) 2001-10-21

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