KR100571655B1 - 랜딩 플러그 콘택 구조를 가진 반도체 소자 제조방법 - Google Patents
랜딩 플러그 콘택 구조를 가진 반도체 소자 제조방법 Download PDFInfo
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- KR100571655B1 KR100571655B1 KR1020040047263A KR20040047263A KR100571655B1 KR 100571655 B1 KR100571655 B1 KR 100571655B1 KR 1020040047263 A KR1020040047263 A KR 1020040047263A KR 20040047263 A KR20040047263 A KR 20040047263A KR 100571655 B1 KR100571655 B1 KR 100571655B1
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- 238000000034 method Methods 0.000 title claims abstract description 37
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 150000004767 nitrides Chemical class 0.000 claims abstract description 32
- 239000011229 interlayer Substances 0.000 claims abstract description 31
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 28
- 239000001257 hydrogen Substances 0.000 claims abstract description 28
- 125000006850 spacer group Chemical group 0.000 claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 claims abstract description 22
- 239000010410 layer Substances 0.000 claims abstract description 17
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 15
- 239000007789 gas Substances 0.000 claims abstract description 13
- 238000002161 passivation Methods 0.000 claims abstract description 11
- 230000008021 deposition Effects 0.000 claims abstract description 10
- 150000002431 hydrogen Chemical class 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims description 21
- 239000002019 doping agent Substances 0.000 claims description 20
- 238000005468 ion implantation Methods 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 6
- 238000005121 nitriding Methods 0.000 claims description 6
- 150000002500 ions Chemical class 0.000 claims description 4
- 238000009832 plasma treatment Methods 0.000 claims description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 230000004888 barrier function Effects 0.000 claims description 2
- 230000035515 penetration Effects 0.000 abstract description 10
- 238000010292 electrical insulation Methods 0.000 abstract description 6
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 230000003405 preventing effect Effects 0.000 abstract description 4
- 230000000903 blocking effect Effects 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 68
- 238000005530 etching Methods 0.000 description 6
- -1 hydrogen ions Chemical class 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 238000002955 isolation Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 230000000149 penetrating effect Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 230000009849 deactivation Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
종래기술 | 일 실시예 | 다른 실시예 | |
셀 문턱전압(Vt) | 0.66V | 0.89V | 0.88V |
드레인 포화전류(Idsat) | 29㎂ | 36㎂ | 34㎂ |
Bvds | 2.0V | 3.8V | 3.6V |
Claims (9)
- 게이트 산화막이 형성된 실리콘 기판 상에 하드 마스크 절연막을 구비하는 게이트 전극 패턴을 형성하는 단계;상기 게이트 전극 패턴의 측벽에 버퍼 산화막 스페이서 및 질화막 스페이서를 차례로 형성하는 단계;상기 게이트 전극 패턴 사이의 예정된 간극에 랜딩 플러그 콘택을 형성하는 단계;상기 랜딩 플러그 콘택이 형성된 전체 구조 표면에 수소 차단 특성을 가진 패시베이션층을 형성하는 단계; 및상기 패시베이션층이 형성된 전체 구조 상부에 층간절연막 - 증착시 소오스 가스로부터 수소(H)를 발생시키는 층간절연막임 - 을 형성하는 단계를 포함하는 반도체 소자 제조방법.
- 게이트 산화막이 형성된 실리콘 기판 상에 하드 마스크 절연막을 구비하는 게이트 전극 패턴을 형성하는 단계;상기 게이트 전극 패턴의 측벽에 버퍼 산화막 스페이서 및 질화막 스페이서를 차례로 형성하는 단계;상기 게이트 전극 패턴 사이의 예정된 간극에 랜딩 플러그 콘택을 형성하는 단계;상기 랜딩 플러그 콘택이 형성된 전체 구조 표면에 N형 도펀트를 도핑하는 단계; 및상기 N형 도펀트가 도핑된 전체구조 상부에 층간절연막 - 증착시 소오스 가스로부터 수소(H)를 발생시키는 층간절연막임 - 을 형성하는 단계를 포함하는 반도체 소자 제조방법.
- 제2항에 있어서,상기 N형 도펀트를 도핑하는 단계에서,이온주입 에너지 2∼50keV, 이온주입 도즈 1×1015∼1×1016ions/㎠ 조건을 사용하여 인(P) 또는 비소(As)를 도핑하는 것을 특징으로 하는 반도체 소자 제조방법.
- 제2항에 있어서,상기 N형 도펀트를 도핑하는 단계에서,N형 도펀트를 포함하는 가스를 사용한 플라즈마 처리를 수행하는 것을 특징으로 하는 반도체 소자 제조방법.
- 제2항에 있어서,상기 N형 도펀트를 도핑하는 단계에서,PH3 가스 도핑 공정을 수행하는 것을 특징으로 하는 반도체 소자 제조방법.
- 게이트 산화막이 형성된 실리콘 기판 상에 하드 마스크 절연막을 구비하는 게이트 전극 패턴을 형성하는 단계;상기 게이트 전극 패턴의 측벽에 버퍼 산화막 스페이서 및 질화막 스페이서를 차례로 형성하는 단계;상기 게이트 전극 패턴 사이의 예정된 간극에 랜딩 플러그 콘택을 형성하는 단계;상기 랜딩 플러그 콘택이 형성된 전체 구조 표면에 캡핑 질화막을 형성하는 단계; 및상기 캡핑 질화막이 형성된 전체구조 상부에 층간절연막 - 증착시 소오스 가스로부터 수소(H)를 발생시키는 층간절연막임 - 을 형성하는 단계를 포함하는 반도체 소자 제조방법.
- 제6항에 있어서,상기 캡핑 질화막을 형성하는 단계에서,저압화학기상증착(LPCVD) 또는 플라즈마화학기상증착(PECVD) 방식을 이용하여 질화막을 증착하는 것을 특징으로 하는 반도체 소자 제조방법.
- 제7항에 있어서,상기 캡핑 질화막을 형성하는 단계에서,질화 공정을 통해 기판 표면을 질화 시키는 공정을 수행하는 것을 특징으로 하는 반도체 소자 제조방법.
- 제7항 또는 제8항에 있어서,상기 캡핑 질화막은 50∼500Å 두께로 형성하는 것을 특징으로 하는 반도체 소자 제조방법.
Priority Applications (2)
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KR1020040047263A KR100571655B1 (ko) | 2004-06-23 | 2004-06-23 | 랜딩 플러그 콘택 구조를 가진 반도체 소자 제조방법 |
US10/968,940 US7186647B2 (en) | 2004-06-23 | 2004-10-21 | Method for fabricating semiconductor device having landing plug contact structure |
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KR1020040047263A KR100571655B1 (ko) | 2004-06-23 | 2004-06-23 | 랜딩 플러그 콘택 구조를 가진 반도체 소자 제조방법 |
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KR20050122103A KR20050122103A (ko) | 2005-12-28 |
KR100571655B1 true KR100571655B1 (ko) | 2006-04-17 |
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Cited By (1)
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KR101132721B1 (ko) | 2004-12-16 | 2012-04-06 | 매그나칩 반도체 유한회사 | 마스크 롬 장치의 제조방법 |
Families Citing this family (5)
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US7498188B2 (en) * | 2004-09-02 | 2009-03-03 | Aptina Imaging Corporation | Contacts for CMOS imagers and method of formation |
US7662082B2 (en) | 2004-11-05 | 2010-02-16 | Theragenics Corporation | Expandable brachytherapy device |
US7547621B2 (en) * | 2006-07-25 | 2009-06-16 | Applied Materials, Inc. | LPCVD gate hard mask |
KR101185988B1 (ko) * | 2009-12-30 | 2012-09-25 | 에스케이하이닉스 주식회사 | 반도체 메모리소자의 랜딩플러그컨택 형성방법 |
US10128016B2 (en) * | 2016-01-12 | 2018-11-13 | Asml Netherlands B.V. | EUV element having barrier to hydrogen transport |
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US6159839A (en) * | 1999-02-11 | 2000-12-12 | Vanguard International Semiconductor Corporation | Method for fabricating borderless and self-aligned polysilicon and metal contact landing plugs for multilevel interconnections |
TW418501B (en) * | 1999-08-25 | 2001-01-11 | Winbond Electronics Corp | Memory device with vertical landing plug contact and its manufacturing method |
TWI278958B (en) * | 2002-06-03 | 2007-04-11 | Hynix Semiconductor Inc | Method for fabricating semiconductor device |
KR20050002315A (ko) * | 2003-06-30 | 2005-01-07 | 주식회사 하이닉스반도체 | 반도체 소자의 제조 방법 |
KR100518233B1 (ko) * | 2003-10-31 | 2005-10-04 | 주식회사 하이닉스반도체 | 반도체 소자의 제조방법 |
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- 2004-06-23 KR KR1020040047263A patent/KR100571655B1/ko active IP Right Grant
- 2004-10-21 US US10/968,940 patent/US7186647B2/en active Active
Cited By (1)
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KR101132721B1 (ko) | 2004-12-16 | 2012-04-06 | 매그나칩 반도체 유한회사 | 마스크 롬 장치의 제조방법 |
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KR20050122103A (ko) | 2005-12-28 |
US20050287801A1 (en) | 2005-12-29 |
US7186647B2 (en) | 2007-03-06 |
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