KR100541156B1 - 반도체 소자의 제조 방법 - Google Patents
반도체 소자의 제조 방법 Download PDFInfo
- Publication number
- KR100541156B1 KR100541156B1 KR1020030002364A KR20030002364A KR100541156B1 KR 100541156 B1 KR100541156 B1 KR 100541156B1 KR 1020030002364 A KR1020030002364 A KR 1020030002364A KR 20030002364 A KR20030002364 A KR 20030002364A KR 100541156 B1 KR100541156 B1 KR 100541156B1
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- Prior art keywords
- oxide film
- layer
- porous oxide
- metal wiring
- trench
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02203—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being porous
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (5)
- 반도체 구조물 상부에 상기 초저유전율을 갖는 다공질 산화막을 증착하는 단계;상기 다공질 산화막을 패터닝 하여 금속배선용 홀을 형성하는 단계;상기 금속배선용 홀 측벽에 상기 다공질 산화막의 표면에 형성된 기공들을 매립하기위해 중성 리간드를 사용하는 단원자층 증착법을 이용하여 스페이서 형태의 단원자층 산화막을 형성하는 단계; 및전체 구조 상부에 베리어 금속층 및 씨드층을 단차를 따라 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 제조 방법.
- 반도체 구조물 상부에 제 1 식각 방지막, 제 1 다공질 산화막, 제 2 식각 방지막 및 제 2 다공질 산화막을 순차적으로 증착하는 단계;상기 제 2 다공질 산화막, 상기 제 2 식각 방지막 및 제 1 다공질 산화막을 패터닝 하여 비아홀을 형성하는 단계;상기 제 2 다공질 산화막 및 상기 제 2 식각 방지막을 패터닝 하여 상기 비아홀 보다 개구부가 넓은 트렌치를 형성하는 단계;상기 비아홀 및 상기 트렌치 측벽에 상기 다공질 산화막의 표면에 형성된 기공들을 매립하기위해 중성 리간드를 사용하는 단원자층 증착법을 이용하여 스페이서 형태의 단원자층 산화막을 형성하는 단계; 및상기 비아홀 및 상기 트렌치를 금속으로 매립하여 듀얼 다마신 패턴의 금속 배선을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 제조 방법.
- 제 1 항 또는 제 2 항에 있어서,상기 중성 리간드는 VTMOS(Vinyltrimethoxysilane; (OCH3)3SiCHCH2), ATMS(Allyltrimethylsilane; (CH3)3SiCHCH2) 및 VTMS(Vinyltrimethylsilane; (CH3)3SiCH2CHCH2)등을 사용하여 증착하는 것을 특징으로 하는 반도체 소자의 제조 방법.
- 제 3 항에 있어서,상기 중성 리간드 환원 기체로 산소(O2)가스 또는 오존(O3)가스를 이용하는 것을 특징으로 하는 반도체 소자의 제조 방법.
- 제 1 항 또는 제 2 항에 있어서,상기 단원자층 산화막을 VTMS((CH3)3SiCHCH2) 중성리간드를 사용하여 증착할 경우, 25 내지 400℃의 증착온도, 0.01 내지 10torr의 반응기 압력과 2 내지 1000sccm의 Ar가스와 2 내지 1000sccm의 O2 가스를 주입하여 10 내지 500Å 두께의 단원자층 산화막을 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법.
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KR1020030002364A KR100541156B1 (ko) | 2003-01-14 | 2003-01-14 | 반도체 소자의 제조 방법 |
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KR1020030002364A KR100541156B1 (ko) | 2003-01-14 | 2003-01-14 | 반도체 소자의 제조 방법 |
Publications (2)
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KR20040065401A KR20040065401A (ko) | 2004-07-22 |
KR100541156B1 true KR100541156B1 (ko) | 2006-01-11 |
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KR101198937B1 (ko) * | 2005-12-28 | 2012-11-07 | 매그나칩 반도체 유한회사 | 반도체 장치의 금속배선 형성방법 |
JP7193731B2 (ja) * | 2019-03-29 | 2022-12-21 | 東京エレクトロン株式会社 | エッチング方法及びエッチング装置 |
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