KR100490812B1 - Self-aligned coaxial via capacitors - Google Patents

Abstract

Various embodiments of coaxial capacitors are formed self-aligned in vias that include blind vias, buried vias, and plated through holes. The coaxial capacitor is applied to use plating 125 of plated vias as the first electrode. The dielectric layer 130 is formed so that a portion of the via lies on the first electrode 125. The second electrode 135 is formed in the portion of the via not filled by the dielectric layer 130. Such coaxial capacitors are suitable for use in decoupling and power dampening applications to reduce or reduce signal and power noise in electronic devices, or to reduce overshoot and droop in power. For this application, it is generally expected that a plurality of coaxial capacitors, often several thousand, will be combined in parallel to achieve the desired level of capacitors.

Description

Self Aligning Coaxial Via Capacitors {SELF-ALIGNED COAXIAL VIA CAPACITORS}

The present invention relates generally to capacitors, and more particularly to self-aligned coaxial capacitors formed in vias, an apparatus using the capacitors and a method of manufacturing the same.

Electronic circuits, especially computers and instrumentation circuits, have become more powerful and faster in recent years. As circuit frequencies exceed hundreds of MHz as the relevant spectral components exceed 10 GHz, noise in DC power and ground lines becomes increasingly problematic. Such noise can occur as is known, for example because of inductive and capacitive parasitics. To reduce such noise, capacitors, known as decoupling capacitors, are often used to provide a stable signal or stable power to the circuit. Decoupling capacitors are generally located as close to the load as possible to increase the effect.

Capacitors slow down the droop of power when the electronic device begins to use power, such as the immediate demand of the voltage caused by the processor performing the calculation, and slow down overshoot of the power when the electronic device is turned on. It is also used to make it work.

Often, capacitors are surface mounted in electronic devices such as a processor or a package substrate on which the processor is mounted. Another solution includes the formation of planar capacitors implemented or integrated within substrates such as high density interconnect (HDI) substrates and ceramic multilayer structures. As electronic devices continue to advance, the need for higher levels of capacitance for decoupling and power damping at reduced inductance levels increases.

With increasingly reduced device size and packing density, the available real estate for capacitors mounted on the surface is a limiting factor. In addition, for planar capacitors, higher and higher capacitances require larger surface areas. This increases the risk of shorting or leakage, reducing the yield of the device and increasing the concern for the reliability of the device.

As can be seen from the above interest, there is a need for an alternative capacitance solution for the fabrication and operation of electronic integrated circuit devices.

Summary of the Invention

In one embodiment, the present invention provides a capacitor. The capacitor includes a via having sidewalls defined by the substrate and extending from the first side of the substrate to the second side of the substrate, the first side extending outwardly from the sidewalls. The capacitor further includes a first electrode lying on the sidewalls of the via and at least a portion of the first side of the substrate. The capacitor also lies in at least a first portion of the first electrode and further includes a dielectric layer formed such that the remaining portion of the via is not filled, wherein the first portion of the first electrode is present in the sidewalls. The capacitor also further includes a second electrode formed in the remaining portion of the via.

In another embodiment, the present invention provides a method of manufacturing a capacitor. The method includes forming sidewalls of the via and a first electrode layer overlying at least a portion of the first side of the substrate, the sidewalls of the via extending from the first side of the substrate to the second side of the substrate. Defined by some, the first face extends outwardly from the side walls. The method further includes forming a dielectric layer overlying at least a first portion of the first electrode layer, with a portion of the via not filled, wherein the first portion of the first electrode layer is in the sidewalls. The method also further includes forming a second electrode comprising forming a conductive material in the portion of the via not filled by the dielectric layer.

In another embodiment, the present invention provides a method of operating an electronic device. The method includes coupling a first electrode for each of the plurality of capacitors to a first potential. The method further includes coupling a second electrode for each of the plurality of capacitors to a second potential. Each of the plurality of capacitors is a self-aligned coaxial capacitor formed in one of the plurality of vias of the substrate supporting the electronic device and formed in a one-to-one relationship to the plurality of vias.

In another embodiment, the present invention provides an electronic device. The electronic device includes a first potential source, a second potential source and at least one capacitor. At least one capacitor includes a via having sidewalls defined by the substrate and extending from the first side of the substrate to the second side of the substrate, the first side extending outwardly from the sidewalls. The at least one capacitor further comprises a first electrode overlying the sidewalls of the via and at least a portion of the first side of the substrate. The at least one capacitor also lies in at least a first portion of the first electrode and further includes a dielectric layer formed such that the remaining portion of the via is not filled, wherein the first portion of the first electrode is in the sidewalls. The at least one capacitor also includes a second electrode formed in the remaining portion of the via.

Other embodiments of the invention include methods, apparatus, and systems of varying scope.

1A-1F are cross-sectional views of self-aligned coaxial capacitors at various processing steps.

2 is a cross-sectional view of a self-aligned coaxial capacitor.

3A-3F are cross-sectional views of self-aligned coaxial capacitors at various processing steps.

DETAILED DESCRIPTION In the following detailed description, reference is made to the accompanying drawings, some of which are shown here as specific embodiments in which the invention may be practiced. These embodiments are described in detail so that those skilled in the art can practice the invention, other embodiments can be used, and structural, logical and electrical changes can be made without departing from the spirit and scope of the invention. It will be understood that it can be done. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention may be limited only by the appended claims and equivalents thereto. Like numbers in the drawings indicate like elements and are apparent from the description.

Various embodiments will be described with capacitors implemented for microprocessor package applications. One example of a microprocessor package is a package of integrated circuit semiconductor die mounted on a printed circuit board (PCB), where the PCB is physically retained and the auxiliary circuits and components facilitate the use of the processor contained in the die. However, the present invention is not so limited. Those skilled in the art will appreciate that various embodiments of the present invention may be utilized in connection with other electronic devices in addition to motherboards and other printed circuit boards, high density interconnect (HDI) substrates, and other multilayer electronic substrates such as ceramic multilayer substrates. It will be appreciated that this applies to use. In addition, various embodiments describe the manufacture and characterization of capacitors as substantially cylindrical structures. However, other geometries are suitable for use in various embodiments if the mathematical characterization is modified for obvious differences in geometry.

1A shows a via 105. The via is an opening that extends through at least one layer of the substrate and is used to electrically interconnect circuitry on one layer of the substrate with circuitry on the surface opposite the layer or circuitry on one or more other layers of the substrate. Typical vias have a diameter of approximately 150 μm and a length of approximately 25-40 μm when extending through a single layer of the substrate 100. Substrate 100 may have one or more layers. The via 105 may be bound up and / or down by additional layers of the substrate 100. Vias bounded only at one end are often called blind vias. Vias bounded at both ends are often referred to as buried vias. Vias that extend through all layers of the substrate 100 are often referred to as through holes. Typical through holes have a diameter of approximately 250 μm and a length of approximately 800 μm. While the foregoing examples of via sizes are generally contemplated, various embodiments of the present invention are not limited to such sizes. In addition, subsequent exemplary sizes are likewise not limiting. It can be seen that the trend in the industry is to generally reduce the size of the device for the associated cost and performance benefits.

The via 105 is defined by the substrate 100 and has sidewalls 110 extending from the first surface 115 of the substrate 100 to the second surface 120 of the substrate 100. The vias 105 are formed by known methods to form openings in the substrate. Examples include laser drilling and mechanical drilling. First side 115 and second side 120 extend outwardly from sidewalls 110.

In FIG. 1B, the first electrode 125 is formed on the sidewalls 110. In one embodiment, the first electrode 125 further extends to lie at least a portion of the first surface 115 and at least a portion of the second surface 120. In another embodiment, the first electrode 125 may extend so as to lie on at least a portion of the first side 115, but not on any portion of the second side 120. First electrode 125 generally represents a conductive layer that is formed as part of standard processing to form vias 105 and used for interconnection. After forming the first electrode 125, the vias are generally considered plated vias or plated through holes.

In the use of the via 105, the first electrode 125 is generally used to connect a circuit on the first side 115 to a circuit on the second side 120. Additionally or alternatively, the first electrode can be used to connect a circuit on the first face 115 to a circuit on various intermediate layers between the first face 115 and the second face 120. In one embodiment, the first electrode 125 includes copper (Cu). Copper is a common plating material used to manufacture printed circuit boards (PCBs). In one embodiment, first electrode 125 deposits a seed layer, such as sputter-deposited or electroless-deposited copper, onto substrate 100 and then seed layer. A copper layer is electroplated on it.

In another embodiment, the first electrode 125 is formed using standard photolithography techniques. This technique involves patterning a photolithography mask on one side of the substrate 100, leaving portions of the substrate 100 exposed, where it is desired to form the first electrode 125. . The conductive material layer is then deposited on the exposed portions by physical or chemical vapor deposition (PVD or CVD) to remove the mask and the deposited material thereon. Other methods of depositing the first electrode, such as screen printing or printing of other conductive inks, will be apparent to those of ordinary skill in the art.

In FIG. 1C, dielectric layer 130 is formed comprising a dielectric material. In one embodiment, dielectric layer 130 includes a metal oxide, such as tantalum oxide (Ta ₂ O ₅ ). The metal oxide of one embodiment may be formed by sputter deposition from a metal target to form a metal layer, and may be formed by anodizing the metal layer in an electrolyte of weak acid to form the metal oxide. In one embodiment, the weak acid electrolyte is an organic acid, such as less than about 5% citric acid dilute nonaqueous solution by weight. This weak acid electrolyte is expected to produce a membrane with lower inclusions, thereby lower stress. The thickness of the oxide can be controlled through the application of a controlled voltage. For example, when using a tantalum layer for the formation of a metal oxide, an applied voltage of approximately 60V would produce a thickness of approximately 900 kV tantalum oxide. Leaving an unoxidized metal in the dielectric layer 130 is important because the metal is present at the interface between the first electrode 125 and the dielectric layer 130 and its conductivity does not adversely affect the final capacitance. Not.

Through the use of a shadow mask 185, a metal layer, such as tantalum, may be deposited in the areas not covered by the shadow mask 185 by PVD. The shadow mask 185 is a mechanical mask placed on or in proximity to the substrate 100 to prevent or mask areas that do not wish to be deposited. In one embodiment, a PVD process, such as sputtering, is performed from both sides 115 and 120 of the substrate 100 such that the dielectric layer 130 is also placed on a portion of the second side 120 in addition to a portion of the first side 115. Is formed. In another embodiment, a PVD process, such as sputtering, is only performed from the first side 115 of the substrate 100 such that the dielectric layer 130 lies on a portion of the first side 115 but a portion of the second side 120. It is formed so as not to lie. Alternatively, the metal layer may be deposited by electrolytic plating or photolithography techniques and converted into metal oxides by anodization in the electrolyte of weak acid.

In embodiments using anodization or similar reaction processes to form the dielectric layer 130, the underlying first electrode 125 is susceptible to attack. It may be beneficial to protect the exposed areas of the first electrode 125 from such an attack. One example includes applying a protective layer, such as a patterned photoresist material, to the exposed portion of the first electrode 125 before anodizing the dielectric layer 130. Another example is to selectively apply only that portion of the metal blanket layer that defines the dielectric layer 130 of the future, such as applying a blanket layer of metal over the first electrode 125 and using a patterned photoresist material. And anodizing. After converting the metal to the corresponding metal oxide, the protective layer and other overlying material will be removed. In addition, an adhesion layer is applied to the first electrode 125 prior to forming the dielectric layer 130, and the adhesion layer protects the exposed portions of the first electrode 125 while forming the dielectric layer 130. Will contribute to

In addition, dielectric layer 130 may be formed through reactive sputtering from multiple element targets or by RF sputtering from a composite target of dielectric material without anodizing or other oxidation techniques. Organometallic CVD (MOCVD) and sol-gel techniques are further used to directly form metal oxide dielectrics. Other techniques for forming the dielectric material layer are known and may include chemical vapor deposition (CVD) and plasma chemical vapor deposition (PECVD). In addition, other dielectric materials may be used in various embodiments. Examples of other dielectric materials are strontium titanate (SrTiO ₃ ), barium titanate (BaTiO ₃ ), barium strontium titanate (BaSrTiO ₃ ; BST), lead zirconium, which are often formed by MOCVD or by sputtering from a composite target Titanate (PbZrTiO ₃ ; PZT), aluminum oxide (Al ₂ O ₃ ) or zirconium oxide (Zr ₂ O ₃ ). Examples also include more conventional dielectric materials such as silicon dioxide (SiO ₂ ), silicon nitride (SiN), and silicon oxynitride (SiO _x N _y ).

The designer must consider operating conditions, especially temperature, when choosing the deposition technique. Organic substrates generally require processing temperatures below approximately 250 ° C., while some of the deposition techniques described above may require operating temperatures above approximately 550 ° C. As an example, many metal oxides with high dielectric constants, such as the titanates described above, use an annealing process or a high temperature densification process following deposition to obtain the maximum value of the dielectric constant. This densification process can reach temperatures of approximately 700-1000 ° C. and may not be suitable for organic substrates. However, this densification process would be suitable for substrates having high temperature resistance, such as ceramic substrates. In some embodiments, bonding the dielectric material to the first electrode 125 may be enhanced through control of the first electrode 125, such as black oxide treatment of the copper electrode. However, this treatment is generally undesirable because it can roughen the copper surface and cause defects in subsequent dielectric layers.

The dielectric layer 130 is formed to lie in at least a first portion of the first electrode 125, and the first portion of the first electrode 125 is a portion present in the sidewalls 110. In addition, the dielectric layer 130 is formed so that the remaining portion of the via 105 is not filled. As illustrated in FIG. 1C, as described above in one embodiment, the dielectric layer 130 may extend to lie in a second portion of the first electrode 125 lying on a portion of the first face 115. This second portion of the first electrode 125 may further lie on a portion of the second face 120. The extension of the dielectric layer 130 over the second portion of the first electrode 125 provides some advantage with regard to the separation of the first electrode 125 and subsequent electrodes, which will become apparent below. However, at least a portion of the first electrode 125 on the first face 115 remains uncovered by the dielectric layer 130.

In FIG. 1D, the second electrode 135 is formed in the remaining portion of the via 105 that is not filled by the dielectric layer 130. In one embodiment, the second electrode 135 is formed by filling the remainder of the via 105 with conductive paste. In one embodiment, the conductive paste is cured.

Alternatively, electroless plating, followed by electrolytic plating of a metal such as copper, may be used in one embodiment to form an electroplated metal layer that is placed on dielectric layer 130 as second electrode 135. . In this embodiment, the second electrode 135 will generally have a hollow structure defined by the structure of the remaining portion of the via 105 that is not filled by the dielectric layer 130. The rest of 105) can be filled completely. Any portion of the vias 105 that are not filled by the resulting electroplated metal layer in this embodiment may optionally be filled with, for example, known polymer via plugs. As in many of the methods described for the formation of the first electrode 125, other methods also form a conductive material as the second electrode 135 in the remaining portion of the via 105 that is not filled by the dielectric layer 130. Can be used to

In FIG. 1E, excess portion of the second electrode 135 is removed if necessary to separate the first electrode 125 from the second electrode 135. In one embodiment, removal of excess portion of second electrode 135 includes chemical-mechanical planarization (CMP) to physically abrad the material. Removing the excess portion of the second electrode 135 includes removing a portion of the dielectric layer 130 lying on the first side 115 or the second side 120. In order to reduce the possibility of shorting or bridging between the first electrode 125 and the second electrode 135, the dielectric layer 130 on the first and second surfaces 115 and 120 is disposed. It is desired to keep at least some, but this is not necessary. In addition, removing the excess portion of the second electrode 135 may include all materials placed on the second surface 120, that is, the second electrode 135, the dielectric layer 130, and the first electrode placed on the second surface 120. May include removing a portion of 125. As shown in FIG. 1E, removal of the excess portion of the second electrode 135 may leave a separate portion 137 on the surface of the first electrode 125. However, this separated portion 137 of the second electrode 135 is not important because it is separated from the second electrode 135 by the dielectric layer 130 and does not interfere with the function of the first electrode 125.

In FIG. 1F, the first insulating layer 150 is formed by being placed on the first electrode 125, the dielectric layer 130, and the second electrode 135, and a part of the first electrode 125 and the second electrode 135. Is patterned to expose a portion of the. The contacts 140 and 142 are formed to engage with the exposed portions of the first electrode 125 and the second electrode 135, respectively. In FIG. 1F, contacts 140 and 142 are formed adjacent to first surface 115, but one or both of the contacts may optionally be coupled to respective electrodes adjacent to second surface 120. The second insulating layer 155 is formed on the contacts 140 and 142 and the first insulating layer 150, and is patterned to expose a portion of the contact 140 and a portion of the contact 142. The exposed portion of contact 140 is coupled to a first potential source, such as ground potential 160, and the exposed portion of contact 142 is coupled to a second potential source, such as supply potential Vcc 165. The resulting self-aligned coaxial capacitor 170 is subjected to decoupling and power damping, as described above in this configuration, but the capacitor 170 can be used in any electronic device application.

The capacitance of the capacitor 170 can be estimated using the following formula (see FIG. 2).

Where ε _r is the dielectric constant (8.854 x 10 ^-12 F / m), ε ₀ is the dielectric constant of the dielectric material, r ₂ is the distance from the center of the coaxial structure to the first electrode, and r ₂ is the second The radius of the electrode (r ₂ -r ₁ is the thickness of the dielectric layer) and L is the length of the via in meters.

As the power and frequency requirements of the microprocessor increase, the capacitance requirements for decoupling and power buffering also increase. Capacitors formed in accordance with the above-described embodiments will generally be smaller than usual in batches for such applications. However, the increasing complexity of the microprocessor package increases the number of vias and through holes in the design of the support substrate. For example, modern microprocessor packages have an average diameter of 150 μm (after plating) and an average length of 30 μm in addition to approximately 2000 plated through holes having an average diameter of 250 μm (after plating) and a length of 800 μm. It may have more than one plated via. Each of the plated vias and through holes are coupled to supply and ground potentials as described above, so that they are added to form parallel capacitance. The coupling capacitance for the microprocessor package can be adjusted to a desired value by controlling the number of vias used as a capacitor, the thickness of the dielectric material and the dielectric. For example, using a tantalum oxide dielectric material having a dielectric thickness of approximately 0.1 μm and a dielectric constant of approximately 25 in all plated vias and plated through-holes, a coupling capacitance of approximately 3 μs is achieved for the microprocessor package of this example. Can be obtained. As another example, using a BST dielectric material having a dielectric constant of approximately 500, a dielectric thickness of approximately 0.05 μm in plated vias and a dielectric thickness of approximately 0.30 μm in plated through-holes, Coupling capacitance can be obtained for the microprocessor package of this example.

Although the above embodiments described the formation of a capacitor in a via having openings on both sides of the substrate, the blind vias only extend partially through the substrate. 3A-3F illustrate one embodiment of a coaxial via capacitor formed in a blind via. Subsequent formation of the layer overlying the substrate causes the blind vias to be buried vias. Guidelines for materials and methods of forming individual layers are generally as provided above with reference to FIGS. 1A-1F. Note the exception.

3A shows via 305. The via 305 extends through at least one layer 302 of the substrate 300 but does not extend through the substrate 300. Via 305 ends in second layer 304 of substrate 300 exposing at least a portion of a metal or other conductive run 306. Layer 302 may represent one or more layers of substrate 300. Likewise, layer 304 can represent one or more layers of substrate 300.

Via 305 is defined by layer 302 of substrate 300, and sidewalls 310 extend from first side 315 of substrate 300 to second side 320 of substrate 300. Has The first surface 315 extends outward from the sidewalls 310. The second face 320 extends inwardly from the side walls 310. The via 305 is formed by a known method of forming openings in the substrate. Examples include laser drilling and mechanical drilling. For this purpose, it will be assumed that the second face 320 is substantially flat. However, the forming technique used to form the vias 305 may produce a second face 320 that is non-planar, such as concave or conical.

In FIG. 3B, in one embodiment, the first electrode 325 is formed on the sidewalls 310 and the second surface 320. In another embodiment, the first electrode 325 lies on the sidewalls 310 but is formed to expose a portion of the second surface 320. This embodiment can be obtained by forming the first electrode 325 before laminating the layers 302, 304.

The first electrode 325 further extends to lie at least a portion of the first face 315. The first electrode 325 is generally formed as part of the standard treatment of forming the via 305. In the use of the via 305, the first electrode 325 is generally used to connect the circuit on the first face 315 with a circuit coupled to the conductive run 306. Additionally or alternatively, the first electrode 325 connects the circuit on the first face 315 through additional conductive runs to the circuit on the various interlayers between the first face 315 and the second face 320. Can be used to connect. In one embodiment, the first electrode 325 includes copper (Cu).

In FIG. 3C, dielectric layer 330 is formed containing a dielectric material. The dielectric layer 330 is formed so as to lie in at least a first portion of the first electrode 325, and the first portion of the first electrode 325 is a portion present in the sidewalls 310. In addition, the dielectric layer 330 is formed so that the remaining portion of the via 305 is not filled. As shown in FIG. 3C, the dielectric layer 330 may extend to lie in a second portion of the first electrode 325 lying on a portion of the first face 315. The extension of the dielectric layer 330 over the second portion of the first electrode 325 provides some advantage with regard to the separation of the first electrode 325 and the subsequent electrode, which will be apparent below. However, at least a portion of the first electrode 325 on the first side 315 remains uncovered by the dielectric layer 330. In one embodiment, dielectric layer 330 may be formed using physical vapor deposition and may be defined by shadow mask 385 as described above with reference to FIG. 1C. Alternative embodiments use other dielectric materials and deposition techniques as described above with reference to dielectric layer 130.

In FIG. 3D, the second electrode 335 is formed in the remaining portion of the via 305 not filled by the dielectric layer 330. In one embodiment, the second electrode 335 is formed by filling the remaining portion of the via 305 with a conductive paste. In one embodiment, the conductive paste is cured.

Alternatively, electroless plating, followed by electrolytic plating of metals such as copper, can be used in one embodiment to form an electroplated metal layer that is placed on dielectric layer 330 as second electrode 335. In this embodiment, the second electrode 335 will generally have a hollow structure defined by the structure of the remaining portion of the via 305 not filled by the dielectric layer 330, and the remainder of the via 305 The part can be filled completely. Any portion of the via 305 that is not filled by the resulting electroplated metal layer in this embodiment may optionally be filled with, for example, a known polymer via plug. As in many of the methods described for the formation of the first electrode 125, other methods also form a conductive material as the second electrode 335 in the remaining portion of the via 305 not filled by the dielectric layer 330. Can be used to

In FIG. 3E, excess portion of the second electrode 335 is removed if necessary to separate the first electrode 325 from the second electrode 335. In one embodiment, removal of excess portion of second electrode 335 includes chemical-mechanical planarization (CMP) to physically wear the material. Removing the excess portion of the second electrode 335 includes removing a portion of the dielectric layer 330 lying on the first face 315. In order to reduce the possibility of shorting or bridging between the first electrode 325 and the second electrode 335, it is desired to retain at least a portion of the dielectric layer 330 lying on the first face 315, but this is not necessary. . As shown in FIG. 3E, removal of the excess portion of the second electrode 335 will leave a separate portion 337 on the surface of the first electrode 325. However, this separated portion 337 of the second electrode 335 is not important because it is separated from the second electrode 335 by the dielectric layer 330 and does not interfere with the function of the first electrode 325.

In FIG. 3F, the first insulating layer 350 is formed while lying on the first electrode 325, the dielectric layer 330, and the second electrode 335, and a part of the first electrode 325 and the second electrode 335. Is patterned to expose a portion of the. The contacts 340 and 342 are formed to engage with the exposed portions of the first electrode 325 and the second electrode 335, respectively, and the contacts 340 and 342 are both formed adjacent to the first surface 315. . The second insulating layer 355 is formed while lying in the contacts 340 and 342 and the first insulating layer 350, and is patterned to expose a portion of the contact 340 and a portion of the contact 342. The exposed portion of contact 340 is coupled to a first potential source, such as ground potential 360, and the exposed portion of contact 342 is coupled to a second potential source, such as supply potential Vcc 365. The resulting self-aligned coaxial capacitor 370 is applied to decoupling and power buffering, as described above in this structure, but the capacitor 370 can be used for any electronic device application.

Various embodiments of coaxial capacitors formed in vias have been described. Various embodiments are self-aligned in that the opening defining the second electrode is substantially centered in the via by the nature of the deposition of the first electrode and the dielectric layer. This self-aligning property uses the embodiment described above to fill a plated via with a dielectric material, followed by drilling an opening through the dielectric material to remove some of the dielectric material and forming a second electrode in the opening. To distinguish them from the capacitors formed therein. Self-aligned coaxial capacitors can be used to simultaneously form thousands of capacitors, but many applications require fewer process steps because drilling holes through the dielectric material will generally be limited to approximately 20 or less at a time. do. Self-aligned coaxial capacitors can be formed with thinner dielectric layers, allowing higher levels of capacitance for a given via diameter. The deposition techniques described herein allow more control over the ultimate thickness of the dielectric layer, allowing more freedom in integrated circuit design. Because the second electrode of various embodiments is more centered than drilling openings in the dielectric material, reduced process variability is allowed allowing for tighter design tolerances and resulting gains in performance and reliability. . The registration accuracy of laser or mechanical drilling is currently about 20 μm, limiting the dielectric thickness to about 20 μm. Accordingly, self-aligned coaxial capacitors of various embodiments are capable of inductance values of one to two orders of magnitude smaller than capacitors formed by drilling openings in dielectric materials.

The coaxial capacitors of the various embodiments are suitable for use in decoupling and power buffer applications. In such applications, it is generally expected that a plurality of coaxial capacitors, often several thousand, will be combined in parallel to achieve the desired level of capacitance. By forming capacitors in the vias, substantially no additional real estate, i.e., surface area, is required.

Although specific embodiments have been shown and described herein, those skilled in the art will understand that any arrangement calculated to achieve the same purpose may be substituted for the specific embodiments shown. Many applications of the invention will be apparent to those of ordinary skill in the art. Accordingly, this application is intended to cover any adaptations or variations of the present invention. It is manifestly apparent that this invention is limited only by the following claims and equivalents thereof.

Claims (30)

A via extending from the first side of the substrate to the second side of the substrate with sidewalls defined by the substrate, the first side extending outwardly from the sidewalls, A first electrode overlying at least a portion of the first side of the substrate and the sidewalls of the via, A dielectric layer overlying at least a first portion of the first electrode, the first portion of the first electrode being in the sidewalls, the remaining portion of the via not filled; and A second electrode formed in the remaining portion of the via Including, The second electrode completely fills the via such that an external contact to the second electrode is external to the via in the layer on the substrate adjacent to the first surface and is connected to an electronic component, And the first electrode, the second electrode and the dielectric layer are configured as self-aligned coaxial capacitors having a substantially cylindrical structure. The method of claim 1, And the first electrode comprises copper and the dielectric layer comprises tantalum oxide. The method of claim 1, And the dielectric layer further lies on a second portion of the first electrode lying on the first face. The method of claim 1, A first contact connected to the first electrode and a first potential source and A second contact connected to the second electrode and a second potential source Capacitor comprising a further. The method of claim 1, And the substrate is selected from the group consisting of an organic substrate and a ceramic substrate. The method of claim 1, And the substrate comprises one or more layers. A via extending from the first side of the substrate, the first side extending outwardly from the sidewalls, to the second side of the substrate, having sidewalls defined by the substrate, A first electrode lying on at least a portion of the sidewalls of the via and the first and second surfaces of the substrate, A dielectric layer lying on at least a first portion of the first electrode, the first portion of the first electrode being in the sidewalls, and deposited so that the remaining portion of the via is not filled; A second electrode formed in the remaining portion of the via Including, The second electrode completely fills the via such that an external contact to the second electrode is external to the via in the layer on the substrate adjacent to the first surface and is connected to an electronic component, And the first electrode, the second electrode and the dielectric layer are configured as self-aligned coaxial capacitors having a substantially cylindrical structure. The method of claim 7, wherein And the second side of the substrate extends outwardly from the sidewalls. The method of claim 7, wherein And the dielectric layer further lies on a second portion of the first electrode lying on the first face. A second side of the substrate from the first side of the substrate, the first side extending outwardly from the sidewalls, the second side extending inwardly from the sidewalls, having sidewalls defined by the substrate; A beer extending to A first electrode lying on at least a portion of the sidewalls of the via and the first and second surfaces of the substrate, A dielectric layer lying on at least a first portion of the first electrode, the first portion of the first electrode extending from the first side to the second side; formation of the dielectric layer allows the via to be removed without removal of a portion of the dielectric layer Prevents part of the from being filled-, and A second electrode formed while completely filling the portion of the via not filled by the dielectric layer Including, The second electrode is formed such that an external contact to the second electrode is external to the via in a layer on the substrate adjacent to the first surface and connected to an electronic component. And the first electrode, the second electrode and the dielectric layer are configured as self-aligned coaxial capacitors having a substantially cylindrical structure. Sidewalls of the via and at least a portion of the first side of the substrate, wherein the sidewalls of the via are defined by a portion of the substrate extending from the first side of the substrate to the second side of the substrate, the first side Forming a first electrode layer overly extending from the sidewalls; Forming a dielectric layer overlying at least a first portion of the first electrode layer, the first portion of the first electrode layer being within the sidewalls, wherein a portion of the via is not filled; and Forming a second electrode comprising forming a conductive material in the portion of the via not filled by the dielectric layer Including, The second electrode completely fills the via such that an external contact to the second electrode is external to the via in the layer on the substrate adjacent to the first surface and is connected to an electronic component, And the first electrode, the second electrode and the dielectric layer are formed as self-aligned coaxial capacitors having a substantially cylindrical structure. The method of claim 11, Forming the first electrode layer further comprises forming a copper layer. The method of claim 11, Forming the dielectric layer, Forming a metal layer overlying at least a first portion of the first electrode layer, the first portion of the first electrode layer being within the sidewalls, wherein a portion of the via is not filled, and Anodizing the metal layer to form the dielectric layer Capacitor forming method further comprising. The method of claim 11, Forming the dielectric layer, Sputtering a metal layer overlying at least a first portion of the first electrode layer, the first portion of the first electrode layer being within the sidewalls, wherein a portion of the via is not filled; And Anodizing the metal layer in a weak acid electrolyte to form the dielectric layer Capacitor forming method further comprising. The method of claim 14, The electrolyte of the weak acid is a capacitor forming method characterized in that it comprises an organic acid dilute non-aqueous solution. The method of claim 15, And said organic acid dilute non-aqueous solution is a non-aqueous solution of citric acid which is less than approximately 5% by weight. The method of claim 11, Forming a second electrode further comprises filling the portion of the via not filled by the dielectric layer with a conductive paste. The method of claim 11, Forming the second electrode further includes removing excess material such that the first electrode is separated from the second electrode. The method of claim 18, Removing the excess material further includes removing a portion of the dielectric layer. Sidewalls of the via and at least a portion of the first side of the substrate and the second side of the substrate—the sidewalls of the via are defined by a portion of the substrate extending from the first side to the second side; Forming a first electrode layer lying on the first side extending outwardly from the sidewalls, Forming a dielectric layer overlying at least a first portion of the first electrode layer, the first portion of the first electrode layer being within the sidewalls, wherein a portion of the via is not filled; and Forming a second electrode comprising forming a conductive material in the portion of the via not filled by the dielectric layer Including, The second electrode completely fills the via such that an external contact to the second electrode is external to the via in the layer on the substrate adjacent to the first surface and is connected to an electronic component, And the first electrode, the second electrode and the dielectric layer are formed as self-aligned coaxial capacitors having a substantially cylindrical structure. Sidewalls of the via and at least a portion of the first side of the substrate and the second side of the substrate—the sidewalls of the via are defined by a portion of the substrate extending from the first side to the second side; Forming a first electrode layer lying on the first side and the second side extending outwardly from the sidewalls, Forming a dielectric layer overlying at least a first portion of the first electrode layer, the first portion of the first electrode layer being within the sidewalls, wherein a portion of the via is not filled; and Forming a second electrode overlying the dielectric layer Including, The second electrode completely fills the via such that an external contact to the second electrode is external to the via in the layer on the substrate adjacent to the first surface and is connected to an electronic component, And the first electrode, the second electrode and the dielectric layer are configured as self-aligned coaxial capacitors having a substantially cylindrical structure. Sidewalls of a via, at least a portion of a first side of the substrate and a second side of the substrate—the sidewalls of the via are defined by a portion of the substrate extending from the first side to the second side, Forming a first electrode layer, the first surface extending outwardly from the sidewalls, the second surface extending inwardly from the sidewalls, Forming a dielectric layer overlying at least a first portion of the first electrode layer, the first portion of the first electrode layer being within the sidewalls, wherein a portion of the via is not filled; and Forming a second electrode comprising forming a conductive material in the portion of the via not filled by the dielectric layer Including, The second electrode completely fills the via such that an external contact to the second electrode is external to the via in the layer on the substrate adjacent to the first surface and is connected to an electronic component, And the first electrode, the second electrode and the dielectric layer are formed as self-aligned coaxial capacitors having a substantially cylindrical structure. The method of claim 22, Forming a first contact connected to the first electrode, and Forming a second contact connected to the second electrode Capacitor forming method further comprising. Sidewalls of a via and at least a portion of a first side of the substrate, wherein the sidewalls of the via are defined by a portion of the substrate extending from the first side to the second side of the substrate, the first side being the sidewall Extending outwards from the field to form a first metal seed layer overlying, Electrolytically plating a second metal layer on the first metal seed layer to form a first electrode, Depositing a third metal layer overlying at least a first portion of the first electrode, the first portion of the first electrode being in the sidewalls, wherein a portion of the via is not filled; Anodizing the third metal layer to form a dielectric layer; Forming a second electrode by completely filling the portion of the via not filled by the third metal layer with a conductive paste, and Removing the excess conductive paste to separate the second electrode from the first electrode Including, The second electrode is formed such that an external contact to the second electrode is external to the via in a layer on the substrate adjacent to the first surface and connected to an electronic component. And the first electrode, the second electrode and the dielectric layer are formed as self-aligned coaxial capacitors having a substantially cylindrical structure. The method of claim 24, Wherein the first metal seed layer and the first electrode are further placed on at least a portion of the second side of the substrate. The method of claim 25, And the second side of the substrate extends outwardly from the sidewalls. Sidewalls of a via and at least a portion of a first side of the substrate, wherein the sidewalls of the via are defined by a portion of the substrate extending from the first side to the second side of the substrate, the first side being the sidewall Extending outwards from the grass-forming a copper seed layer overlying, Electrolytically plating a copper layer on the copper seed layer to form a first electrode, Depositing a tantalum layer overlying at least a first portion of the first electrode, the first portion of the first electrode being within the sidewalls, wherein a portion of the via is not filled; Anodizing the tantalum layer to form a tantalum oxide dielectric layer, Forming a second electrode by completely filling the portion of the via not filled by the tantalum layer with a conductive paste, and Removing the excess conductive paste to separate the second electrode from the first electrode Including, The second electrode is formed such that an external contact to the second electrode is external to the via in a layer on the substrate adjacent to the first surface and connected to an electronic component. And the first electrode, the second electrode and the dielectric layer are configured as self-aligned coaxial capacitors having a substantially cylindrical structure. A plurality of self-aligned coaxial capacitors formed to completely fill one of the plurality of vias of the substrate supporting the electronic device, having a substantially cylindrical structure, and having a one-to-one relationship with the plurality of vias; connecting a first electrode for each of the coaxial capacitors to a first potential, and Connecting a second electrode for each of the plurality of capacitors, the second electrode disposed in the first electrode in each via, separated from the first electrode by a dielectric layer, to a second potential Method of operating an electronic device comprising a. A first potential source, A second potential source, and At least one capacitor, The capacitor, A via extending from the first side of the substrate, the first side extending outwardly from the sidewalls, to the second side of the substrate, having sidewalls defined by the substrate, A first electrode lying on at least a portion of the sidewalls of the via and the first surface of the substrate A dielectric layer overlying at least a first portion of the first electrode, the first portion of the first electrode being in the sidewalls, the remaining portion of the via not filled; A second electrode formed in the remaining portion of the via-the second electrode completely fills the via so that an external contact to the second electrode is outside the via, the first electrode, the second electrode and The dielectric layer is configured as a self-aligned coaxial capacitor having a substantially cylindrical structure; A first contact connected to the first electrode and the first potential source, and A second contact on the substrate having a portion adjacent the first surface and another portion connected to the second electrode on the second electrode, the second contact being connected to the second potential source An electronic device comprising a. A first potential source, A second potential source, and At least one capacitor, The capacitor, A via extending from the first side of the substrate, the first side extending outwardly from the sidewalls, to the second side of the substrate, having sidewalls defined by the substrate, A first electrode lying on at least a portion of the sidewalls of the via and the first and second surfaces of the substrate, A dielectric layer lying on at least a first portion of the first electrode, the first portion of the first electrode being in the sidewalls, wherein the formation of the dielectric layer is such that a portion of the via is removed without subsequent removal of the portion of the dielectric layer. Do not fill-, A second electrode formed in said portion of said via not filled by said dielectric layer-said second electrode completely fills said via so that an external contact to said second electrode is outside said via, said first electrode Wherein the second electrode and the dielectric layer are configured as self-aligned coaxial capacitors having a substantially cylindrical structure. A first contact connected to the first electrode and the first potential source, and A second contact on the substrate having a portion adjacent the first surface and another portion connected to the second electrode on the second electrode, the second contact being connected to the second potential source An electronic device comprising a.