KR100403197B1 - 반도체 소자의 금속 배선 형성 방법 - Google Patents
반도체 소자의 금속 배선 형성 방법 Download PDFInfo
- Publication number
- KR100403197B1 KR100403197B1 KR10-2001-0035572A KR20010035572A KR100403197B1 KR 100403197 B1 KR100403197 B1 KR 100403197B1 KR 20010035572 A KR20010035572 A KR 20010035572A KR 100403197 B1 KR100403197 B1 KR 100403197B1
- Authority
- KR
- South Korea
- Prior art keywords
- metal
- forming
- layer
- dual damascene
- mechanical polishing
- Prior art date
Links
- 239000002184 metal Substances 0.000 title claims abstract description 77
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 77
- 238000000034 method Methods 0.000 title claims abstract description 42
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000005498 polishing Methods 0.000 claims abstract description 29
- 230000009977 dual effect Effects 0.000 claims abstract description 26
- 239000000126 substance Substances 0.000 claims abstract description 25
- 238000007747 plating Methods 0.000 claims abstract description 22
- 239000010410 layer Substances 0.000 claims description 70
- 238000009792 diffusion process Methods 0.000 claims description 18
- 230000004888 barrier function Effects 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 10
- 239000011229 interlayer Substances 0.000 claims description 9
- 238000009713 electroplating Methods 0.000 claims description 8
- 230000001590 oxidative effect Effects 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 230000003628 erosive effect Effects 0.000 abstract description 8
- 238000007517 polishing process Methods 0.000 abstract description 4
- 238000006748 scratching Methods 0.000 abstract description 4
- 230000002393 scratching effect Effects 0.000 abstract description 4
- 239000007769 metal material Substances 0.000 abstract 1
- 239000002002 slurry Substances 0.000 description 6
- 239000007800 oxidant agent Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 229910021645 metal ion Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (7)
- 층간 절연막에 듀얼 다마신 패턴이 형성된 반도체 기판이 제공되는 제 1 단계;상기 듀얼 다마신 패턴을 포함한 상기 층간 절연막 상에 확산 방지막을 형성하는 제 2 단계;전체 상부에 금속 시드층을 형성하는 제3 단계;산화재만을 이용한 화학적 기계적 연마로 상기 층간 절연막 상의 금속 시드층을 제거하여 상기 듀얼 다마신 패턴의 측벽 및 저면에만 상기 금속 시드층을 형성하는 제4 단계;상기 층간 절연막의 상부 표면에 상기 확산 방지막이 잔류된 상태에서 전기 도금법으로 상기 듀얼 다마신 패턴 내부에 금속 도금층을 형성하는 제 5 단계 및산화재만을 이용한 화학적 기계적 연마로 층간 절연막 상부의 금속 도금층 및 확산 방지막을 제거하는 제 6 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.
- 제 1 항에 있어서,상기 확산 방지막은 Ta 또는 TaN으로 형성하며, 500Å이하의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.
- 제 1 항에 있어서,상기 금속 시드층은 구리를 이용하여 약 2000Å의 두께로 형성하며, CVD법으로 증착하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.
- 삭제
- 제 1 항에 있어서,상기 금속 도금층은 전기 도금법으로 구리를 도금하여 형성하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.
- 삭제
- 제 1 항에 있어서,상기 산화재로는 H2O2또는 NH4OH을 사용하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2001-0035572A KR100403197B1 (ko) | 2001-06-21 | 2001-06-21 | 반도체 소자의 금속 배선 형성 방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2001-0035572A KR100403197B1 (ko) | 2001-06-21 | 2001-06-21 | 반도체 소자의 금속 배선 형성 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20020096748A KR20020096748A (ko) | 2002-12-31 |
KR100403197B1 true KR100403197B1 (ko) | 2003-10-23 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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KR10-2001-0035572A KR100403197B1 (ko) | 2001-06-21 | 2001-06-21 | 반도체 소자의 금속 배선 형성 방법 |
Country Status (1)
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KR (1) | KR100403197B1 (ko) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100642908B1 (ko) * | 2004-07-12 | 2006-11-03 | 주식회사 하이닉스반도체 | 반도체 소자의 금속 배선 형성 방법 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR19990015599A (ko) * | 1997-08-07 | 1999-03-05 | 윤종용 | 무전해 도금을 이용한 반도체장치의 듀얼 다마슨금속 배선층 형성방법 |
EP0930647A1 (en) * | 1998-01-20 | 1999-07-21 | International Business Machines Corporation | Method to selectively fill recesses with conductive metal |
KR20000043063A (ko) * | 1998-12-28 | 2000-07-15 | 김영환 | 반도체 소자의 금속 배선 형성 방법 |
JP2000323568A (ja) * | 1999-05-11 | 2000-11-24 | Hitachi Ltd | 半導体装置およびその製造方法 |
KR20010004719A (ko) * | 1999-06-29 | 2001-01-15 | 김영환 | 반도체 소자의 금속 배선 형성 방법 |
KR20010009036A (ko) * | 1999-07-07 | 2001-02-05 | 김영환 | 반도체장치의 배선 및 그 연결부 형성방법 |
KR20020006362A (ko) * | 2000-07-12 | 2002-01-19 | 윤종용 | 반도체 소자의 구리 배선층 형성 방법 |
-
2001
- 2001-06-21 KR KR10-2001-0035572A patent/KR100403197B1/ko active IP Right Grant
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR19990015599A (ko) * | 1997-08-07 | 1999-03-05 | 윤종용 | 무전해 도금을 이용한 반도체장치의 듀얼 다마슨금속 배선층 형성방법 |
EP0930647A1 (en) * | 1998-01-20 | 1999-07-21 | International Business Machines Corporation | Method to selectively fill recesses with conductive metal |
KR20000043063A (ko) * | 1998-12-28 | 2000-07-15 | 김영환 | 반도체 소자의 금속 배선 형성 방법 |
JP2000323568A (ja) * | 1999-05-11 | 2000-11-24 | Hitachi Ltd | 半導体装置およびその製造方法 |
KR20010004719A (ko) * | 1999-06-29 | 2001-01-15 | 김영환 | 반도체 소자의 금속 배선 형성 방법 |
KR20010009036A (ko) * | 1999-07-07 | 2001-02-05 | 김영환 | 반도체장치의 배선 및 그 연결부 형성방법 |
KR20020006362A (ko) * | 2000-07-12 | 2002-01-19 | 윤종용 | 반도체 소자의 구리 배선층 형성 방법 |
Also Published As
Publication number | Publication date |
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KR20020096748A (ko) | 2002-12-31 |
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