KR100386637B1 - semiconductor package and method for fabricating thereof - Google Patents
semiconductor package and method for fabricating thereof Download PDFInfo
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- KR100386637B1 KR100386637B1 KR10-1999-0067458A KR19990067458A KR100386637B1 KR 100386637 B1 KR100386637 B1 KR 100386637B1 KR 19990067458 A KR19990067458 A KR 19990067458A KR 100386637 B1 KR100386637 B1 KR 100386637B1
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- Prior art keywords
- fluid
- semiconductor chip
- circuit board
- package
- semiconductor
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 49
- 238000000034 method Methods 0.000 title claims description 17
- 239000012530 fluid Substances 0.000 claims abstract description 45
- 229910000679 solder Inorganic materials 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 abstract description 8
- 230000008054 signal transmission Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 9
- 239000002245 particle Substances 0.000 description 8
- 230000008569 process Effects 0.000 description 7
- 239000000758 substrate Substances 0.000 description 6
- 239000004020 conductor Substances 0.000 description 4
- 239000004033 plastic Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- 238000000518 rheometry Methods 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229910015365 Au—Si Inorganic materials 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
본 발명은 신호 전달이 빠르고 전기적 특성이 매우 우수한 경박단소화된 새로운 타입의 반도체 패키지를 제공하는데 그 목적이 있다.It is an object of the present invention to provide a new type of thin and short semiconductor package with fast signal transmission and excellent electrical characteristics.
이를 위해, 본 발명은 본딩패드(500)를 구비한 반도체 칩(5)과, 상기 반도체 칩(5)과 이격됨과 더불어 상기 반도체 칩(5)의 본딩패드(500)와 대향하는 위치에 콘택패드(400)가 위치하는 회로기판(4)과, 상기 반도체 칩(5)과 회로기판(4) 사이에 구비되는 전기유변유체(2)와, 상기 전기유변유체(2)를 수용하는 유체수용체(7)를 포함하여서 됨을 특징으로 하는 반도체 패키지 및 그 제조방법이 제공된다.To this end, the present invention is a semiconductor chip (5) having a bonding pad 500, and a contact pad in a position facing the bonding pad 500 of the semiconductor chip 5, while being spaced apart from the semiconductor chip (5) A circuit board 4 on which the 400 is located, an electrofluidic fluid 2 provided between the semiconductor chip 5 and the circuit board 4, and a fluid receptor containing the electrofluidic fluid 2; There is provided a semiconductor package and a method of manufacturing the same.
Description
본 발명은 반도체 패키지에 관한 것으로서, 더욱 상세하게는 전기유변유체(ER fluid; Electro Rheological fluid)를 이용하여 도전을 행하는 새로운 형태의 반도체 패키지에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly, to a new type of semiconductor package which conducts a challenge by using an Electro Rheological Fluid (ER fluid).
일반적으로, 반도체 산업에서 집적회로에 대한 패키징 기술은 소형화에 대한 요구 및 실장 신뢰성을 만족시키기 위해 지금까지 계속 발전해오고 있다.In general, the packaging technology for integrated circuits in the semiconductor industry continues to evolve to meet the demand for miniaturization and mounting reliability.
즉, 소형화에 대한 요구는 칩 스케일에 근접한 패키지에 대한 개발을 가속화시키고 있으며, 실장 신뢰성에 대한 요구는 실장작업의 효율성 및 실장후의 기계적·전기적 신뢰성을 향상시킬 수 있는 패키지 제조 기술에 대한 중요성을 부각시키고 있다.In other words, the demand for miniaturization is accelerating the development of packages close to the chip scale, and the demand for mounting reliability emphasizes the importance of package manufacturing technology that can improve the efficiency of mounting work and the mechanical and electrical reliability after mounting. I'm making it.
한편, 일반적으로 반도체소자는 집적회로가 형성된 웨이퍼 상태에서 낱개의 칩으로 각각 분리된 후, 이것을 플라스틱 패키지나 세라믹 패키지에 탑재하여 기판에의 실장이 용이하도록 조립하는 공정을 거치게 된다.On the other hand, in general, semiconductor devices are separated into individual chips in a wafer in which integrated circuits are formed, and then mounted on a plastic package or a ceramic package, and then assembled to facilitate mounting on a substrate.
이와 같은, 반도체소자에 대한 조립공정의 주목적은 기판이나 소켓에 실장하기 위한 형상의 확보와 기능보호에 있다고 할 수 있다.The main purpose of the assembling process for a semiconductor element is to secure the shape and protect the function for mounting on a substrate or a socket.
또한, 최근에는 집적회로의 고집적화에 따라 다핀화, 미세조립기술, 또 실장형태의 다양화에 따른 패키지의 다종류화 등, 조립공정과 관련된 기술도 각각 세분된 분야에 따라 크게 변화하고 있다.In addition, in recent years, technologies related to the assembly process, such as multi-pinning, micro-assembly technology, and package variety due to the diversification of the mounting type according to the high integration of integrated circuits, are also greatly changed according to the subdivided fields.
반도체 조립공정의 개요에 대해 현재 가장 많이 사용되고 있는 플라스틱 타입의 반도체소자를 예로 들어 설명하면 다음과 같다.An overview of the semiconductor assembly process will be described below with an example of a plastic type semiconductor device which is most used.
먼저, 전기적 회로가 형성된 웨이퍼를 각각의 단일칩으로 분리하는데, 이때 Si(실리콘)는 모스경도 7로서 딱딱하고 깨지기 쉬운 성질을 갖고 있으므로 웨이퍼의 제조시 미리 분리할 라인에 절단하기 위한 물질을 넣어두고 이 분리라인을 따라 브레이크 응력을 가해 파괴, 분리시키는 방법을 취하는 경우가 많다.First, the wafer on which the electrical circuit is formed is separated into each single chip. In this case, Si (silicon) has a Mohs hardness of 7 and is hard and brittle, so that a material for cutting is placed in a line to be separated in advance in manufacturing the wafer In many cases, a break stress is applied along this separation line to break and separate.
또한, 분리된 각각의 반도체 칩은 리드프레임의 다이패드에 본딩되고, 이때의 접합방법은 Au-Si 공정(共晶)법, 납땜법, 수지접착법 등이 있으며 용도에 따라 알맞은 방법이 선택되어 사용된다.In addition, each separated semiconductor chip is bonded to the die pad of the lead frame, and the bonding method is Au-Si process, soldering method, resin bonding method, etc. Used.
한편, 전술한 바와같이 반도체 칩을 리드프레임의 다이패드에 접착하는 목적은 조립이 완료된 후 기판에 실장시키기 위해서 뿐만 아니라, 전기적 입출력단자나 어스(earth)를 겸하는 일도 있으며 소자의 동작시 발생하는 열의 방열통로서도 필요로하는 경우가 있기 때문이다.On the other hand, as described above, the purpose of bonding the semiconductor chip to the die pad of the lead frame is not only to be mounted on the substrate after assembly is completed, but also to serve as an electrical input / output terminal or earth, This is because it may be required also as a heat dissipation tube.
상기와 같이 반도체 칩을 본딩한 후에는 칩과 리드프레임의 인너리드를 와이어로 본딩하므로써 연결하게 되며, 와이어 본딩의 방법으로 플라스틱 봉함 패키지에서는 일반적으로 골드와이어를 사용한 열압착법 또는 열압착법과 초음파법을 혼용한 방법이 주로 이용되고 있다.After bonding the semiconductor chip as described above, the inner lead of the chip and the lead frame are connected by wire bonding. In the plastic sealing package, the thermal bonding method or the thermocompression method and the ultrasonic method are generally used in the plastic sealing package. The mixed method is mainly used.
또한, 와이어 본딩에 의해 칩과 인너리드가 전기적으로 연결된 후에는 칩을 고순도의 에폭시 수지를 사용하여 성형 봉합하므로써 몰드바디를 형성시키는 몰딩공정이 수행되는데, 이때 사용되는 에폭시 수지는 집적회로의 신뢰성을 좌우하는 중요한 요소이며, 수지의 고순도화와 몰딩시 집적회로에 주어지는 응력을 저감시키기 위한 저응력화 등의 개선이 추진되고 있다.In addition, after the chip and the inner lead are electrically connected by wire bonding, a molding process of forming a mold body by forming and sealing the chip using a high purity epoxy resin is performed. It is an important factor to influence, and improvements such as high purity of the resin and low stress to reduce the stress applied to the integrated circuit during molding are being promoted.
그리고, 상기한 공정이 완료된 후에는 IC 패키지를 소켓이나 기판에 실장하기 위해 아웃터리드(outer lead)를 소정의 형상으로 절단하고 성형하는 공정이 행해지며, 아웃터리드에는 실장접합성(납땜성)을 향상시키기 위해 도금이나 납딥(dip)이 처리된다.After the above process is completed, a process of cutting and molding an outer lead into a predetermined shape is carried out to mount the IC package on a socket or a substrate, and the mount is improved in solderability. Plating or dip dips are applied to make them.
한편, 반도체 패키지는 실장형태 및 리드형태에 따라 여러 가지 유형으로 나뉘는데, 패키지의 대표적인 예로는 전술한 DIP(Dual Inline Package)외에 QFP(Quad Flat Package), TSOP(Thin Small Outline Package), BGA 패키지( Ball Grid Array package) 등이 있으며, 계속 다핀(多-pin)화 또는 경박단소(輕薄短小)화 되고 있다.On the other hand, semiconductor packages are divided into various types according to the mounting type and the lead type. Representative examples of the package include QF (Quad Flat Package), TSOP (Thin Small Outline Package), BGA package ( Ball Grid Array package, etc., and continues to be multi-pin or light and thin.
상기한 패키지 타입중, BGA 패키지(Ball Grid Array package)는 반도체 칩이 부착된 기판의 이면에 구형의 솔더볼을 소정의 상태로 배열(Array)하여 아우터 리드(outer lead) 대신으로 사용하게 되며, 상기 BGA 패키지는 패키지 몸체(Package Body) 면적을 QFP(Quad Flat Package) 타입보다 작게 할 수 있으며, QFP와는 달리 리드의 변형이 없는 장점이 있다.Among the above package types, a BGA package (Ball Grid Array package) is used to replace the outer lead by arranging a spherical solder ball in a predetermined state on the back surface of the substrate on which the semiconductor chip is attached. The BGA package can make the package body area smaller than the QFP (Quad Flat Package) type, and unlike QFP, there is an advantage that there is no deformation of the lead.
한편, 이와 같은 패키지들은 실장면적, 입출력 단자수, 전기적 신뢰성, 제조공정의 유연성, 제조비용등에 있어 제각기 장점 및 단점을 갖고 있으며, 이들의 장점을 살리면서 단점을 해소하기 위해 새로운 타입의 반도체 패키지가 계속적으로 연구 개발되고 있는 실정이다.On the other hand, these packages have advantages and disadvantages in terms of mounting area, number of input / output terminals, electrical reliability, manufacturing process flexibility, and manufacturing cost, and new types of semiconductor packages have been developed to solve these disadvantages. The situation is continuously being researched and developed.
본 발명은 상기한 제반 문제점을 해결하기 위한 것으로서, 전기유변유체를이용하여 신호 전달이 빠르고 전기적 특성이 매우 우수한 경박단소화된 새로운 타입의 반도체 패키지를 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and an object thereof is to provide a new type of light-weight and short-sized semiconductor package, which is fast in signal transmission and excellent in electrical characteristics by using an electric rheological fluid.
도 1a 및 도 1b는 전기유변유체의 작동 원리를 설명한 개념도로서,1a and 1b is a conceptual diagram illustrating the operating principle of the electro-fluidic fluid,
도 1a는 전원이 인가되기 전 상태도1A is a state diagram before power is applied
도 1b는 전원이 인가된 후의 상태도1B is a state diagram after power is applied
도 2a 및 도 2b는 본 발명의 반도체 패키지 구조 및 작동 원리를 나타낸 종단면도로서,2A and 2B are longitudinal cross-sectional views illustrating a semiconductor package structure and an operating principle of the present invention.
도 2a는 전원이 인가되기 전 상태도2A is a state diagram before power is applied
도 2b는 전원이 인가된 후의 상태도2B is a state diagram after power is applied
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
1:도전체 2:전기유변유체1: Conductor 2: Electric rheological fluid
3:전도성입자 4:회로기판3: conductive particle 4: circuit board
400:콘택패드 5:반도체소자400: contact pad 5: semiconductor element
500:본딩패드 6:솔더볼500: bonding pad 6: solder ball
7:유체수용체 8:마더보드7: fluid receptor 8: motherboard
상기한 목적을 달성하기 위해, 본 발명은 본딩패드를 구비한 반도체 칩과, 상기 반도체 칩과 이격됨과 더불어 상기 반도체 칩의 본딩패드와 대향하는 위치에 콘택패드가 위치하는 회로기판과, 상기 반도체 칩과 회로기판 사이에 구비되는 전기유변유체와, 상기 전기유변유체를 수용하는 유체수용체를 포함하여서 됨을 특징으로 하는 반도체 패키지가 제공된다.In order to achieve the above object, the present invention provides a semiconductor chip having a bonding pad, a circuit board spaced apart from the semiconductor chip and a contact pad positioned at a position facing the bonding pad of the semiconductor chip, and the semiconductor chip. A semiconductor package is provided, comprising an electrical rheology fluid provided between the circuit board and a fluid receiving body containing the electrical rheology fluid.
한편, 상기한 목적을 달성하기 위해, 본 발명은 콘택패드가 구비된 회로기판 상에 유체수용체를 부착하는 단계와, 상기 유체수용체 내에 전기유변유체를 주입하는 단계와, 상기 유체수용체 상부에 상기 회로기판상의 콘택패드와 대향하도록 반도체 칩을 부착하는 단계와, 상기 회로기판 하부에 솔더볼을 부착하는 단계;를 포함하여서 됨을 특징으로 하는 반도체 패키지 제조방법이 제공된다.On the other hand, in order to achieve the above object, the present invention comprises the steps of attaching a fluid receptor on the circuit board with a contact pad, injecting an electrofluidic fluid into the fluid receptor, and the circuit on the fluid receptor And attaching a semiconductor chip so as to face a contact pad on a substrate, and attaching a solder ball to the lower portion of the circuit board.
이하, 본 발명의 일실시예를 첨부도면 도 1a 내지 도 2b를 참조하여 상세히 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 1A to 2B.
도 1a 및 도 1b는 전기유변유체의 작동 원리를 설명한 개념도로서, 도 1a는 전원이 인가되기 전 상태도이고, 도 1b는 전원이 인가된 후의 상태도로서, 먼저, 본 발명의 패키지에 적용되는 전기유변유체의 개념 및 동작원리를 설명하면 다음과 같다.1A and 1B are conceptual views illustrating the operating principle of the electrofluidic fluid. FIG. 1A is a state diagram before power is applied, and FIG. 1B is a state diagram after power is applied. First, an electric rheology applied to a package of the present invention. The concept and principle of operation of the fluid are as follows.
전기유변유체(2)는 유체안에 전도성을 가지는 수십 ㎛ 내지 수㎚의 작은 입자(입자는 ＋, －의 극성을 가지고 있음)를 넣은 것으로서, 양쪽의 도전체(1)에 전기를 공급하게 될 경우, 전기유변유체(2)의 전기적인 특성에 의해 전도성 입자(3)는 일렬로 늘어서게 되어 전기가 통하는 통로 역할을 수행하게 된다.The electrorheological fluid 2 is a small particle of several tens of micrometers to several nm (the particle has a polarity of + and-) having conductivity in the fluid. When the electric fluid is supplied to both conductors 1, By the electrical properties of the electrofluidic fluid 2, the conductive particles 3 are lined up to serve as a passage through which electricity flows.
즉, 전기유변유체(2)는 전압이나 전류가 가해짐에 따라 비콜로이드 용액상태에서 교질(膠質; gel)상태로 변화하게 되며, 이 때 전도성 입자(3)는 가장 가까운 도전체(1)를 향해서 체인구조로 이어지게 되며, 가해지는 전압이나 전류가 커질수록 전도성 입자(3) 상호간의 결합력이 커지게 된다.That is, the electrofluidic fluid 2 changes from a non-colloidal solution state to a colloidal state as voltage or current is applied, and at this time, the conductive particles 3 form the closest conductor 1. Towards the chain structure, and as the voltage or current applied increases, the bonding force between the conductive particles 3 increases.
한편, 도 2a 및 도 2b는 본 발명의 반도체 패키지 구조 및 작동 원리를 나타낸 종단면도로서, 도 2a는 전원이 인가되기 전 상태도이고, 도 2b는 전원이 인가된 후의 상태도이다.2A and 2B are longitudinal cross-sectional views illustrating a semiconductor package structure and an operating principle of the present invention. FIG. 2A is a state diagram before power is applied, and FIG. 2B is a state diagram after power is applied.
본 발명은 본딩패드(500)를 구비한 반도체 칩(5)과, 상기 반도체 칩(5)과 이격되어 위치하고 상기 반도체 칩(5)의 본딩패드(500)와 대향하는 위치에 콘택패드(400)가 위치하며 내부에 회로패턴이 형성된 회로기판(4)과, 상기 반도체 칩(5)과 회로기판(4) 사이에 구비되는 전기유변유체(2)를 포함하여 구성된다.The present invention provides a semiconductor chip 5 including a bonding pad 500 and a contact pad 400 at a position spaced apart from the semiconductor chip 5 and opposite to the bonding pad 500 of the semiconductor chip 5. And a circuit board 4 having a circuit pattern formed therein and an electric rheological fluid 2 provided between the semiconductor chip 5 and the circuit board 4.
이 때, 전기유변유체(2)는 전원이 인가되기 전에는 액체 상태이므로 도 2a 및 도 2b에 나타낸 바와 같은 유체수용체(7)를 구성하여 패키지 제조 과정에서의 유체의 누설을 방지한다.At this time, since the electrofluidic fluid 2 is in a liquid state before the power is applied, the fluid receiving fluid 7 is formed as shown in FIGS. 2A and 2B to prevent leakage of the fluid in the package manufacturing process.
한편, 상기 회로기판(4) 하부에는 외부전원 접속을 위한 솔더볼(6)이 부착되며, 본 실시예에서는 솔더볼(6)을 부착한 것을 예로 들었으나, 솔더볼이 아닌 범프를 형성하여도 무방하다.On the other hand, the solder ball 6 for attaching the external power supply is attached to the lower portion of the circuit board 4, in this embodiment, the solder ball 6 is attached to the example, but may be formed bumps other than the solder ball.
이와 같이 구성된 본 발명의 전기유변유체(2)를 이용한 반도체 패키지의 제조 과정은 다음과 같다.The manufacturing process of the semiconductor package using the electrorheological fluid 2 of the present invention configured as described above is as follows.
먼저, 회로기판(4) 상면에 유체수용체(7)를 부착시킨 후, 상기 유체수용체(7) 상부의 개구공(700)을 통해 유체수용체(7) 내부에 전기유변유체(2)를 주입한다.First, after attaching the fluid receptor 7 to the upper surface of the circuit board 4, the electro-fluidic fluid 2 is injected into the fluid receptor 7 through the opening hole 700 above the fluid receptor 7. .
이와 같이 된 상태에서, 유체수용체(7) 상부에 반도체 칩(5)을 부착한다.In this state, the semiconductor chip 5 is attached to the upper portion of the fluid receptor 7.
이 때, 상기 반도체 칩(5)의 본딩패드(500)는 유체수용체(7)의 개구공(700)과 일치하게 되며, 이와 더불어 회로기판(4)의 콘택패드(400)와 일정 간격 이격된 상태로 대향하게 된다.At this time, the bonding pad 500 of the semiconductor chip 5 is coincided with the opening hole 700 of the fluid receptor 7, and is spaced apart from the contact pad 400 of the circuit board 4 by a predetermined distance. The state is opposed.
그리고, 상기와 같이 하여 회로기판(4)과 유체수용체(7)와 반도체 칩(5)의 조립이 완료된 후에는 회로기판(4) 저면에 솔더볼(6)을 부착하여 패키지의 제작을 완료하게 된다.After the assembly of the circuit board 4, the fluid receptor 7, and the semiconductor chip 5 is completed as described above, the solder balls 6 are attached to the bottom surface of the circuit board 4 to complete the manufacture of the package. .
한편, 이와 같이 제조된 반도체 패키지의 작용은 다음과 같다.On the other hand, the action of the semiconductor package thus produced is as follows.
마더보드(8)에 반도체 패키지를 실장한 상태에서, 마더보드(8)에 전원을 인가하면 전기유변유체(2) 내의 전도성 입자(3)들이 체인 구조로 변하면서 전기적 통로를 이루게 된다.When the semiconductor package is mounted on the motherboard 8, when power is applied to the motherboard 8, the conductive particles 3 in the electrofluidic fluid 2 change into a chain structure, thereby forming an electrical passage.
즉, 전도성 입자(3)들이 회로기판(4)의 콘택패드(400)와 반도체 칩(5)의 본딩패드(500) 사이를 연결하는 도전체 고리를 이루게 되므로써, 반도체소자로의 전원 공급이 가능해지게 된다.That is, since the conductive particles 3 form a conductor ring connecting the contact pad 400 of the circuit board 4 and the bonding pad 500 of the semiconductor chip 5, power supply to the semiconductor device is possible. You lose.
이상에서와 같이, 본 발명은 전기유변유체를 이용한 반도체 패키지로서, 본 발명의 반도체 패키지는 와이어나 솔더 범프등의 등의 외부접속단자와의 연결부재가 별도로 필요없다.As described above, the present invention is a semiconductor package using an electro-fluidic fluid, and the semiconductor package of the present invention does not need a connection member with an external connection terminal such as a wire or a solder bump.
따라서, 본 발명의 패키지는 와이어를 이용하여 외부접속단자와 연결하던 기존의 패키지와는 달리 와이어 쇼트 및 손상을 방지할 수 있고, 솔더 범프를 이용한 기존의 패키지와는 달리 작업성이 향상되어, 패키지의 신뢰성 및 생산성을 높일 수 있게 된다.Therefore, the package of the present invention can prevent the short and damage of the wire, unlike the existing package that is connected to the external connection terminal using a wire, unlike the existing package using the solder bumps, workability is improved, the package It can increase the reliability and productivity.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-1999-0067458A KR100386637B1 (en) | 1999-12-30 | 1999-12-30 | semiconductor package and method for fabricating thereof |
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| KR10-1999-0067458A KR100386637B1 (en) | 1999-12-30 | 1999-12-30 | semiconductor package and method for fabricating thereof |
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| KR100386637B1 true KR100386637B1 (en) | 2003-06-02 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4483788A (en) * | 1982-03-25 | 1984-11-20 | The National Research Development Corp. | Electric field responsive fluids |
| US5886415A (en) * | 1996-01-19 | 1999-03-23 | Shinko Electric Industries, Co., Ltd. | Anisotropic conductive sheet and printed circuit board |
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1999
- 1999-12-30 KR KR10-1999-0067458A patent/KR100386637B1/en active IP Right Grant
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4483788A (en) * | 1982-03-25 | 1984-11-20 | The National Research Development Corp. | Electric field responsive fluids |
| US5886415A (en) * | 1996-01-19 | 1999-03-23 | Shinko Electric Industries, Co., Ltd. | Anisotropic conductive sheet and printed circuit board |
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| KR20010059920A (en) | 2001-07-06 |
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