KR100367403B1 - Method for forming contact of a semiconductor device - Google Patents

Method for forming contact of a semiconductor device Download PDF

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Publication number
KR100367403B1
KR100367403B1 KR10-1999-0025047A KR19990025047A KR100367403B1 KR 100367403 B1 KR100367403 B1 KR 100367403B1 KR 19990025047 A KR19990025047 A KR 19990025047A KR 100367403 B1 KR100367403 B1 KR 100367403B1
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South Korea
Prior art keywords
forming
contact
word line
semiconductor device
contact hole
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KR10-1999-0025047A
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Korean (ko)
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KR20010004415A (en
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이주영
이광표
곽흥식
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체소자의 콘택 형성방법에 관한 것으로, 제 1폴리와 제 1텅스텐 실리사이드가 적층된 폴리사이드 구조의 워드라인을 형성하고 상기 워드라인 상측을 평탄화시키는 층간절연막을 형성한 다음, 상기 층간절연막을 통하여 상기 워드라인의 상기 제 1텅스텐 실리사이드를 노출시키는 콘택홀을 형성하고 상기 콘택홀을 통하여 상기 워드라인에 접속되는 제 2폴리와 제 2텅스텐 실리사이드 적층구조의 폴리사이드로 비트라인을 형성하는 반도체소자의 콘택 형성방법으로서, 상기 콘택홀을 형성하고 콘택홀의 표면을 NH4OH : H2O2: 순수 = X : Y : Z 의 특정 SC-1 용액으로 세정하여 콘택저항을 감소시키고 그에 따른 소자의 구동전압을 감소시키며 소자의 신호 이송속도를 증가시킬 수 있어 반도체소자의 동작 특성을 향상시킬 수 있는 기술이다.The present invention relates to a method for forming a contact of a semiconductor device, comprising: forming a word line having a polyside structure in which a first poly and a first tungsten silicide are stacked, and forming an interlayer insulating film to planarize an upper side of the word line; A semiconductor forming a contact hole exposing the first tungsten silicide of the word line through and forming a bit line with a polyside of a second poly and second tungsten silicide stacked structure connected to the word line through the contact hole A method for forming a contact of a device, the contact hole is formed and the surface of the contact hole is cleaned with a specific SC-1 solution of NH 4 OH: H 2 O 2 : pure water = X: Y: Z to reduce the contact resistance and thereby It is a technology that can improve the operating characteristics of semiconductor devices by reducing the driving voltage of the device and increasing the signal transfer speed of the device.

Description

반도체소자의 콘택 형성방법{METHOD FOR FORMING CONTACT OF A SEMICONDUCTOR DEVICE}TECHNICAL FOR FORMING CONTACT OF A SEMICONDUCTOR DEVICE

본 발명은 반도체소자의 콘택 형성방법 형성방법에 관한 것으로서, 보다 상세하게는 도전배선 간의 콘택 형성공정시 콘택 저항을 감소시킬 수 있는 기술에 관한 것이다.The present invention relates to a method for forming a contact forming method of a semiconductor device, and more particularly, to a technology capable of reducing contact resistance during a contact forming process between conductive wirings.

일반적으로 반도체소자의 도전배선인 워드라인이나 비트라인은 다결정실리콘을 이용하여 형성하였다.In general, word lines or bit lines, which are conductive wirings of semiconductor devices, are formed using polysilicon.

그러나, 반도체소자가 고집적화, 고속화됨에 따라 상기 워드라인이나 비트라인의 재료인 다결정실리콘은 높은 저항으로 인하여 고속화를 어렵게 하는 단점이 있다.However, as semiconductor devices are highly integrated and high in speed, polysilicon, which is a material of the word line or bit line, has a disadvantage of high speed due to high resistance.

상기한 단점을 해결하기 위해, 종래기술에서는 반도체소자의 고속화를 가능하게 하기 위하여 상기 워드라인이나 비트라인과 같은 도전배선의 일정두께는 다결정실리콘으로 형성하고 일정두께는 고융점 금속으로 저항이 작은 텅스텐 실리사이드를 형성하여 적층구조, 즉 텅스텐 폴리사이드 구조의 도전배선을 형성하였다.In order to solve the above disadvantages, in the prior art, in order to enable high speed semiconductor devices, a predetermined thickness of the conductive wiring such as the word line or the bit line is formed of polycrystalline silicon, and the predetermined thickness is a high melting point metal, and the resistance is low. The silicide was formed to form a conductive structure of a laminated structure, that is, a tungsten polyside structure.

그러나, 상기와 같은 다결정실리콘과 텅스텐실리사이드의 적층구조로 도전배선을 형성하고 그 상부에 도전배선을 콘택시키는 경우, 상기 텅스텐 실리사이드의 표면이 산화되는 현상이 유발되어 콘택저항을 증가시키고 그에 따른 반도체소자의 특성 및 신뢰성이 저하되는 현상이 유발되었다.However, in the case where the conductive wiring is formed with the multilayer structure of polycrystalline silicon and tungsten silicide as described above, and the conductive wiring is contacted on the upper surface, the surface of the tungsten silicide is oxidized to increase the contact resistance and thereby the semiconductor device. The phenomenon that the characteristics and reliability of the deterioration was caused.

한편, 상기 다결정실리콘과 텅스텐실리사이드의 적층구조인 텅스텐 폴리사이드는, 소자의 고집적화에 따른 신호처리속도를 증가시키기 위하여 기존의 도프드 다결정실리콘을 대체하여 워드라인과 비트라인으로 사용되고 있다.Meanwhile, the tungsten polyside, which is a laminated structure of polysilicon and tungsten silicide, is used as a word line and a bit line to replace the conventional doped polycrystalline silicon in order to increase the signal processing speed due to the high integration of the device.

일반적으로 텅스텐 폴리사이드 비트라인과 워드라인은 캐패시터로의 신호이송을 위해 셀의 주변회로 부위에서 콘택되며, 이때의 콘택저항은 신호이송속도를 좌우하는 주요인자로 고려되고 있다.In general, the tungsten polyside bit line and word line are contacted at the peripheral circuit part of the cell for signal transfer to a capacitor, and the contact resistance at this time is considered as a major factor that determines the signal transfer speed.

따라서, 신호처리시 시간지연(time delay)을 감소시키기 위해 콘택저항을 최대한으로 감소시켜야 한다.Therefore, the contact resistance should be reduced as much as possible in order to reduce time delay in signal processing.

그리하여, 최근의 콘택공정은 워드라인의 텅스텐 실리사이드와 비트라인의 도프드 다결정실리콘이 콘택하여 다음과 같은 문제점을 유발하였다.Therefore, the recent contact process causes the following problems by contacting the tungsten silicide of the word line and the doped polysilicon of the bit line.

먼저, 비트라인을 형성하기 위한 콘택식각공정시 플라즈마 가스와의 반응에 의해 워드라인 텅스텐 실리사이드층 표면에 WO3등의 화합물이 형성되므로 콘택저항이 증가된다.First, a contact resistance is increased because a compound such as WO 3 is formed on the surface of a word line tungsten silicide layer by a reaction with plasma gas during a contact etching process for forming a bit line.

그리고, 상기와 같은 산화물에 의한 콘택저항 증가를 방지하여 콘택 저항을 감소시키기 위해 도프드 다결정실리콘을 텅스텐 실리사이드 상부에 형성함으로써 저항을 낮추는 방법을 사용중이지만 공정 수의 증가 및 고정 시간의 증가로 인해 비용이 크게 늘어나는 단점이 있다.In order to reduce the contact resistance by preventing the increase of the contact resistance caused by the oxide, a method of lowering the resistance by forming doped polycrystalline silicon on the tungsten silicide is used, but the cost is increased due to the increase of the number of processes and the increase of the fixed time. This has a drawback that greatly increases.

본 발명은 상기한 종래기술의 문제점을 해결하기위하여, 도전배선 간의 콘택공정시 유발되는 산화막이나 텅스텐 실리사이드의 손상을 방지할 수 있도록 특정 SC-1 세정을 이용하여 제거하여 콘택저항을 감소시킴으로써 반도체소자의 동작 특성을 향상시킬 수 있는 반도체소자의 콘택 형성방법을 제공하는데 그 목적이 있다.The present invention is to solve the problems of the prior art, the semiconductor device by reducing the contact resistance by removing using a specific SC-1 cleaning to prevent damage to the oxide film or tungsten silicide caused during the contact process between the conductive wiring It is an object of the present invention to provide a method for forming a contact of a semiconductor device capable of improving the operation characteristics of the semiconductor device.

도 1 은 본 발명의 실시예에 따른 반도체소자의 콘택 형성방법을 도시한 단면도이다.1 is a cross-sectional view illustrating a method for forming a contact of a semiconductor device according to an embodiment of the present invention.

- 도면의 주요부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawings-

11 : 반도체기판 13 : 제 1폴리11: semiconductor substrate 13: first poly

15 : 제 1텅스텐 실리사이드 17 : 층간절연막15: first tungsten silicide 17: interlayer insulating film

19 : 콘택홀 21 : 제 2폴리19: contact hole 21: the second poly

23 : 제 2텅스텐 실리사이드23: second tungsten silicide

상기한 목적을 달성하기 위해 본 발명에 따른 반도체소자의 콘택 형성방법 형성방법은, 제 1폴리와 제 1텅스텐 실리사이드가 적층된 폴리사이드 구조의 워드라인을 형성하고 워드라인 상측을 평탄화시키는 층간절연막을 형성한 다음, 층간절연막을 통하여 워드라인의 제 1텅스텐 실리사이드를 노출시키는 콘택홀을 형성하고 콘택홀을 통하여 워드라인에 접속되는 제 2폴리와 제 2텅스텐 실리사이드 적층구조의 폴리사이드로 비트라인을 형성하는 반도체소자의 콘택 형성방법으로서, 콘택홀을 형성하고 콘택홀의 표면을 NH4OH : H2O2: 순수 = X : Y : Z 의 특정 SC-1 용액으로 세정하는 것을 특징으로한다.In order to achieve the above object, a method of forming a contact for a semiconductor device according to the present invention may include forming an interlayer insulating film that forms a word line having a polyside structure in which a first poly and a first tungsten silicide are laminated and planarizes an upper side of the word line. Next, a contact hole exposing the first tungsten silicide of the word line is formed through the interlayer insulating layer, and a bit line is formed of the polyside of the second poly and second tungsten silicide laminated structure connected to the word line through the contact hole. The method for forming a contact of a semiconductor device is characterized in that a contact hole is formed and the surface of the contact hole is washed with a specific SC-1 solution of NH 4 OH: H 2 O 2 : pure water = X: Y: Z.

(단. 상기 X, Y, Z 는 각각 0.5 ∼ 5, 0.5 ∼ 5, 5 ∼ 20 의 부피비임.)(However, the X, Y, Z is a volume ratio of 0.5 to 5, 0.5 to 5, 5 to 20, respectively.)

이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 설명한다. 또한 본 실시예는 본 발명의 권리범위를 한정하는 것은 아니고, 단지 예시로 제시된 것이다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, this embodiment is not intended to limit the scope of the present invention, but is presented by way of example only.

도 1 은 본 발명의 실시예에 따른 반도체소자의 콘택 형성방법 형성방법을 도시한 단면도이다.1 is a cross-sectional view illustrating a method of forming a contact forming method of a semiconductor device according to an embodiment of the present invention.

먼저, 반도체기판(11)상부에 워드라인을 형성한다.First, a word line is formed on the semiconductor substrate 11.

이때, 워드라인은 제 1폴리(13)와 제 1텅스텐 실리사이드(15) 적층구조의 텅스텐 폴리사이드를 형성하고 워드라인 마스크를 이용한 식각공정으로 형성한다.In this case, the word line is formed of a tungsten polyside having a stacked structure of the first poly 13 and the first tungsten silicide 15 and formed by an etching process using a word line mask.

그 다음, 전체표면상부에 층간절연막(17)을 형성한다.Then, an interlayer insulating film 17 is formed over the entire surface.

이때, 층간절연막(17)은 비.피.에스.지.(boro phospho silicate glass, 이하에서 BPSG 라 함)와 같이 유동성이 우수한 절연물질로 형성한다.At this time, the interlayer insulating film 17 is formed of an insulating material having excellent fluidity, such as B.sub.P.G. (Brolet phospho silicate glass, hereinafter referred to as BPSG).

그 다음, 워드라인의 상측에 구비되는 제 1텅스텐 실리사이드(15)을 노출시키는 콘택홀(19)을 형성한다.Next, a contact hole 19 exposing the first tungsten silicide 15 provided above the word line is formed.

이때, 제 1텅스텐 실리사이드(15)가 콘택식각공정에 의하여 식각되어 표면이 손상되고 산화되어 WO3산화막이 형성된다.At this time, the first tungsten silicide 15 is etched by the contact etching process to damage the surface and oxidize to form a WO 3 oxide film.

그리고, 산화막은 콘택홀(19)을 매립하는 콘택공정을 실시하기 전까지 형성될 수 있다.The oxide film may be formed until the contact process of filling the contact hole 19 is performed.

그 다음, 특정 SC-1 세정을 사용하여 WO3산화막을 제거하는 동시에 손상된 제 1텅스텐 실리사이드(15)의 손상된 부분을 식각한다.A specific SC-1 cleaning is then used to remove the WO 3 oxide film and simultaneously etch the damaged portion of the damaged first tungsten silicide 15.

여기서, 특정 SC-1 은 NH4OH : H2O2: 순수 = X : Y : Z 로 하되, 여기서 X, Y, Z 는 각각 0.5 ∼ 5, 0.5 ∼ 5, 5 ∼ 20 의 부피비로 사용한 것이다.Herein, the specific SC-1 is NH 4 OH: H 2 O 2 : pure water = X: Y: Z, where X, Y, and Z are used at a volume ratio of 0.5 to 5, 0.5 to 5, and 5 to 20, respectively. .

그리고, 특정 SC-1 세정공정은 40 ∼ 80 ℃ 온도로 실시한다.And specific SC-1 washing process is performed at 40-80 degreeC temperature.

그리고, 특정 SC-1 세정공정은 wet 스테이션(wet station)에서 실시하되, 세정공정을 피라나(piranha)세정, DHF, RSC-1, DHF 의 순서로 적용한다.The specific SC-1 cleaning process is performed in a wet station, but the cleaning process is applied in the order of piranha cleaning, DHF, RSC-1, and DHF.

이때, DHF 세정공정은 불산계 화학 적용하고, 농도는 HF를 사용하는 경우 H2O : HF = 50∼200 : 1 부피비로 실시한다.또한, 상기 특정 SC-1 세정공정은 피라나세정, BHF, RSC-1, BHF 의 순서로 적용하며, 이때 BHF 세정공정은 NH4F : HF = 100∼300 : 1 부피비 농도의 BOE용액을 사용하여 실시한다.In this case, the DHF cleaning process is applied with hydrofluoric acid, and the concentration is H 2 O: HF = 50 to 200: 1 by volume ratio. In addition, the specific SC-1 cleaning process is carried out by piranha washing and BHF. , RSC-1, BHF in this order, the BHF cleaning process is carried out using a BOE solution of NH 4 F: HF = 100 ~ 300: 1 volume ratio.

그리고, RSC-1 세정의 경우는 40 ∼ 80 ℃의 온도에서 15 ∼ 30 분 정도 실시한다.And in the case of RSC-1 washing | cleaning, it implements about 15 to 30 minutes at the temperature of 40-80 degreeC.

그리고, 특정 SC-1 세정공정은 각 린스 공정에 대해 피라나-QDR, DHF-오버플로우(overflow), RSC-1-QDR을 적용하되, 각각의 린스공정은 5 ∼ 10 분 정도 실시한다.In addition, the specific SC-1 cleaning process is applied to each rinse process by Pirana-QDR, DHF-overflow and RSC-1-QDR, but each rinse process is performed for about 5 to 10 minutes.

그 다음, 워드라인에 접속되는 텅스텐 폴리사이드 구조의 비트라인을 형성한다.Next, a bit line of tungsten polyside structure is formed which is connected to the word line.

이때, 비트라인은 제 2폴리(21)와 제 2텅스텐 실리사이드(23)의 적층구조로 형성된 텅스텐 폴리사이드 구조이다.At this time, the bit line is a tungsten polyside structure formed of a laminated structure of the second poly 21 and the second tungsten silicide 23.

상기한 바와 같이 본 발명에 따른 반도체소자의 콘택 형성방법은 워드라인과 비트라인의 콘택공정시 특정 SC-1 세정공정으로 부도체인 WO3와 손상된 텅스텐 실리사이드를 제거함으로써 콘택저항을 감소시키고 텅스텐 실리사이드 상부에 캐핑 폴리를 형성하지 않아도 되기 때문에 공정을 단순화시킬 수 있으며 구동전압을 감소시키고 캐패시터로의 신호이송속도가 증가된다는 효과가 있다.As described above, the method for forming a contact of a semiconductor device according to the present invention reduces contact resistance by removing WO 3 and damaged tungsten silicide by a specific SC-1 cleaning process during the contact process of the word line and the bit line, thereby reducing the contact resistance and Since there is no need to form a capping poly in the process, the process can be simplified, reducing the driving voltage and increasing the signal transfer speed to the capacitor.

Claims (8)

제 1폴리와 제 1텅스텐 실리사이드가 적층된 폴리사이드 구조의 워드라인을 형성하고 상기 워드라인 상측을 평탄화시키는 층간절연막을 형성한 다음, 상기 층간절연막을 통하여 상기 워드라인의 상기 제 1텅스텐 실리사이드를 노출시키는 콘택홀을 형성하고 상기 콘택홀을 통하여 상기 워드라인에 접속되는 제 2폴리와 제 2텅스텐 실리사이드 적층구조의 폴리사이드로 비트라인을 형성하는 반도체소자의 콘택 형성방법으로서,Forming a word line having a polyside structure in which a first poly and a first tungsten silicide are stacked, and forming an interlayer insulating film to planarize the word line, and exposing the first tungsten silicide of the word line through the interlayer insulating film. A method for forming a contact in a semiconductor device in which a bit line is formed by forming a contact hole for forming a contact hole and a polyside having a second poly and a second tungsten silicide stacked structure connected to the word line through the contact hole. 상기 콘택홀을 형성하고 콘택홀의 표면을 NH4OH : H2O2: 순수 = X : Y : Z 의 SC-1 용액을 사용하여 40∼80℃의 온도를 유지하는 wet 스테이션에서 특정 SC-1 세정 공정을 진행하여 세정하는 것을 특징으로 하는 반도체소자의 콘택 형성방법.The contact hole is formed and the surface of the contact hole is a specific SC-1 in a wet station that maintains a temperature of 40 to 80 ° C. using a SC-1 solution of NH 4 OH: H 2 O 2 : pure water = X: Y: Z. A contact forming method of a semiconductor device, characterized in that the cleaning process is performed by cleaning. 단. 상기 X, Y, Z 는 각각 0.5 ∼ 5, 0.5 ∼ 5, 5 ∼ 20 의 부피비임.only. The said X, Y, Z is a volume ratio of 0.5-5, 0.5-5, 5-20, respectively. 삭제delete 제 1 항에 있어서,The method of claim 1, 상기 특정 SC-1 세정공정은 피라나세정, DHF, RSC-1, DHF 의 순서로 실시하는 것을 특징으로하는 반도체소자의 콘택 형성방법.The specific SC-1 cleaning process is performed in the order of piranha washing, DHF, RSC-1, DHF. 제 1 항에 있어서,The method of claim 1, 상기 특정 SC-1 세정공정은 피라나세정, BHF, RSC-1, BHF 의 순서로 실시하는 것을 특징으로하는 반도체소자의 콘택 형성방법.The specific SC-1 cleaning process is performed in the order of piranha cleaning, BHF, RSC-1, BHF. 제 3 항에 있어서,The method of claim 3, wherein 상기 DHF 세정공정 시, 불산계 화학용액은 H2O : HF = 50∼200 : 1 부피비로 HF를 사용하는 것을 특징으로하는 반도체소자의 콘택 형성방법.In the DHF cleaning process, the hydrofluoric acid-based chemical solution is H 2 O: HF = 50 to 200: The contact forming method of a semiconductor device, characterized in that using HF in a volume ratio. 제 4 항에 있어서,The method of claim 4, wherein 상기 BHF 세정공정 시, NH4F : HF = 100∼300 : 1 부피비로 BOE 용액을 사용하는 것을 특징으로하는 반도체소자의 콘택 형성방법.The method of forming a contact of a semiconductor device, characterized in that during the BHF cleaning step, using a BOE solution in the NH 4 F: HF = 100 to 300: 1 volume ratio. 제 3 항에 있어서,The method of claim 3, wherein 상기 RSC-1 세정공정은 40 ∼ 80 ℃ 의 온도에서 15 ∼ 30 분 동안 실시하는 것을 특징으로하는 반도체소자의 콘택 형성방법.The RSC-1 cleaning process is performed for 15 to 30 minutes at a temperature of 40 to 80 ℃ contact method of a semiconductor device. 제 1 항에 있어서,The method of claim 1, 상기 특정 SC-1 세정공정은 각 린스 공정에 대해 피라나-QDR, DHF-오버플로우, RSC-1-QDR을 적용하되, 각각의 린스공정은 5 ∼ 10 분 정도 실시하는 것을 특징으로하는 반도체소자의 콘택 형성방법.In the specific SC-1 cleaning process, Pirana-QDR, DHF-overflow, and RSC-1-QDR are applied to each rinse step, but each rinse step is performed for about 5 to 10 minutes. Contact formation method.
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