KR20080062527A - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor device Download PDFInfo
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- KR20080062527A KR20080062527A KR1020060138461A KR20060138461A KR20080062527A KR 20080062527 A KR20080062527 A KR 20080062527A KR 1020060138461 A KR1020060138461 A KR 1020060138461A KR 20060138461 A KR20060138461 A KR 20060138461A KR 20080062527 A KR20080062527 A KR 20080062527A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 46
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 31
- 238000000034 method Methods 0.000 claims abstract description 48
- 150000004767 nitrides Chemical class 0.000 claims abstract description 28
- 239000002002 slurry Substances 0.000 claims abstract description 27
- 239000011229 interlayer Substances 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 239000010410 layer Substances 0.000 claims abstract description 13
- 239000002253 acid Substances 0.000 claims abstract description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 4
- 239000008119 colloidal silica Substances 0.000 claims abstract description 4
- 229910052751 metal Inorganic materials 0.000 claims description 22
- 239000002184 metal Substances 0.000 claims description 22
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 16
- 229920005591 polysilicon Polymers 0.000 claims description 16
- 239000007800 oxidant agent Substances 0.000 claims description 13
- 230000002378 acidificating effect Effects 0.000 claims description 12
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 11
- 239000010937 tungsten Substances 0.000 claims description 11
- 229910052721 tungsten Inorganic materials 0.000 claims description 11
- 229910021332 silicide Inorganic materials 0.000 claims description 8
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 8
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 239000010941 cobalt Substances 0.000 claims description 3
- 229910017052 cobalt Inorganic materials 0.000 claims description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 239000002245 particle Substances 0.000 claims description 3
- 239000002904 solvent Substances 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical class OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims description 2
- 238000005406 washing Methods 0.000 claims description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims 1
- 239000011737 fluorine Substances 0.000 claims 1
- 229910052731 fluorine Inorganic materials 0.000 claims 1
- 238000005498 polishing Methods 0.000 abstract description 21
- 230000007547 defect Effects 0.000 abstract description 5
- 239000000126 substance Substances 0.000 abstract description 3
- 239000005380 borophosphosilicate glass Substances 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- 235000011114 ammonium hydroxide Nutrition 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 235000011007 phosphoric acid Nutrition 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
도 1은 종래의 반도체 소자의 제조방법에 따른 문제점을 도시한 그래프.1 is a graph showing a problem according to a conventional method for manufacturing a semiconductor device.
도 2 및 도 3은 종래의 반도체 소자의 제조방법에 따른 문제점을 도시한 사진.2 and 3 are photographs showing a problem according to a conventional method for manufacturing a semiconductor device.
도 4a 및 도 4e는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정별 단면도.4A and 4E are cross-sectional views of processes for describing a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
도 5는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 그래프.5 is a graph illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
도 6 및 도 9는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 사진.6 and 9 are photographs for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
400 : 소자분리막 402 : 반도체기판400: device isolation layer 402: semiconductor substrate
404 : 게이트산화막 406 : 게이트용 도전막404: gate oxide film 406: gate conductive film
408 : 하드마스크질화막 410 : 게이트408: hard mask nitride film 410: gate
412 : 스페이서 414 : 층간절연막412
416 : 랜딩플러그콘택 418 : 도전막416: landing plug contact 418: conductive film
420 : 랜딩플러그폴리420: Landing Plug Poly
본 발명은 반도체 소자의 제조방법에 관한 것으로, 보다 상세하게는, 폴리실리콘막 및 산화막의 디싱(dishing)에 의한 결함의 발생을 방지할 수 있는 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of preventing generation of defects due to dishing of a polysilicon film and an oxide film.
반도체 소자의 고집적화에 따라 상,하부 패턴들간, 특히 기판 접합영역과 비트라인간 및 기판 접합영역과 캐패시터 간이 전기적 연결에 어려움을 겪게 되었다. 이에, 현재 대부분의 반도체 제조 공정에서는 상하부 패턴간의 안정적인 전기적 접속을 위해 자기정렬콘택(self aligned contact : 이하 SAC) 공정을 통해 접합영역 상에 랜딩플러그폴리(Landing Plug Poly)를 형성하고 있으며, 이러한 랜딩플러그폴리를 통해 접합영역과 비트라인 및 접합영역과 캐패시터 간의 전기적 연결이 안정적으로 이루어지도록 하고 있다. Due to the high integration of semiconductor devices, it has been difficult to electrically connect between upper and lower patterns, in particular, between the substrate junction region and the bit line, and between the substrate junction region and the capacitor. Therefore, in most semiconductor manufacturing processes, a landing plug poly is formed on a junction region through a self aligned contact (SAC) process for stable electrical connection between upper and lower patterns. The plug poly ensures a stable electrical connection between the junction region, the bit line, and the junction region and the capacitor.
한편, 종래의 반도체 제조 공정은 게이트를 형성한 다음, 층간절연막으로서 BPSG막을 증착하고, 이어서, 어닐링을 통해 상기 BPSG막을 플로우(flow)시켜 완전한 매립(Gap-Fill)이 이루어지도록 하고 있다. Meanwhile, in the conventional semiconductor manufacturing process, after forming a gate, a BPSG film is deposited as an interlayer insulating film, and then the BPSG film is flowed through annealing to achieve complete gap-filling.
그러나, 종래의 랜딩 플러그 폴리 형성방법에 따르면, 폴리실리콘막의 증착 후, 염기성 슬러리를 사용하여 CMP(Chemical Mechanical Polishing) 공정을 진행하고 있는데, 이와 같이 염기성 슬러리를 사용하여 CMP 공정을 진행하는 경우, 산화막과 질화막에 대한 CMP 공정의 연마 선택비가 낮아, 도 1의 그래프에 도시된 바와 같이, BPSG막과 폴리실리콘막의 연마속도가 높으며 질화막과 5∼8배 정도의 연마속도의 차이가 나게 되어, 결과적으로, CMP 공정 수행 후, BPSG막 및 폴리실리콘막과 질화막간의 단차가 발생하게 된다. However, according to the conventional method of forming a landing plug poly, after the deposition of the polysilicon film, a CMP (Chemical Mechanical Polishing) process is performed using a basic slurry. In this case, when the CMP process is performed using a basic slurry, an oxide film is used. As shown in the graph of FIG. 1, the polishing selectivity of the CMP process with respect to the nitride film is low, and the polishing rate of the BPSG film and the polysilicon film is high, and the polishing rate is about 5 to 8 times that of the nitride film. After the CMP process, a step between the BPSG film and the polysilicon film and the nitride film occurs.
이러한 각각의 연마속도의 차이로 인한 단차 및 염기성 슬러리의 사용으로 인하여 층간절연막 물질인 BPSG막은 물론 플러그 물질인 폴리실리콘막의 표면에서 도 2에 도시된 바와 같이, 디싱(dishing)이 발생될 수 있다. Due to the use of the step and the basic slurry due to the difference in each polishing rate, dishing may occur on the surface of the interlayer insulating material BPSG film as well as the plug material polysilicon film as shown in FIG. 2.
이에 따라, 상기한 디싱 문제를 해결하기 위해서는 별도의 산화막을 추가로 증착해야만 하므로 공정상의 번거로움이 존재할 수 밖에 없다. Accordingly, in order to solve the dishing problem described above, a separate oxide film must be additionally deposited, so that there may be inconvenience in process.
특히, 디싱 지역에 빠진 연마잔류물은 후속 세정(cleaning) 공정에서 완전히 제거되지 않고 잔류될 수 있으며, 이 경우에는 도 3에 도시된 바와 같이, 비트라인 콘택 또는 스토리지 노드 콘택들 간에 브릿지(bridge)가 유발되어 소자 수율 저하(yield loss)가 유발된다. In particular, abrasive residues missing in the dishing area may remain without being completely removed in a subsequent cleaning process, in which case a bridge between bitline contacts or storage node contacts, as shown in FIG. 3. Is induced, leading to a yield loss.
따라서, 본 발명은 층간절연막 및 폴리실리콘막의 디싱 발생을 방지하여 반도체 소자의 수율 저하를 방지할 수 있는 반도체 소자의 제조방법을 제공한다.Accordingly, the present invention provides a method of manufacturing a semiconductor device capable of preventing the occurrence of dishing between the interlayer insulating film and the polysilicon film, thereby preventing a decrease in yield of the semiconductor device.
일 실시예에 있어서, 반도체 소자의 제조방법은, 반도체기판 상에 상부에 하드마스크 질화막을 구비한 게이트들을 형성하는 단계; 상기 게이트들 사이의 기판 표면내에 접합영역을 형성하는 단계; 상기 게이트들을 덮도록 기판 결과물 상에 층간절연막을 형성하는 단계; 상기 게이트의 하드마스크 질화막이 노출되도록 층간절 연막을 CMP하는 단계; 상기 CMP된 층간절연막을 식각하여 게이트 및 게이트들 사이의 접합영역을 노출시키는 랜딩플러그콘택을 형성하는 단계; 상기 랜딩플러그콘택을 매립하도록 기판 결과물 상에 도전막을 증착하는 단계; 및 상기 게이트의 하드마스크 질화막이 노출되도록 도전막을 산화제가 첨가된 산성 슬러리를 사용하여 CMP하는 단계;를 포함한다.In one embodiment, a method of manufacturing a semiconductor device includes: forming gates having a hard mask nitride film on a semiconductor substrate thereon; Forming a junction region in the substrate surface between the gates; Forming an interlayer insulating film on a substrate resultant to cover the gates; CMPing the interlayer insulation film so that the hard mask nitride film of the gate is exposed; Etching the CMP interlayer insulating film to form a landing plug contact exposing a gate and a junction region between the gates; Depositing a conductive film on a substrate product to fill the landing plug contact; And CMP using the acidic slurry to which the oxidizing agent is added so that the hard mask nitride film of the gate is exposed.
상기 산화제는 H2O2, CaO2, BaO2, Na2O2, Fe(NO3)3 및 H5IO6 중의 어느 하나를 1∼5%의 농도로 첨가한다.The oxidant adds any one of H 2 O 2, CaO 2, BaO 2, Na 2 O 2, Fe (NO 3) 3, and H 5 IO 6 to a concentration of 1 to 5%.
상기 산성 슬러리는 콜로이들(colloidal) 실리카 연마재 인것을 특징으로 한다.The acidic slurry is characterized in that the colloidal silica abrasive.
상기 산성 슬러리는 1∼5 pH인 것을 사용한다.The acid slurry is one having a pH of 1 to 5.
상기 산성 슬러리는 연마입자의 농도가 5∼30%인 것을 사용한다.The acid slurry is one having a concentration of abrasive particles of 5 to 30%.
상기 산성 슬러리는 H3PO4 계열의 성분을 1∼10%의 농도로 첨가한다.The acidic slurry is added to the H 3 PO 4 series of components at a concentration of 1 to 10%.
상기 도전막은 폴리실리콘막 또는 금속막을 사용한다.The conductive film uses a polysilicon film or a metal film.
상기 금속막은 질화티타늄막 또는 텅스텐막을 사용한다.The metal film is a titanium nitride film or a tungsten film.
상기 도전막은 SEG 또는 SPE 공정에 의한 에피-실리콘막인 것을 사용한다.The conductive film is an epi-silicon film by SEG or SPE process.
상기 도전막은 에피-실리콘막과 금속실리사이드막 및 금속막의 적층막으로 이루어진다.The conductive film is formed of a laminated film of an epi-silicon film, a metal silicide film, and a metal film.
상기 금속실리사이드막은 티타늄막 또는 코발트막을 사용한다.The metal silicide film uses a titanium film or a cobalt film.
상기 금속실리사이드막은 CVD 또는 PVD 방법을 이용하여 형성한다.The metal silicide film is formed using a CVD or PVD method.
상기 금속막의 적층막은 텅스텐막 또는 질화티타늄막을 사용한다.As the laminated film of the metal film, a tungsten film or a titanium nitride film is used.
상기 금속막의 적층막은 CVD 또는 PVD 방법을 이용하여 형성한다.The laminated film of the metal film is formed using a CVD or PVD method.
상기 게이트의 하드마스크 질화막이 노출되도록 도전막을 산화제가 첨가된 산성 슬러리를 사용하여 CMP하는 단계 후, 상기 랜딩플러그 상에 잔류물을 제거하기 위하여 SC-1, NH4OH+HF 및 플로린 또는 하이드로실라민 계열의 솔벤트를 이용하여 세정하는 단계;를 더 포함한다.CMP using an acidic slurry with an oxidant added to expose the hard mask nitride layer of the gate, and then SC-1, NH4OH + HF and florin or hydrosilamine-based to remove residue on the landing plug. It further comprises the step of cleaning with a solvent of.
(실시예)(Example)
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.
본 발명은 산화막 대 질화막의 연마선택비가 우수한 산성 슬러리를 이용하여 랜딩 플러그의 CMP 공정을 수행한다. 아울러, 하드마스크질화막, 폴리실리콘 및 텅스텐의 연마속도를 조절하기 위해 산화제를 첨가하여 상기 랜딩 플러그의 CMP 공정을 수행한다.The present invention performs a CMP process of the landing plug using an acid slurry having excellent polishing selectivity of oxide to nitride. In addition, the CMP process of the landing plug is performed by adding an oxidizing agent to adjust the polishing rate of the hard mask nitride film, polysilicon and tungsten.
이 경우, 본 발명은 산화막 대 질화막의 연마선택비가 우수한 산성의 슬러리를 이용하여 랜딩 플러그의 CMP 공정을 수행함으로써 산화막과 질화막의 연마속도를 조절할 수 있고, 이에 따라, 디싱(dishing)의 발생을 방지할 수 있어서. 상기 디싱에 의해 야기되는 반도체 소자의 결함 발생을 방지할 수 있다.In this case, the present invention can control the polishing rate of the oxide film and the nitride film by performing the CMP process of the landing plug using an acid slurry having an excellent polishing selectivity of the oxide film to the nitride film, thereby preventing the occurrence of dishing. I can do it. It is possible to prevent the occurrence of defects in the semiconductor element caused by the dishing.
또한, 본 발명은 산화제를 첨가하여 CMP 공정을 수행함으로써, 폴리실리콘막과 텅스텐막의 연마속도를 조절할 수 있어, 후속의 층간절연막 CMP 공정에서 발생하는 폴리실리콘막의 스크래치로 인한 비트라인간의 브릿지를 방지할 수 있음에 따라서, 반도체 소자의 수율을 증가시킬 수 있다.In addition, the present invention can control the polishing rate of the polysilicon film and tungsten film by adding the oxidizing agent, thereby preventing the bridge between the bit lines due to the scratch of the polysilicon film generated in the subsequent interlayer insulating film CMP process. As can be, the yield of the semiconductor device can be increased.
도 4a 및 도 4e는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정별 단면도이다.4A and 4E are cross-sectional views of processes for describing a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
도 4a를 참조하면, 소자분리막(400)을 구비한 반도체기판(402) 상에 게이트 산화막(404), 게이트용 도전막(406) 및 하드마스크 질화막(408)의 적층 구조로 된 수 개의 게이트(410)를 형성하고, 상기 게이트(410)의 양측벽에 스페이서(412)를 형성한다. 그런 다음, 상기 게이트(410)들 양측 사이의 기판(402) 표면 내에 접합영역을 형성하고, 상기 게이트(410)들을 덮도록 기판(402) 전면 상에 층간절연막(414)을 증착한다.Referring to FIG. 4A, a plurality of gates having a stacked structure of a
도 4b를 참조하면, 상기 하드마스크 질화막(408)이 노출되도록 상기 층간절연막(414)을 CMP(chemical mechanical polishing)하여 평탄화시킨다. Referring to FIG. 4B, the
도 4c를 참조하면, 상기 평탄화된 층간절연막(414)을 식각하여 수 개의 게이트(410) 및 기판(402) 접합영역을 동시에 노출시키는 랜딩플러그콘택(landing plug contact : 416))을 형성한다. Referring to FIG. 4C, the planarized
도 4d를 참조하면, 상기 랜딩플러그콘택(416)을 매립하도록 기판(402) 결과물 상에 도전막(418)을 증착한다. 여기서, 상기 도전막은 폴리실리콘막, 금속막, 및 SEG 또는 SPE 공정에 의한 에피-실리콘막과 금속실리사이드막 및 금속막의 적층막으로 형성하도록 한다. Referring to FIG. 4D, a
또한, 상기 금속막은 질화티타늄막 또는 텅스텐막을 사용하고, 상기 금속실리사이드막은 CVD 또는 PVD 방법을 이용한 티타늄막 또는 코발트막을 사용하며, 상기 금속막의 적층막은 CVD 또는 PVD 방법을 이용한 텅스텐막 또는 질화티타늄막을 사용하도록 한다.The metal film may be a titanium nitride film or a tungsten film. The metal silicide film may be a titanium film or a cobalt film using a CVD or PVD method. The metal film may be a tungsten film or a titanium nitride film using a CVD or PVD method. Do it.
도 4e를 참조하면, 상기 게이트(410)의 하드마스크 질화막(408)이 노출될 때까지 도전막(418)을 산화제가 첨가된 산성 슬러리를 사용하여 CMP하여, 게이트(410)들 사이의 기판(402) 접합영역 상에 랜딩플러그폴리(420)를 형성한다.Referring to FIG. 4E, the
여기서, 상기 산화제는 H2O2, CaO2, BaO2, Na2O2, Fe(NO3)3 및 H5IO6 중의 어느 하나인 것을 1∼5%의 농도로 첨가하도록 한다. 또한, 상기 산성 슬러리는 콜로이들(colloidal) 실리카 연마재로 이루어지며, 그리고 1∼5 pH, 연마입자의 농도는 5∼30% 이고, H3PO4 계열의 성분을 1∼10%의 농도로 첨가하여 수행하도록 한다.Here, the oxidizing agent is added to any one of H 2 O 2, CaO 2, BaO 2, Na 2 O 2, Fe (NO 3) 3 and H 5 IO 6 at a concentration of 1 to 5%. In addition, the acid slurry is made of a colloidal silica abrasive, 1 to 5 pH, the concentration of abrasive particles is 5 to 30%, H3PO4-based components to be carried out by adding a concentration of 1 to 10% do.
이후, 도시하지는 않았지만, 상기 게이트의 하드마스크 질화막이 노출되도록 도전막을 산화제가 첨가된 산성 슬러리를 사용하여 CMP하는 단계 후에, 상기 랜딩플러그 상에 잔류물을 제거하기 위하여 SC-1, NH4OH+HF 및 플로린 또는 하이드로실라민 계열의 솔벤트로 세정하여 본 발명의 실시예에 따른 반도체 소자를 완성한다.Subsequently, although not shown, after the step of CMPing the conductive film using an acidic slurry to which the oxidizing agent is added to expose the hard mask nitride film of the gate, SC-1, NH 4 OH + HF and to remove the residue on the landing plug. The semiconductor device according to the embodiment of the present invention is completed by washing with a florin or hydrosilamine-based solvent.
도 5는 본 발명의 실시예에 따른 반도체 소자의 제조방법에 의한 그래프를 도시한 단면도로서, 산성 슬러리를 사용하여 CMP 공정을 수행함으로써, 텅스텐막 및 콘택플러그폴리막의 연마속도는 높으며 층간절연막인 BPSG막과 하드마스크 질화막의 연마속도는 거의 비슷하게 유지할 수 있음을 알 수 있다. 5 is a cross-sectional view illustrating a graph of a method of manufacturing a semiconductor device according to an embodiment of the present invention. By performing a CMP process using an acidic slurry, a polishing rate of a tungsten film and a contact plug poly film is high and an interlayer insulating film is BPSG. It can be seen that the polishing rates of the film and the hard mask nitride film can be maintained at about the same.
도 6 내지 도 9는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 도시한 사진이다. 6 to 9 are photographs showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.
도시된 바와 같이, 산성 슬러리를 사용한 CMP 공정을 수행함으로써, 층간절연막과 하드마스크의 질화막의 연마 속도가 거의 비슷하기 때문에 페리(peri) 영역 과 양측의 셀 에지(cell edge) 및 셀 센터(cell center) 부분에 잔류한 층간절연막의 양은 거의 일정하여 손실이 거의 없음을 알 수 있다. 게다가, 콘택플러그 및 층간절연막의 손실이 100Å 미만인 것을 알 수 있다.As shown, by performing the CMP process using an acidic slurry, the polishing rates of the interlayer insulating film and the nitride film of the hard mask are almost the same, so that the peri region and the cell edge and the cell center of both sides are almost the same. It can be seen that the amount of the interlayer insulating film remaining in the () part is almost constant and there is almost no loss. In addition, it can be seen that the loss of the contact plug and the interlayer insulating film is less than 100 GPa.
이와 같이, 본 발명은 염기성의 슬러리를 이용하여 랜딩 플러그의 CMP 공정을 수행하는 종래의 반도체 소자의 제조방법과 달리, 산화막 대 질화막의 연마선택비가 우수한 산성의 슬러리를 이용하여 랜딩 플러그의 CMP 공정을 수행함으로써, 산화막과 질화막의 연마속도를 조절할 수 있어 콘택 플러그 및 산화막의 디싱에 의해 야기되는 반도체 소자의 결함을 방지할 수 있다.As described above, the present invention is different from the conventional method of manufacturing a semiconductor device in which the CMP process of the landing plug is performed by using a basic slurry, and the CMP process of the landing plug is performed by using an acidic slurry having excellent polishing selectivity of the oxide film and the nitride film. By performing, the polishing rate of the oxide film and the nitride film can be adjusted to prevent defects in the semiconductor device caused by dishing of the contact plug and the oxide film.
또한, 본 발명은 산화제를 첨가하여 CMP 공정을 수행함으로써, 폴리실리콘막과 텅스텐막의 연마속도를 조절할 수 있어, 후속의 층간절연막 CMP 공정에서 발생하는 폴리실리콘막의 스크래치로 인한 비트라인간의 브릿지를 방지할 수 있음에 따라서, 반도체 소자의 수율을 증가시킬 수 있다.In addition, the present invention can control the polishing rate of the polysilicon film and tungsten film by adding the oxidizing agent, thereby preventing the bridge between the bit lines due to the scratch of the polysilicon film generated in the subsequent interlayer insulating film CMP process. As can be, the yield of the semiconductor device can be increased.
이상, 전술한 본 발명의 실시예들에서는 특정 실시예에 관련하고 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다.In the above-described embodiments of the present invention, the present invention has been described and described with reference to specific embodiments, but the present invention is not limited thereto, and the scope of the following claims is not limited to the scope of the present invention. It will be readily apparent to those skilled in the art that the present invention may be variously modified and modified.
이상에서와 같이 본 발명은, 산성의 슬러리를 이용한 CMP 공정을 수행하여 산화막과 질화막의 연마속도를 조절할 수 있어 콘택 플러그 및 산화막의 디싱에 의해 야기되는 반도체 소자의 결함을 방지할 수 있다.As described above, according to the present invention, the polishing rate of the oxide film and the nitride film can be controlled by performing a CMP process using an acidic slurry to prevent defects in the semiconductor device caused by dishing of the contact plug and the oxide film.
또한, 본 발명은 산화제를 첨가하여 CMP 공정을 수행함으로써, 폴리실리콘막과 텅스텐막의 연마속도를 조절할 수 있어, 후속의 층간절연막 CMP 공정에서 발생하는 폴리실리콘막의 스크래치로 인한 비트라인간의 브릿지를 방지할 수 있음에 따라서, 반도체 소자의 수율을 증가시킬 수 있다.In addition, the present invention can control the polishing rate of the polysilicon film and tungsten film by adding the oxidizing agent, thereby preventing the bridge between the bit lines due to the scratch of the polysilicon film generated in the subsequent interlayer insulating film CMP process. As can be, the yield of the semiconductor device can be increased.
Claims (15)
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