KR100333716B1 - Semiconductor device fabrication method capable of reducing contact resistance of bit line - Google Patents
Semiconductor device fabrication method capable of reducing contact resistance of bit line Download PDFInfo
- Publication number
- KR100333716B1 KR100333716B1 KR1019980024708A KR19980024708A KR100333716B1 KR 100333716 B1 KR100333716 B1 KR 100333716B1 KR 1019980024708 A KR1019980024708 A KR 1019980024708A KR 19980024708 A KR19980024708 A KR 19980024708A KR 100333716 B1 KR100333716 B1 KR 100333716B1
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor device
- word line
- interlayer insulating
- bit line
- insulating film
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 15
- 238000005389 semiconductor device fabrication Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 claims abstract description 27
- 239000011229 interlayer Substances 0.000 claims abstract description 19
- 230000002093 peripheral effect Effects 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 12
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 9
- 239000010937 tungsten Substances 0.000 claims abstract description 9
- 238000001039 wet etching Methods 0.000 claims abstract description 9
- 239000003637 basic solution Substances 0.000 claims abstract description 7
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 6
- QGLKJKCYBOYXKC-UHFFFAOYSA-N nonaoxidotritungsten Chemical compound O=[W]1(=O)O[W](=O)(=O)O[W](=O)(=O)O1 QGLKJKCYBOYXKC-UHFFFAOYSA-N 0.000 claims description 3
- 229910001930 tungsten oxide Inorganic materials 0.000 claims description 3
- QOSATHPSBFQAML-UHFFFAOYSA-N hydrogen peroxide;hydrate Chemical compound O.OO QOSATHPSBFQAML-UHFFFAOYSA-N 0.000 claims 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 abstract description 7
- 229910021342 tungsten silicide Inorganic materials 0.000 abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 239000010410 layer Substances 0.000 description 4
- 239000007864 aqueous solution Substances 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 239000007789 gas Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/488—Word lines
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 텅스텐 폴리사이드 구조의 워드라인을 갖는 반도체 장치 제조 공정 중, 비트라인과 콘택될 주변회로영역의 워드라인을 노출시키는 층간절연막 식각 과정에서 워드라인 상에 형성된 WO3막을 효과적으로 제거하여 비트라인의 콘택저항을 효과적으로 감소시킬 수 있는 반도체 장치 제조 방법에 관한 것으로, 층간절연막을 선택적으로 식각하여 비트라인과 콘택될 셀영역의 반도체 기판과 주변회로영역의 워드라인을 노출시킨 후, NH4OH 등의 염기성 용액을 이용한 습식식각을 실시하여, 층간절연막 식각시 텅스텐 실리사이드 상에 형성된 WO3막을 제거하는데 그 특징이 있다.The present invention effectively removes the bit line by removing the WO 3 film formed on the word line during the interlayer insulating film etching process that exposes the word line of the peripheral circuit region to be contacted with the bit line during the semiconductor device manufacturing process having the word line of the tungsten polyside structure. A method of manufacturing a semiconductor device capable of effectively reducing contact resistance of a semiconductor device, the method comprising: selectively etching an interlayer insulating film to expose a semiconductor substrate of a cell region to be contacted with a bit line and a word line of a peripheral circuit region, and then, NH 4 OH, or the like. The wet etching is performed using a basic solution of to remove the WO 3 film formed on the tungsten silicide during the interlayer insulating film etching.
Description
본 발명은 반도체 장치 제조 분야에 관한 것으로, 텅스텐 폴리사이드 구조의 워드라인과 비트라인의 콘택 저항을 감소시킬 수 있는 반도체 장치 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of semiconductor device manufacturing, and more particularly, to a method of manufacturing a semiconductor device capable of reducing contact resistance of a word line and a bit line of a tungsten polyside structure.
반도체 장치의 셀영역에서는 반도체 기판과 비트라인이 콘택되고, 주변회로영역에서는 워드라인(word line)과 비트라인(bit line)이 콘택된다. 워드라인(word line)을 텅스텐 폴리사이드(polycide)로 형성한 후, 폴리실리콘막 또는 폴리사이드로 비트라인을 형성하는 공정에서, 주변회로영역에서는 비트라인을 이루는 폴리실리콘막과 워드라인을 이루는 텅스텐 폴리사이드 상부의 텅스텐 실리사이드(WSix)가 접하게 된다.The semiconductor substrate and the bit line are contacted in the cell region of the semiconductor device, and the word line and the bit line are contacted in the peripheral circuit region. In the process of forming a word line from a tungsten polycide and then forming a bit line from a polysilicon film or polyside, in a peripheral circuit region, tungsten forming a word line and a polysilicon film forming a bit line Tungsten silicide (WSi x ) on top of the polyside is in contact.
비트라인 콘택 부분의 저항을 감소시키기 위하여 층간절연막을 선택적으로 식각하여 비트라인과 연결될 부분을 노출시킨 후 불산계 수용액을 이용한 세정공정을 실시한다. 그러나, 주변회로영역에서는 층간절연막 식각시 사용되는 CF4및 O2등의 식각가스에 의해 텅스텐 실리사이드 상부에 형성된 WO3막이 세정공정에서 효과적으로 제거되지 않아 콘택저항이 증가되는 문제점이 있다.In order to reduce the resistance of the bit line contact portion, the interlayer insulating film is selectively etched to expose the portion to be connected to the bit line, and then a cleaning process using a hydrofluoric acid-based aqueous solution is performed. However, in the peripheral circuit region, the WO 3 film formed on the tungsten silicide by etching gases such as CF 4 and O 2 used in the interlayer insulating film is not effectively removed in the cleaning process, thereby increasing the contact resistance.
상기와 같은 문제점을 해결하기 위한 본 발명은 텅스텐 폴리사이드 구조의 워드라인을 갖는 반도체 장치 제조 공정 중, 비트라인과 콘택될 주변회로영역의 워드라인을 노출시키는 층간절연막 식각과정에서 워드라인 상에 형성된 WO3막을 효과적으로 제거하여 비트라인의 콘택저항을 효과적으로 감소시킬 수 있는 반도체 장치 제조 방법을 제공하는데 그 목적이 있다.The present invention to solve the above problems is formed on the word line during the interlayer insulating film etching process to expose the word line of the peripheral circuit region to be contacted with the bit line during the semiconductor device manufacturing process having a word line of the tungsten polyside structure It is an object of the present invention to provide a method for manufacturing a semiconductor device that can effectively remove the WO 3 film and effectively reduce the contact resistance of the bit line.
도1 내지 도3은 본 발명의 일실시예에 따른 반도체 장치 제조 공정 단면도1 to 3 are cross-sectional views of a semiconductor device manufacturing process in accordance with an embodiment of the present invention.
* 도면의 주요 부분에 대한 도면 부호의 설명* Explanation of reference numerals for the main parts of the drawings
1: 반도체 기판 2: 소자분리막1: semiconductor substrate 2: device isolation film
3: 게이트 산화막 4: 절연막 스페이서3: gate oxide film 4: insulating film spacer
5: 폴리실리콘막 6: 텅스텐 실리사이드5: polysilicon film 6: tungsten silicide
7: 마스크 산화막 8: 층간절연막7: mask oxide film 8: interlayer insulating film
9: WO3막 10: 폴리실리콘막9: WO 3 film 10: polysilicon film
상기 목적을 달성하기 위한 본 발명은, 셀영역과 주변회로영역의 반도체 기판 상에 텅스텐 폴리사이드(polycide) 구조의 워드라인(word line)을 형성하는 제1 단계; 상기 제1 단계가 완료된 전체 구조 상에 층간절연막을 형성하고, 상기 층간절연막을 선택적으로 식각하여 상기 셀영역의 반도체 기판과 상기 주변회로영역의 워드라인을 노출시키는 콘택홀을 형성하는 제2 단계; 및 염기성 용액을 이용한 습식식각으로, 상기 제2 단계에서 상기 주변회로의 워드라인 상에 형성된 텅스텐 산화막을 제거하는 제3 단계를 포함하는 반도체 장치 제조 방법을 제공한다.The present invention for achieving the above object, the first step of forming a word line of the tungsten polycide (polycide) structure on the semiconductor substrate of the cell region and the peripheral circuit region; A second step of forming an interlayer insulating film on the entire structure in which the first step is completed, and forming a contact hole for selectively etching the interlayer insulating film to expose a semiconductor substrate of the cell region and a word line of the peripheral circuit region; And a third step of removing the tungsten oxide film formed on the word line of the peripheral circuit in the second step by wet etching using a basic solution.
본 발명은 텅스텐 폴리사이드 구조의 워드라인과 비트라인의 콘택 저항을 감소시키기 위하여, 층간절연막을 선택적으로 식각하여 비트라인과 콘택될 셀영역의 반도체 기판과 주변회로영역의 워드라인을 노출시킨 후, NH4OH 등의 염기성 용액을 이용한 습식식각을 실시하여, 층간절연막 식각시 텅스텐 실리사이드 상에 형성된 WO3막을 제거하는데 그 특징이 있다.According to the present invention, in order to reduce the contact resistance of the word line and the bit line of the tungsten polyside structure, the interlayer insulating film is selectively etched to expose the semiconductor substrate of the cell region to be contacted with the bit line and the word line of the peripheral circuit region. The wet etching using a basic solution such as NH 4 OH is performed to remove the WO 3 film formed on the tungsten silicide during the interlayer insulating film etching.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 바람직한 실시예를 첨부된 도면 도1 내지 도3를 참조하여 설명한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. Will be explained.
먼저, 도1에 도시한 바와 같이 500 Å 내지 900 Å 두께의 폴리실리콘막(5) 및 600 Å 내지 900 Å 두께의 텅스텐 실리사이드(6)로 이루어진 폴리사이드 구조의 워드라인 형성이 완료된 반도체 기판(1) 상에 700 Å 내지 1100 Å 두께의 층간절연막(8)을 형성한다. 상기 층간절연막(8)은 BPSG(borophospho silicate glass)막으로 형성한다. 도1에서 미설명 도면부호 '2'는 소자분리막, '3'은 게이트 산화막,'4'는 절연막 스페이서, '7'은 마스크 산화막, 'A'는 셀영역, 'B'는 주변회로영역을 나타낸다.First, as shown in FIG. 1, the semiconductor substrate 1 having completed the polyline structured word line formed of a polysilicon film 5 having a thickness of 500 mW to 900 mW and a tungsten silicide 6 having a thickness of 600 mW to 900 mW is completed. ) To form an interlayer insulating film 8 having a thickness of 700 to 1100 Å. The interlayer insulating film 8 is formed of a borophospho silicate glass (BPSG) film. In FIG. 1, reference numeral '2' denotes an isolation layer, '3' denotes a gate oxide layer, '4' denotes an insulating film spacer, '7' denotes a mask oxide layer, 'A' denotes a cell region, and 'B' denotes a peripheral circuit region. Indicates.
다음으로, 도2에 도시한 바와 같이 CF4및 O2등의 식각가스를 이용한 건식식각으로 층간절연막(8) 및 마스크 산화막(7)을 선택적으로 식각하여 셀영역(A)의 반도체 기판(3)과 주변회로영역(B)의 워드라인을 노출시키는 콘택홀을 형성한다. 이때, 워드라인을 이루는 주변회로의 텅스텐 실리사이드(6) 상에 WO3막(9)이 형성된다.Next, as shown in FIG. 2, the interlayer insulating film 8 and the mask oxide film 7 are selectively etched by dry etching using an etching gas such as CF 4 and O 2 to thereby provide a semiconductor substrate 3 in the cell region A. FIG. ) And a contact hole exposing the word line of the peripheral circuit region (B). At this time, the WO 3 film 9 is formed on the tungsten silicide 6 of the peripheral circuit forming the word line.
이어서, 20 wt% 내지 30 wt%의 NH4OH가 포함된 염기성 수용액으로 50 ℃ 내지 80 ℃ 온도에서 습식식각을 실시하여 층간절연막(8) 식각시 주변회로영역의 워드라인 상에 형성된 WO3막(9)을 제거한다. 상기 염기성 수용액에 과산화수소수를 더 첨가하기도 한다.Subsequently, the wet etching was performed at a temperature of 50 ° C. to 80 ° C. with a basic aqueous solution containing 20 wt% to 30 wt% of NH 4 OH to form a WO 3 film formed on the word line of the peripheral circuit region when the interlayer insulating film 8 was etched. Remove (9). Hydrogen peroxide solution may be further added to the basic aqueous solution.
상기 습식식각 조건에서 WO3막의 식각률은 200 Å/분 내지 400 Å/분이고, 열산화막의 식각률은 1 Å/분 내지 2 Å/분, 폴리실리콘막의 식각률은 20 Å/분 내지 30 Å/분, BPSG막의 식각률은 60 Å/분 내지 70 Å/분이다. 따라서, 습식식각으로 인한 반도체 기판의 손상 및 층간절연막의 손상으로 인한 콘택홀 크기 확장 문제는 발생하지 않는다.In the wet etching conditions, the etching rate of the WO 3 film is 200 mW / min to 400 mW / min, the etching rate of the thermal oxide film is 1 mW / min to 2 mW / min, the polysilicon film is 20 mW / min to 30 mW / min, The etching rate of the BPSG film is 60 mW / min to 70 mW / min. Therefore, the problem of contact hole size expansion caused by damage of the semiconductor substrate and damage of the interlayer insulating layer due to wet etching does not occur.
상기 습식식각 후 자연산화막 제거를 위하여 불산계 용액을 이용한 세정공정을 실시한다.After the wet etching, a cleaning process using a hydrofluoric acid-based solution is performed to remove the native oxide film.
다음으로, 도3에 도시한 바와 같이 500 Å 내지 2000 Å 두께의 폴리실리콘막(10)을 증착하여 셀영역(A)의 반도체 기판(1)과 주변회로영역의 워드라인과 연결되는 비트라인을 형성한다.Next, as shown in FIG. 3, a polysilicon film 10 having a thickness of 500 kHz to 2000 kHz is deposited to form a bit line connected to the semiconductor substrate 1 of the cell region A and the word line of the peripheral circuit region. Form.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
상기와 같이 이루어지는 본 발명은 텅스텐 폴리사이드 구조의 워드라인과 비트라인 콘택 저항의 원인이 되는 WO3막을 효과적으로 제거함으로써 소자의 특성 저하를 방지할 수 있다.According to the present invention as described above, it is possible to prevent the deterioration of device characteristics by effectively removing the WO 3 film which causes the word line and bit line contact resistance of the tungsten polyside structure.
Claims (7)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980024708A KR100333716B1 (en) | 1998-06-29 | 1998-06-29 | Semiconductor device fabrication method capable of reducing contact resistance of bit line |
| US09/338,525 US6114241A (en) | 1998-06-29 | 1999-06-23 | Method of manufacturing a semiconductor device capable of reducing contact resistance |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980024708A KR100333716B1 (en) | 1998-06-29 | 1998-06-29 | Semiconductor device fabrication method capable of reducing contact resistance of bit line |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20000003466A KR20000003466A (en) | 2000-01-15 |
| KR100333716B1 true KR100333716B1 (en) | 2002-09-05 |
Family
ID=19541236
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980024708A KR100333716B1 (en) | 1998-06-29 | 1998-06-29 | Semiconductor device fabrication method capable of reducing contact resistance of bit line |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100333716B1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030074855A (en) | 2002-03-14 | 2003-09-22 | (주)와콘 | Liquid pipe for detecting water leakage and establishing method |
-
1998
- 1998-06-29 KR KR1019980024708A patent/KR100333716B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR20000003466A (en) | 2000-01-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3797747B2 (en) | Method for forming buffer pad of semiconductor memory device | |
| US6875706B2 (en) | Cleaning solution and method of cleaning a semiconductor device using the same | |
| JP3228230B2 (en) | Method for manufacturing semiconductor device | |
| KR100333716B1 (en) | Semiconductor device fabrication method capable of reducing contact resistance of bit line | |
| KR20000042460A (en) | Method for forming bit line contact of semiconductor device | |
| KR100596899B1 (en) | Method for manufacturing semiconductor device | |
| KR100641916B1 (en) | Method for forming storage node of semiconductor devices | |
| KR100341593B1 (en) | Method for forming contact hole in semiconductor device | |
| KR100367403B1 (en) | Method for forming contact of a semiconductor device | |
| KR100546111B1 (en) | Manufacturing Method of Semiconductor Device | |
| KR950014271B1 (en) | Removing method of etching residue to polysilicon film | |
| KR100470391B1 (en) | Method for improving reflesh of semiconductor device | |
| KR100844935B1 (en) | Method for fabricating semiconductor device with landing plug contact structure | |
| KR100853477B1 (en) | Method for fabricating semiconductor device | |
| KR100200307B1 (en) | Method for forming a contact of a semiconductor device | |
| KR100607322B1 (en) | Method of manufacturing a flash EEPROM cell | |
| KR20030058264A (en) | Method for forming plug in semiconductor device | |
| KR100403951B1 (en) | Method for forming contact hole of semiconductor device | |
| KR960002102B1 (en) | Making method of poliside gate electrode | |
| KR20000025638A (en) | Method for forming contacts of semiconductor device | |
| KR20010063497A (en) | Method for forming contact plug of semiconductor device | |
| KR20040008685A (en) | Method for forming conduction line having hard mask layer in semiconductor device | |
| KR100701684B1 (en) | Method for manufacturing isolation pattern of word line in semiconductor device | |
| KR20000074480A (en) | Method for forming gate electrode of semiconductor device | |
| KR20010108779A (en) | Method for forming contact by using tantalum oxide etch barrier |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20120323 Year of fee payment: 11 |
|
| LAPS | Lapse due to unpaid annual fee |