KR100345165B1 - 반도체 패키지의 절단 방법 - Google Patents
반도체 패키지의 절단 방법 Download PDFInfo
- Publication number
- KR100345165B1 KR100345165B1 KR1020000045487A KR20000045487A KR100345165B1 KR 100345165 B1 KR100345165 B1 KR 100345165B1 KR 1020000045487 A KR1020000045487 A KR 1020000045487A KR 20000045487 A KR20000045487 A KR 20000045487A KR 100345165 B1 KR100345165 B1 KR 100345165B1
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- South Korea
- Prior art keywords
- lead
- lead frame
- photoresist pattern
- paddle
- encapsulant
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
Claims (3)
- 패들로부터 연장된 리드를 갖는 리드 프레임의 밑면 전체에 포토레지스트를 도포한 후 이를 패터닝하여, 상기 리드간의 연결 부위인 절단 부위만을 노출시키는 포토레지스트 패턴을 형성하는 단계;상기 리드 프레임의 패들상에 반도체 칩을 접착하고, 상기 반도체 칩과 리드를 와이어 본딩한 후, 상기 와이어 본딩 영역을 봉지제로 몰딩하는 단계;상기 포토레지스트 패턴을 식각 마스크로 하여, 노출된 리드의 절단 부위를 식각하여 제거하는 단계;상기 포토레지스트 패턴을 제거하는 단계;상기 제거된 리드의 절단 부위선상에 위치한 봉지제 부분만을 절단하는 단계를 포함하는 것을 특징으로 하는 반도체 패키지의 절단 방법.
- 제 1 항에 있어서, 상기 리드의 절단 부위를 노출시키는 포토레지스트 패턴이 갖는 식각홈의 폭을 리드의 절단 부위의 폭보다 동일하거나 또는 적어도 짧게 형성하는 것을 특징으로 하는 반도체 패키지의 절단 방법.
- 패들로부터 연장된 리드를 갖고, 상기 리드간의 연결 부위인 절단 부위의 표면 또는 밑면에 식각홈이 형성된 리드 프레임의 밑면 전체에 포토레지스트를 도포한 후 이를 패터닝하여, 상기 리드의 절단 부위만을 노출시키는 포토레지스트 패턴을 형성하는 단계;상기 리드 프레임의 패들상에 반도체 칩을 접착하고, 상기 반도체 칩과 리드를 와이어 본딩한 후, 상기 와이어 본딩 영역을 봉지제로 몰딩하는 단계;상기 포토레지스트 패턴을 식각 마스크로 하여, 노출된 리드의 절단 부위를 식각하여 제거하는 단계;상기 포토레지스트 패턴을 제거하는 단계;상기 제거된 리드의 절단 부위선상에 위치한 봉지제 부분만을 절단하는 단계를 포함하는 것을 특징으로 하는 반도체 패키지의 절단 방법.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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KR1020000045487A KR100345165B1 (ko) | 2000-08-05 | 2000-08-05 | 반도체 패키지의 절단 방법 |
Applications Claiming Priority (1)
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KR1020000045487A KR100345165B1 (ko) | 2000-08-05 | 2000-08-05 | 반도체 패키지의 절단 방법 |
Publications (2)
Publication Number | Publication Date |
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KR20020012060A KR20020012060A (ko) | 2002-02-15 |
KR100345165B1 true KR100345165B1 (ko) | 2002-07-24 |
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KR1020000045487A KR100345165B1 (ko) | 2000-08-05 | 2000-08-05 | 반도체 패키지의 절단 방법 |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103400778A (zh) * | 2013-08-06 | 2013-11-20 | 江苏长电科技股份有限公司 | 先蚀后封无源器件三维系统级金属线路板结构及工艺方法 |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20040011952A (ko) * | 2002-07-31 | 2004-02-11 | (주)칩트론 | 반도체 제조공정 |
KR20040011951A (ko) * | 2002-07-31 | 2004-02-11 | (주)칩트론 | 매핑 타입으로 몰딩된 반도체의 식각소잉공정 |
KR20100071485A (ko) | 2008-12-19 | 2010-06-29 | 삼성전기주식회사 | 웨이퍼 레벨 패키지의 제조방법 |
CN103035545B (zh) * | 2011-10-10 | 2017-10-17 | 马克西姆综合产品公司 | 使用引线框架的晶圆级封装方法 |
CN109256367B (zh) * | 2018-10-24 | 2024-03-22 | 嘉盛半导体(苏州)有限公司 | 预塑封引线框架、半导体封装结构及其单元、封装方法 |
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- 2000-08-05 KR KR1020000045487A patent/KR100345165B1/ko active IP Right Grant
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103400778A (zh) * | 2013-08-06 | 2013-11-20 | 江苏长电科技股份有限公司 | 先蚀后封无源器件三维系统级金属线路板结构及工艺方法 |
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