KR100345064B1 - Method of fabricating shallow trench isolation for preventing dishing - Google Patents
Method of fabricating shallow trench isolation for preventing dishing Download PDFInfo
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- KR100345064B1 KR100345064B1 KR1020000037121A KR20000037121A KR100345064B1 KR 100345064 B1 KR100345064 B1 KR 100345064B1 KR 1020000037121 A KR1020000037121 A KR 1020000037121A KR 20000037121 A KR20000037121 A KR 20000037121A KR 100345064 B1 KR100345064 B1 KR 100345064B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
Abstract
디싱을 방지하기 위한 쉘로우트렌치분리 형성방법은, STI형성 후 기판상부의 평탄화과정시 산화막매립 후, 이온주입에 의해 연마율을 조절하여 CMP공정을 실시함으로써, 디싱(Dishing)현상을 효과적으로 방지하기 위한 공정에 관한 것이다.The shallow trench isolation formation method for preventing dishing is performed to effectively prevent dishing by performing a CMP process by adjusting the polishing rate by ion implantation after the oxide film is buried in the planarization of the substrate after STI formation. It is about process.
본 발명은 형성된 쉘로우트렌치를 매립한 후, 이 매립층에 탄소이온을 주입하고 열처리공정을 실시함으로써, 굴곡진 매립층의 연마율을 다르게 조정한다. 이후 CMP에 의해 기판상부를 평탄화시킴으로써 디싱을 방지하여 쉘로우트렌치를 형성하는 다단계의 공정들을 포함하고 있다.The present invention adjusts the polishing rate of the curved buried layer differently by embedding the formed shallow trenches, injecting carbon ions into the buried layer and performing a heat treatment step. Thereafter, the planarization is performed by CMP to prevent dishing, thereby forming a shallow trench.
따라서 본 발명은 패턴밀도에 따른 디싱현상을 방지함으로써, 생산수율을 증대시키고 반도체소자의 전기적 특성을 향상시키는 효과가 있다.Therefore, the present invention prevents dishing according to the pattern density, thereby increasing the production yield and improving the electrical characteristics of the semiconductor device.
Description
본 발명은 STI(Shallow Trench Isolation)에 관련된 것으로, 보다 구체적으로는 STI(Shallow Trench Isolation) 형성 후 화학기계적연마(Chemical Mechanical Polishing; 이하 'CMP'라 함)에 의한 트렌치매립 산화막의 평탄화과정시 산화막매립 후, 이온주입에 의해 연마율을 조절하여 CMP공정을 실시함으로써, 디싱(Dishing)현상을 효과적으로 방지할 수 있는, 디싱을 방지하기 위한 쉘로우트렌치분리 형성방법에 관한 것이다.The present invention relates to shallow trench isolation (STI), and more particularly, to an oxide film during planarization of a trench buried oxide film by chemical mechanical polishing (hereinafter referred to as 'CMP') after the formation of shallow trench isolation (STI). The present invention relates to a shallow trench isolation formation method for preventing dishing, by performing a CMP process by adjusting the polishing rate by implantation after implantation, thereby effectively preventing dishing.
소자의 집적도가 0.20㎛ 이하로 향상됨에 따라, LOCOS(LOCal Oxidation of Silicon)방식에 의한 분리막(isolation)은 소자의 구동특성을 만족시키지 못하게 되었다. 따라서 이에 대한 대안으로 STI공정이 대두되었다.As the degree of integration of the device is improved to 0.20 μm or less, the isolation by the LOCOS (LOCal Oxidation of Silicon) method does not satisfy the driving characteristics of the device. Therefore, STI process has emerged as an alternative.
STI공정은 종래의 필드산화막(Field Oxide ; Fox) 대신 미소폭의 트렌치(Shallow Trench)에 의해 분리막을 형성하는 공정이다. 이러한 STI 공정을 간단히 언급하면, 먼저 실리콘기판 상부에 산화막이나 질화막을 증착하고 여기에 우물형태와 비슷한 쉘로우트렌치를 형성한다. 이후 트렌치매립 산화막으로 트렌치를 매립한 후, 화학기계적연마(CMP)등의 후처리 공정으로 그 상부를 평탄화시키므로써 분리공정을 완성한다.The STI process is a process of forming a separator by a trench having a small width instead of a field oxide (FOX). Briefly referring to this STI process, an oxide film or nitride film is first deposited on a silicon substrate, and a shallow trench similar to a well type is formed thereon. Thereafter, the trench is filled with a trench buried oxide film, and then the upper part is planarized by a post-treatment process such as chemical mechanical polishing (CMP) to complete the separation process.
그러나, 전술한 종래 STI의 CMP는 다음과 같은 문제점이 있다.However, the CMP of the conventional STI described above has the following problems.
즉, CMP를 완료한 각 층의 두께는 해당 층의 형성농도에 크게 영향을 받는다. 즉 해당 층의 농도가 높은 영역은 연마(polishing)가 덜 되고, 농도가 낮은 영역은 연마가 잘 되는 디싱(dishing)현상이 발생되는 문제점이 있다. 이러한 디싱현상의 원인이 되는 농도 불균일 문제를 해결하기 위하여 더미패턴(dummy pattern)을 삽입하는 방법이 고려될 수 있으나, 더미패턴 삽입방법은 많은 시뮬레이션(simulation)과 피드백(feed back)과정을 거쳐야 하므로 시간적, 경제적인 손실이 많다.That is, the thickness of each layer completing CMP is greatly influenced by the formation concentration of the layer. In other words, a high concentration of the layer is less polished, and a low concentration has a problem of dishing. In order to solve the density unevenness causing the dishing problem, a method of inserting a dummy pattern may be considered, but the method of inserting a dummy pattern requires a lot of simulation and feedback processes. There are many time and economic losses.
따라서 전술한 문제점을 해결하기 위한 본 발명의 목적은, CMP의 조건에 따라 각 층의 연마율에 차이가 있음을 이용하여, 산화막 표면에 탄소이온을 주입시킨후 열공정을 실시한 후, 탄소이온이 주입된 산화막의 계면구조를 변화시켜 CMP를 선택적으로 수행함으로써 디싱현상을 방지하기 위한, 디싱을 방지하기 위한 쉘로우트렌치분리 형성방법을 제공하는 데 있다.Therefore, an object of the present invention for solving the above-described problems, using the difference in the polishing rate of each layer according to the conditions of CMP, by injecting carbon ions to the oxide film surface and performing a thermal process, carbon ions The present invention provides a shallow trench isolation formation method for preventing dishing by selectively performing CMP by changing the interfacial structure of the implanted oxide film.
도 1a 내지 도 1d는 본 발명의 일실시예에 따른 디싱을 방지하기 위한 STI 형성방법의 공정도.1A to 1D are process diagrams of an STI forming method for preventing dishing according to an embodiment of the present invention.
< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>
10 : 기판 12 : 질화막10 substrate 12 nitride film
14 : 쉘로우트렌치 16 : 매립층14 shallow trench 16 buried layer
18 : CMP장치18: CMP device
본 발명에 따른 디싱을 방지하기 위한 쉘로우트렌치분리 형성방법은, 쉘로우트렌치를 형성함에 있어서,Shallow trench isolation forming method for preventing dishing according to the present invention, in forming a shallow trench,
기판상부에 상기 쉘로우트렌치 매립시 상기 기판상부의 연마를 원활히 수행하기 위한 소정의 질화막을 형성하는 제1단계; 상기 기판에 소정 깊이의 쉘로우트렌치를 형성하는 제2단계; 상기 형성된 쉘로우트렌치를 소정의 매립물질로 매립하여 매립층을 형성하는 제3단계; 상기 매립층에 소정 깊이로 탄소이온을 주입하는 제4단계; 상기 이온주입된 매립층의 보상을 위해 열처리공정을 실시하는 제5단계; 보상된 상기 매립층을 연마하여 쉘로우트렌치가 형성된 상기 기판상부를 평탄화하는 제6단계를 포함한다.Forming a predetermined nitride film on the substrate to smoothly polish the substrate on the shallow trench; Forming a shallow trench of a predetermined depth in the substrate; A third step of forming a buried layer by filling the formed shallow trench with a predetermined buried material; A fourth step of injecting carbon ions into the buried layer to a predetermined depth; A fifth step of performing a heat treatment process to compensate for the ion implanted buried layer; And polishing the compensated buried layer to planarize the substrate on which the shallow trench is formed.
이하 도면들을 참조하여 본 발명의 바람직한 실시예를 자세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1d는 본 발명의 일실시예에 따른 디싱을 방지하기 위한 STI 형성방법의 공정도이다.1A to 1D are flowcharts illustrating an STI forming method for preventing dishing according to an embodiment of the present invention.
도 1a에 도시한 바와 같이, 본 실시예는 먼저 기판(10) 상부에 질화막(12)을 증착한다. 이 후, 쉘로우트렌치(14)를 4000Å 깊이로 형성한다.As shown in FIG. 1A, the present embodiment first deposits a nitride film 12 on the substrate 10. Thereafter, the shallow trenches 14 are formed to a depth of 4000 mm 3.
이 후 도 1b와 같이, 형성된 쉘로우트렌치(14)에 고농도플라즈마(HighDensity Plasma; 이하'HDP'라 함) 산화막이나, O3TEOS USG를 약 7000Å정도 증착하여 매립층(16)을 형성한다. 다음 매립층(16) 표면으로부터 약 500∼1000Å 깊이에 투입깊이(Projected Range; 이하 'Rp점'이라 함)가 형성되도록 약 25∼50 KeV의 주입에너지로 탄소이온을 이온주입한다.Thereafter, as shown in FIG. 1B, a buried layer 16 is formed by depositing a high-density plasma (HDD) oxide film or O 3 TEOS USG at about 7000 에 in the shallow trench 14. Next, carbon ions are implanted at an implantation energy of about 25 to 50 KeV to form a projected range (hereinafter referred to as an Rp point) at a depth of about 500 to 1000 Å from the buried layer 16 surface.
다음 도 1c와 같이, 1050℃ 정도의 온도에서 열공정을 실시하여, 매립층(16)의 탄소이온 주입부분 및 상단부를 보상한다. 이 열공정을 실시하면 주입된 탄소이온은 매립층 산화막의 Si-O 구조와 반응하여 재결합한다. 즉, 탄소이온이 주입되지 않은 매립층 내부(14x)의 산화막은 O-Si-O의 구조를 그대로 유지하지만, 매립층 외부(14y)의 산화막은 주입된 탄소이온과 반응하므로 O-Si-O와 O-C-O의 구조가 공존하게 된다.Next, as shown in FIG. 1C, a thermal process is performed at a temperature of about 1050 ° C. to compensate for the carbon ion implanted portion and the upper end of the buried layer 16. In this thermal process, the implanted carbon ions react with the Si-O structure of the buried layer oxide film and recombine. That is, the oxide film in the buried layer 14x inside the buried layer, which is not implanted with carbon ions, maintains the structure of O-Si-O, but the oxide film outside the buried layer 14y reacts with the injected carbon ions, thus O-Si-O and OCO The structure of coexists.
이 후 도 1d와 같이, 평탄화시키기 위해 매립층(16)의 상부에 CMP공정을 실시한다.Thereafter, as illustrated in FIG. 1D, a CMP process is performed on the buried layer 16 to planarize.
CMP공정시 동일조건에서 각 막(film)에 대한 연마율(polishinr removal rate)은 차이가 난다. 즉 중요한 막의 연마율을 살펴보면 열산화막(thermal oxide)이 가장 빠르고 SOG, 질화막(nitride) 등의 순서로 낮아진다. 이것은 CMP공정시 화학적 반응을 통해 막의 계면을 활성화시키는 슬러리(slurry)와, 각 막과의 반응정도가 각기 다른 것에 기인한다. 아울러 본 발명에서는 각 막의 연마율 차이를 효과적으로 이용한다.In the CMP process, the polishing rate for each film is different. In other words, when looking at the polishing rate of the important film, the thermal oxide is the fastest and is lowered in the order of SOG, nitride, and the like. This is due to the slurry that activates the interface of the membrane through chemical reaction in the CMP process and the degree of reaction with each membrane is different. In addition, the present invention effectively utilizes the difference in polishing rate of each film.
이와 같은 CMP공정시 O-Si-O구조인 매립층 내부(16x)는 수산화기(OH-) 잘 반응하는 데 반해, O-Si-O와 O-C-O의 구조가 공존하는 매립층 외부(16y)는 수산기와의 반응이 잘 이루어지지 않으므로, 연마율이 떨어지게 된다. 따라서 증착된 매립층(16)의 단차 때문에, 높은 형성된 STI의 활성(active)영역 상부가 먼저 연마된다. 이 때 연마되는 산화막은 탄소이온이 주입된 부분이다. 이 후 계속적으로 연마를 진행하여 트렌치영역 매립층의 상부가 연마되기 시작할 때에는, 활성영역은 순수한 산화막이 연마되고 트렌치영역은 탄소이온이 주입된 산화막이 연마된다. 따라서 CMP의 연마율 차이가 발생함에 따라 CMP를 선택적으로 할 수 있어 디싱현상을 방지할 수 있다. 결국 반도체소자를 전체적으로 고려할 경우, CMP를 완료하면 패턴밀도(pattern density)가 낮은 영역에서도 디싱현상을 방지하여, 평탄한 계면을 형성할 수 있다.In the CMP process, the inside of the buried layer (16x) having the O-Si-O structure reacts well with the hydroxyl group (OH − ), whereas the outside of the buried layer (16y) having the O-Si-O and OCO structures coexists with the hydroxyl group. Since the reaction is not performed well, the polishing rate is lowered. Thus, due to the step of the deposited buried layer 16, the top of the active region of the high formed STI is first polished. At this time, the oxide film to be polished is a portion in which carbon ions are injected. Subsequently, when polishing is continuously performed and the upper portion of the trench region filling layer starts to be polished, the pure oxide film is polished in the active region, and the oxide film implanted with carbon ions is polished in the trench region. Therefore, as the polishing rate difference of the CMP occurs, the CMP can be selectively selected to prevent dishing. After all, when considering the semiconductor device as a whole, when the CMP is completed, it is possible to form a flat interface by preventing dishing even in a region having a low pattern density.
전술한 바와 같이, 본 발명은 패턴밀도에 따른 디싱현상을 방지함으로써, 생산수율을 증대시키고 반도체소자의 전기적 특성을 향상시키는 효과가 있다.As described above, the present invention prevents dishing according to the pattern density, thereby increasing the production yield and improving the electrical characteristics of the semiconductor device.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0786393A (en) * | 1993-09-17 | 1995-03-31 | Toshiba Corp | Device isolating method of semiconductor device |
| JPH09326393A (en) * | 1996-06-04 | 1997-12-16 | Sony Corp | Manufacture of semiconductor device |
| KR19980030769A (en) * | 1996-10-30 | 1998-07-25 | 김광호 | Planarization method of semiconductor device |
| KR19990055195A (en) * | 1997-12-27 | 1999-07-15 | 김영환 | Method of forming an element isolation film of a semiconductor device |
| JP2000012491A (en) * | 1998-06-23 | 2000-01-14 | Nec Corp | Manufacture of semiconductor device |
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| KR20020002810A (en) | 2002-01-10 |
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