KR101019694B1 - Method for forming isolation layer of semiconductor device - Google Patents
Method for forming isolation layer of semiconductor device Download PDFInfo
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- KR101019694B1 KR101019694B1 KR1020030081979A KR20030081979A KR101019694B1 KR 101019694 B1 KR101019694 B1 KR 101019694B1 KR 1020030081979 A KR1020030081979 A KR 1020030081979A KR 20030081979 A KR20030081979 A KR 20030081979A KR 101019694 B1 KR101019694 B1 KR 101019694B1
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- 238000000034 method Methods 0.000 title claims abstract description 34
- 238000002955 isolation Methods 0.000 title claims abstract description 32
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 150000004767 nitrides Chemical class 0.000 claims abstract description 31
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 23
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 17
- 238000005468 ion implantation Methods 0.000 claims abstract description 13
- 239000002002 slurry Substances 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 10
- 238000005498 polishing Methods 0.000 claims abstract description 10
- 238000010438 heat treatment Methods 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims abstract description 6
- 238000000151 deposition Methods 0.000 claims abstract description 3
- -1 nitrogen ions Chemical class 0.000 claims abstract description 3
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 150000002500 ions Chemical class 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- 210000003323 beak Anatomy 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
- H01L21/02329—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen
- H01L21/02332—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen into an oxide layer, e.g. changing SiO to SiON
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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Abstract
본 발명은 반도체 소자의 제조 방법을 개시한다. 개시된 본 발명의 방법은, 반도체 기판상에 패드산화막 및 패드질화막을 차례로 형성하는 단계와, 상기 패드질화막 및 패드산화막을 패터닝하여 상기 반도체 기판의 소자분리 영역을 노출시키는 단계와, 상기 노출된 반도체 기판을 식각하여 트렌치를 형성하는 단계와, 상기 트렌치를 포함한 전면에 상기 트렌치가 매립되도록 매립 산화막을 증착하는 단계와, 상기 매립 산화막에 질소 이온을 주입하되, 상기 질소 이온 주입은 상기 소자분리 영역에서의 Rp(Projected Range)점의 위치가 상기 패드질화막과 수평선상에 위치하도록 수행하는 단계와, 상기 매립 산화막 내에 열처리를 통하여 SiON막을 형성하는 단계와, 상기 매립 산화막을 액티브 영역에 형성된 SiON막이 제거되도록 1차로 CMP하는 단계와, 상기 매립 산화막을 HSS 슬러리를 이용하여 상기 패드질화막이 노출되도록 2차로 CMP하는 단계 및 상기 패드질화막을 제거하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 소자 분리막 형성방법을 제공한다. 본 발명에 따르면, 매립 산화막 내에 이온 주입 및 열처리를 통하여 산화막에 대한 연마 선택비가 우수한 SiON막을 형성하여 CMP 공정시 디싱을 방지할 수 있다. The present invention discloses a method for manufacturing a semiconductor device. The disclosed method includes sequentially forming a pad oxide film and a pad nitride film on a semiconductor substrate, patterning the pad nitride film and the pad oxide film to expose an isolation region of the semiconductor substrate, and exposing the exposed semiconductor substrate. Etching to form a trench, depositing a buried oxide film to fill the trench on the entire surface including the trench, and implanting nitrogen ions into the buried oxide film, wherein the nitrogen ion implantation is performed in the device isolation region. Performing a position of a projected range (RP) point on the pad nitride film and a horizontal line, forming a SiON film through heat treatment in the buried oxide film, and removing the SiON film having the buried oxide film formed in an active region 1 CMP by car, and padding the buried oxide layer using an HSS slurry This provides a step to ensure that the car 2 CMP exposed and the device isolation film forming a semiconductor device comprising the step of removing the pad nitride layer. According to the present invention, it is possible to prevent dishing during the CMP process by forming a SiON film having excellent polishing selectivity with respect to the oxide film through ion implantation and heat treatment in the buried oxide film.
Description
도 1a내지 도 1f는 본 발명의 실시예에 따른 소자분리막 형성방법을 설명하기 위한 공정별 단면도. 1A to 1F are cross-sectional views illustrating processes for forming a device isolation film according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
11: 실리콘 기판 12: 패드산화막11: silicon substrate 12: pad oxide film
13: 패드질화막 14: 트렌치13: pad nitride layer 14: trench
15: 매립산화막 16: SiON막15: buried oxide film 16: SiON film
본 발명은 반도체 소자의 제조방법에 관한 것으로, 보다 상세히는, 반도체 소자의 소자분리막 형성방법에 관한 것이다. The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a device isolation film of a semiconductor device.
기존의 소자분리막은 로코스(LOCOS) 공정에 의해 형성되어져 왔는데, 상기 로코스 공정에 의한 소자분리막은, 주지된 바와 같이, 그 가장자리 부분에서 새부리 형상의 버즈-빅(bird's-beak)이 발생되기 때문에 소자 분리막의 면적을 증대시키면서 누설전류를 발생시키는 단점이 있다. Conventional device isolation film has been formed by a LOCOS process, the device isolation film by the LOCOS process, as is known, the bird's-beak of the beak shape is generated at its edge portion Therefore, there is a disadvantage in that leakage current is generated while increasing the area of the device isolation layer.
따라서, 상기 로코스 공정에 의한 소자분리막 대신에 작은 폭을 가지며 우수한 소자분리 특성을 갖는 STI(Shallow Trench Isolation) 공정을 이용한 소자분리막 형성방법이 제안되었고, 현재 대부분의 반도체 소자는 STI 공정을 적용해서 소자분리막을 형성하고 있다. Therefore, a device isolation film formation method using a shallow trench isolation (STI) process having a small width and excellent device isolation characteristics has been proposed in place of the device isolation film by the LOCOS process. An element isolation film is formed.
상기한 STI 공정은 트렌치를 형성하여, 이를 절연 물질로 매립 및 CMP하여 소자 분리막을 형성한다. In the STI process, a trench is formed, and the trench is embedded and CMP with an insulating material to form an isolation layer.
상기 CMP를 HSS(High Selectivity Slurry)를 이용하여 실시하면, 기존 일반 슬러리를 사용할 때에 비해 월등히 우수한 WIWNU(With In Wafer Nonuniformity) 및 WTWNU(Wafer To Wafer Nonuniformity)를 얻을 수 있는 반면, 20~30㎛ 이상의 넓은 소자 분리 영역의 경우 디싱(Dishing) 현상이 발생하고, 이에 따른, 주변 액티브 영역이 과도하게 연마(OVER CMP)되어 소자 특성에 문제가 발생한다. When the CMP is carried out using HSS (High Selectivity Slurry), it is possible to obtain WIWNU (With In Wafer Nonuniformity) and WTWNU (Wafer To Wafer Nonuniformity), which are superior to those of conventional slurry. In the case of a large device isolation region, dishing occurs, and thus, the peripheral active region is excessively polished (OVER CMP), thereby causing a problem in device characteristics.
이와 같은 디싱 발생을 억제하기 위한 방법으로 액티브 더미 태턴을 넓은 소자 분리 영역에 삽입시켜 디싱 발생을 최소화 하는 방법이 사용되고 있으나, 후속 게이트 형성 지역이나 웰 형성 영역과 같이 터미 패턴을 삽입 시킬 수 없는 소자분리영역이나, 또는, 더미 패턴 밀도가 낮은 소자 분리 영역에서는 디싱 발생이 불가피하게 되고, 이로인해, 주변 액티브 영역이나 액티브 더미 패턴 지역에서 오버 CMP가 발생하게 된다. As a method of suppressing dishing, a method of minimizing dishing by inserting an active dummy tatten into a wide device isolation region is used. In the region or the device isolation region having a low dummy pattern density, dishing is unavoidable, which causes over CMP in the peripheral active region or the active dummy pattern region.
상기 액티브 영역에서의 오버 CMP는 소자 동작 자체에 치명적이며, 액티브 더미 패턴에서의 오버 CMP는 후속 공정 진행시 파티클(paticle) 및 디펙(defect) 발생의 원인이 될 수 있다. The over CMP in the active region is fatal to the device operation itself, and the over CMP in the active dummy pattern may cause particles and defects in subsequent processes.
따라서, 본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출된 것으로서, STI 공정을 이용한 소자분리 공정의 CMP 공정시 디싱 발생을 최소화 할 수 있는 반도체 소자의 소자분리막 형성방법을 제공함에 그 목적이 있다. Accordingly, an object of the present invention is to provide a method for forming a device isolation film of a semiconductor device capable of minimizing dishing during a CMP process of a device isolation process using an STI process. have.
상기와 같은 목적을 달성하기 위하여 본 발명은, 반도체 기판상에 패드산화막 및 패드질화막을 차례로 형성하는 단계와, 상기 패드질화막 및 패드산화막을 패터닝하여 상기 반도체 기판의 소자분리 영역을 노출시키는 단계와, 상기 노출된 반도체 기판을 식각하여 트렌치를 형성하는 단계와, 상기 트렌치를 포함한 전면에 상기 트렌치가 매립되도록 매립 산화막을 증착하는 단계와, 상기 매립 산화막에 질소 이온을 주입하되, 상기 질소 이온 주입은 상기 소자분리 영역에서의 Rp(Projected Range)점의 위치가 상기 패드질화막과 수평선상에 위치하도록 수행하는 단계와, 상기 매립 산화막 내에 열처리를 통하여 SiON막을 형성하는 단계와, 상기 매립 산화막을 액티브 영역에 형성된 SiON막이 제거되도록 1차로 CMP하는 단계와, 상기 매립 산화막을 HSS 슬러리를 이용하여 상기 패드질화막이 노출되도록 2차로 CMP하는 단계 및 상기 패드질화막을 제거하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 소자 분리막 형성방법을 제공한다. In order to achieve the above object, the present invention comprises the steps of forming a pad oxide film and a pad nitride film on the semiconductor substrate in turn, patterning the pad nitride film and the pad oxide film to expose the device isolation region of the semiconductor substrate, Etching the exposed semiconductor substrate to form a trench; depositing a buried oxide film to bury the trench on the entire surface including the trench; and implanting nitrogen ions into the buried oxide film, wherein the nitrogen ion implantation is performed. Performing a position of a projected range (RP) point in an isolation region on the pad nitride film and a horizontal line, forming a SiON film through heat treatment in the buried oxide film, and forming the buried oxide film in an active region CMP is first performed to remove the SiON film, and the buried oxide film is subjected to HSS slurry. In which the pad nitride provides a method comprising: 2 CMP drive so as to be exposed and the device isolation film forming a semiconductor device comprising the step of removing the pad nitride layer.
여기서, 상기 트렌치는 2900~3100Å의 깊이를 타겟으로 식각하며, 상기 매립 산화막은 4000~7000Å의 두께로 증착하고, 상기 질소 이온주입은 상기 Rp점을 매립산화막 표면으로부터 2500~3000Å깊이에 위치 하도록 수행한다. Here, the trench is etched to a depth of 2900 ~ 3100Å to the target, the buried oxide film is deposited to a thickness of 4000 ~ 7000Å, the nitrogen ion implantation is performed to position the Rp point 2500 ~ 3000 2500 deep from the buried oxide film surface do.
또한, 상기 질소 이온 주입은 5E15~1E16/㎤의 이온량과, 60~80KeV의 에너지로 수행하며, 상기 열처리는 800~1200℃의 온도로 수행한다. In addition, the nitrogen ion implantation is performed at an ion amount of 5E15 to 1E16 / cm 3 and energy of 60 to 80 KeV, and the heat treatment is performed at a temperature of 800 to 1200 ° C.
아울러, 상기 1차 CMP는 상기 SiON막과 매립산화막 및 패드질화막에 대한 연마 선택비가 5.7:3.7:1의 비율로 하여 수행하고, 상기 HSS 슬러리를 사용하는 2차 CMP는 상기 매립 산화막과 SiON막 및 질화막의 연마 선택비가 25:2.5:1의 비율로 하여 수행한다. In addition, the primary CMP is carried out with a polishing selectivity ratio of 5.7: 3.7: 1 for the SiON film, the buried oxide film and the pad nitride film, and the secondary CMP using the HSS slurry is the buried oxide film, the SiON film and The polishing selectivity of the nitride film was carried out in a ratio of 25: 2.5: 1.
(실시예)(Example)
이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다. Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1a내지 도 1f는 본 발명의 실시예에 따른 소자분리막 형성방법을 설명하기 위한 공정별 단면도이다. 1A to 1F are cross-sectional views of processes for describing a method of forming a device isolation film according to an exemplary embodiment of the present invention.
도 1a를 참조하면, 실리콘 기판(11) 상에 패드산화막(12)과 패드질화막(13)을 차례로 형성하고, 상기 패드질화막(13) 상에 소자분리 영역을 한정하는 감광막 패턴(도시안됨)을 형성한다. 그런 다음, 상기 감광막 패턴을 식각 장벽으로 이용해서 노출된 패드질화막(13) 부분 및 그 하부의 패드산화막(12) 및 실리콘 기판(11) 을 식각하여 트렌치(14)를 형성한다. Referring to FIG. 1A, a
여기서, 상기 트렌치는 2900~3100Å의 깊이를 타겟으로 식각한다. Herein, the trench is etched with a depth of 2900 ~ 3100Å.
도 1b를 참조하면, 트렌치(14)가 완전 매립되도록 결과물 상에 매립산화막(15)을 4000~7000Å의 두께로 증착한다. Referring to FIG. 1B, the buried
여기서, 상기 매립산화막(15)은 APCVD(Atmospheric Pressure Chemical Vapor Deposition) 또는 HDP(High Density Plasma) 방식으로 하여 매립한다. Here, the buried
도 1c를 참조하면, 상기 증착된 매립 산화막(15)에 N2 이온을 주입하고, 이를 800~1200℃의 온도로 열처리하여 기존 SiO2 결합 구조를 깨드리고 주입된 N2 이온들이 SiO2와 결합하여 SiON막(16)을 형성한다. Referring to FIG. 1C, N 2 ions are implanted into the deposited
여기서, 상기 N2 이온주입은 Rp(Projected Range)점을 매립산화막(15) 표면으로부터 2500~3000Å깊이에 위치하도록 한다. 액티브 영역 및 소자분리 영역의 SiON막(16)은 서로 형성 위치가 다르며, 특히, 소자 분리 영역의 Rp점의 위치는 액티브 영역의 패드질화막(13)과 수평선 상에 위치하도록 하는 것이 바람직하다. In this case, the N2 ion implantation is to place the Rp (Projected Range) point at a depth of 2500 ~ 3000Å from the buried
또한, 상기 이온 주입은 5E15~1E16/㎤의 이온량과, 60~80KeV의 에너지를 사용하여, 고전압 이온 주입 장치를 사용한다. In addition, the ion implantation uses a high voltage ion implantation device using an ion amount of 5E15 to 1E16 / cm 3 and energy of 60 to 80 KeV.
도 1d를 참조하면, 상기 SiON막(16)이 형성된 매립산화막(15)을 액티브 영역의 SiON막(16)이 제거되고 패드질화막(13) 상의 매립산화막(15)이 1000~2000Å의 두께가 남도록 CMP한다. Referring to FIG. 1D, the buried
여기서, 상기 CMP는 통상의 슬러리를 사용하여 수행하는데, 매립 산화막(15)과 SiON막(16)의 연마속도 차이를 이용하여 수행한다. 또한, SiON막(16)과 매립산화막(15) 및 패드질화막(13)은 5.7:3.7:1의 통상의 일반 슬러리에 대한 연마 선택비를 가진다. In this case, the CMP is performed using a conventional slurry, using the difference in polishing rate between the buried
도 1e를 참조하면, 상기 매립산화막(15)을 HSS 슬러리를 사용하여 패드질화막(13)이 노출되어 50Å 정도를 제거하는 공정을 타겟으로 재차 CMP를 실시한다. Referring to FIG. 1E, the buried
여기서, 상기 HSS 슬러리를 사용하는 CMP는 매립산화막(15)과 패드질화막(13) 및 SiON막(16)의 각각에 대한 연마속도 차이를 이용하며, 매립산화막(15)과 SiON막(16) 및 패드질화막(13) 25:2.5:1의 연마선택비를 갖는다. Here, the CMP using the HSS slurry uses the difference in polishing rates for each of the buried
여기서, 상기 HSS슬러리를 이용한 CMP에서 액티브 영역의 매립산화막이 완전히 제거되고 패드질화막이 연마 되기 시작할 때, 넓은 영역의 소자 분리막은 N2 이온 주입 및 열처리에 의해 형성된 SiON막이 연마 되기 때문에 종전의 매립 산화막에 비해 10배 정도의 디싱을 감소시킬 수 있다. Here, in the CMP using the HSS slurry, when the buried oxide film of the active region is completely removed and the pad nitride film begins to be polished, the device isolation film of the wide region is polished to the previous buried oxide film because the SiON film formed by N2 ion implantation and heat treatment is polished. It can reduce dishing by 10 times.
그런다음, 트렌치 식각시에 식각 장벽으로 사용된 패드 질화막을 제거하고, 이 결과로서, 트렌치형의 소자분리막을 형성한다. Then, the pad nitride film used as the etch barrier during the trench etching is removed, and as a result, a trench type device isolation film is formed.
본 발명에 따르면, 매립 산화막 내에 이온 주입 및 열처리를 통하여 산화막에 대한 연마 선택비가 우수한 SiON막을 형성하여 CMP 공정시 디싱을 방지할 수 있다. According to the present invention, it is possible to prevent dishing during the CMP process by forming a SiON film having excellent polishing selectivity with respect to the oxide film through ion implantation and heat treatment in the buried oxide film.
따라서, 본 발명은 소자분리막 자체의 신뢰성을 확보할 수 있음은 물론 STI 공정의 신뢰성도 확보할 수 있고, 나아가, 소자 특성을 향상시킬 수 있다.Therefore, the present invention can secure the reliability of the device isolation film itself, as well as the reliability of the STI process, and further improve the device characteristics.
기타, 본 발명은 그 요지가 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다. In addition, this invention can be implemented in various changes in the range which does not deviate from the summary.
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