JPH0786393A - Device isolating method of semiconductor device - Google Patents

Abstract

PURPOSE:To keep not only a polishing process high in controllability but also a semiconductor device high in characteristics by a method wherein a carbon film is provided as a polishing stop layer in a polishing process wherein a buried insulating film used for isolating devices from each other is flattened. CONSTITUTION:Carbon films 10 and 14 are made to serve as a polishing stop layer, and silicon oxide films 4 and 7 and a silicon nitride film 11 are polished with cerium oxide as abrasive material. A carbon film used as a polishing stopper can be set 20 times or above as low in polishing rate as a silicon oxide, so that polishing can be stopped at a required position. Then, silicon oxide films 4 and 7 and the silicon nitride film 11 are thermally treated for 30 minutes in an atmosphere of water vapor and oxygen at a temperature of 650 deg.C and successively thermally treated for 30 minutes in an atmosphere of oxygen at a temperature of 1050 deg.C. By these thermal treatments, the silicon oxide film 7 is enhanced in density, and the carbon films 10 and 14 can be removed by burning, so that processes can be lessened in number.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a buried device separating method which is a device separating method.

[0002]

2. Description of the Related Art A planarization process in a conventional buried element isolation method mainly includes a resist etch back method and a polishing method using a polycrystalline silicon film as a polishing barrier layer. Here, a polishing method using a polycrystalline silicon film as a polishing barrier layer will be described with reference to FIG.

A silicon thermal oxide film 2 having a film thickness of 35 nm is formed on a silicon substrate 1. This thermal oxide film 2 prevents interface interference due to stress. Next, a polycrystalline silicon film 3 having a film thickness of 300 nm is formed as a polishing barrier layer for polishing described later by LPCVD, and a silicon oxide film 4 is formed to have a film thickness of 400 nm by atmospheric pressure CVD.

Next, a positive resist (not shown) of 1 μm is applied on the silicon oxide film 4. Next, the positive resist is patterned by a well-known lithographic technique, so that the positive resist remains only above the portion of the silicon substrate 1 which will be the element region. Next, the silicon oxide film 4 is etched by reactive ion etching using the positive resist as a mask. next,
The positive resist is removed with a strong acid or the like.

Next, using the silicon oxide film 4 as a mask, the polycrystalline silicon film 3, the silicon thermal oxide film 2, and the silicon substrate 1 are sequentially etched by reactive ion etching to form element isolation regions 5 on the silicon substrate. A groove having a depth of 500 nm is formed in the portion to be formed (FIG. 4A). Next, a silicon thermal oxide film 6 having a film thickness of 35 nm is formed on the inner surface of the groove in order to remove etching damage and to protect the interface of a buried film described later.

After that, a silicon oxide film 7 is formed as a buried film in the element isolation region 5 by LPCVD, for example.
It is deposited to a film thickness of 0 nm (FIG. 4B). Next, a polycrystalline silicon film 8 having a film thickness of 200 nm is formed on the silicon oxide film 7 by the LPCVD method. Further, after applying a positive resist of 1 μm on the polycrystalline silicon film 8,
Among the trenches to be the element isolation regions 5, especially the trench width is 3 μm
Only on the silicon oxide film 7 formed in the groove 9 described above,
The positive resist is patterned by a well-known lithography technique to be left.

Next, using the positive resist as a mask,
The polycrystalline silicon film 8 is etched by chemical dry etching, and the positive resist is removed with a strong acid or the like (FIG. 4C).

Next, using cerium dioxide as an abrasive and using the polycrystalline silicon film 8 as a film (polishing barrier layer) for stopping polishing, the silicon oxide film 7 and the silicon oxide film 4 are polished and etched back. (Fig. 4
(D)). The remaining polishing agent is removed with a strong acid or the like.

Next, heat treatment is performed for 30 minutes in an atmosphere containing oxygen and water vapor at 650 ° C., and further heat treatment is performed for 30 minutes in a nitrogen atmosphere at 1050 ° C. to densify the silicon oxide film 7. Then, the polycrystalline silicon films 3 and 8 are removed by chemical dry etching. Finally, the silicon thermal oxide film is removed in an aqueous solution of ammonium fluoride to complete the element isolation region (FIG. 4).
(E)).

[0010]

The flattening process of the buried film in the above-mentioned buried element isolation method has the following problems. The polishing method using a polycrystalline silicon film as a polishing barrier layer is a highly productive method capable of etching a thick film in a short time, but for example, a large selection ratio with respect to a silicon oxide film used as a buried insulating film can be obtained. Since it is not present, it is difficult to stop the etching before controlling the etch back to completely polish the polycrystalline silicon films 3 and 8 of the polishing barrier layer. In this case, even if the thickness of the polycrystalline silicon film 3 is increased, the substantial depth of the groove formed on the element isolation region becomes large, so that it becomes more difficult to embed the silicon oxide film 7. Further, it takes a long time to form the polycrystalline silicon films 3 and 8 as the polishing barrier layers (stoppers). Further, the step of etching away the polycrystalline silicon films 3 and 8 of the stopper remaining after the polishing step also requires a long time, and at that time, the silicon thermal oxidation between the polycrystalline silicon film 3 and the silicon substrate 1 is performed. It is necessary to increase the thickness of the silicon thermal oxide film 2 so that the film 2 remains, and the silicon oxide film 7 embedded in the element isolation region is greatly thinned in the removal step of the thermal oxide film 2. There was such a problem. The present invention has been made in view of the above circumstances, and an object of the present invention is to solve the above problems and form an element isolation region having a good shape.

[0011]

In order to achieve the above object, the present invention selectively forms a carbon film on an element region forming portion on a semiconductor substrate and makes the exposed surface of the carbon film resistant to oxidation. A step of covering with a film, a step of forming a groove to be an element isolation region in the semiconductor substrate, a step of forming a thermal oxide film on the inner surface of the groove, and a step of removing the oxidation resistant film on the side wall of the carbon film. A step of forming a buried film on the entire surface so as to fill the groove, a step of leaving the buried film in the groove of the element isolation region by polishing with the carbon film as a polishing barrier layer, and removing the carbon film And an element isolation method for a semiconductor element, the method including:

Here, in the step of selectively forming a carbon film on the element region forming portion and covering the exposed surface of the carbon film with an oxidation resistant film, the carbon film is formed on the entire surface of the semiconductor substrate. And a step of forming an oxidation resistant film on the entire surface of the carbon film, a step of selectively leaving the carbon film and the oxidation resistant film on the element region forming portion, and an oxidation resistant film on the entire surface. After forming, the oxidation resistant film may be etched by anisotropic etching to leave the oxidation resistant film on the side wall of the carbon film.

Desirably, a film containing at least silicon and nitrogen is used as the oxidation resistant film for covering the exposed surface of the carbon film. Further, the groove formed in the element isolation region has a groove width of 3 μm or more, and a carbon film may be further selectively formed on the groove as a polishing barrier layer.
Further, the step of removing the carbon film may be performed in an atmosphere containing oxygen. It is more preferable that the atmosphere containing oxygen contains water vapor.

[0014]

When the buried element isolation region is formed according to the present invention, the element isolation region having a good shape can be formed. That is, the polishing rate ratio of the carbon film to the silicon oxide film can be set to 20 or more, and etching by polishing can be stopped at a desired position. Moreover, the problem of metal contamination is not a problem when the carbon film is used as a stopper.

The carbon film can be removed by burning it in an oxidizing atmosphere, and it can be easily removed selectively after planarization. Particularly in the case of embedding a silicon oxide film, a step of densifying the silicon oxide film by heat treatment is necessary. The densification step is more effective when performed in an oxidizing atmosphere containing water vapor and the like, and at the same time as the densification step of the embedded silicon oxide film, the carbon film as the polishing barrier layer can be burned and removed. .

On the other hand, since the carbon film can be easily removed by combustion, on the contrary, there is a problem that the carbon film as the polishing barrier layer is oxidized and removed in the high temperature process before the polishing process. However, in the present invention, the oxidation of the carbon film is suppressed by forming a film having oxidation resistance, for example, a silicon nitride film on the exposed surface of the carbon film. The formation of such an oxidation resistant film on the surface of the carbon film has an advantage of realizing a good element isolation shape and improving element characteristics, in addition to preventing oxidation of the carbon film.

The improvement of the device characteristics will be described below. First, the problem of the conventional technique of flattening the embedded insulating film by polishing using polycrystalline silicon or the like as a polishing barrier layer will be described with reference to FIG.

When the embedded insulating film 21 is polished using the polycrystalline silicon film, the silicon nitride film, or the like as the polishing barrier layer 22 in the planarization of the embedded insulating film for the embedded element isolation, the shape of the element isolation region immediately after polishing is shown in FIG. The shape is as shown in a). Here, after removing the polishing barrier layer 22, the silicon thermal oxide film 23 on the semiconductor substrate 20 is removed by etching in an aqueous solution of ammonium fluoride. Usually, the silicon oxide film which is the buried insulating film 21 is subjected to a densification process. Since the etching rate in the hydrofluoric acid-based wet etching solution is still higher than the etching rate of the silicon thermal oxide film 23, the element isolation region is lower than the surface of the semiconductor substrate 20 as shown in FIG. 5B. The gate electrode 2 is formed into a shape, and the gate oxide film 24 is formed in the element region with this shape.
When No. 5 is formed, the gate electrode 25 surrounds the corner of the groove opening, which is the end of the element region, so that electric field concentration occurs at the corner of the groove opening. Therefore, there is a problem that a kink occurs in the subthreshold characteristic of the transistor and causes a leak current (FIG. 5C).

On the other hand, the case of using the carbon film as the polishing barrier layer as in the present invention will be described with reference to FIG. In the method of the present invention, a carbon film having a large selection ratio with respect to the silicon oxide film is formed as the polishing barrier layer 22, an oxidation resistant film is formed on the side wall of the carbon film, and the silicon oxide film 21 serving as a buried insulating film is formed. Since the silicon oxide film is removed before formation, the element isolation region immediately after the silicon oxide film is buried and mechanically polished has a shape as shown in FIG. Here, after removing the polishing barrier layer 22, the silicon thermal oxide film 23 on the semiconductor substrate 20 is removed, and then the gate oxide film 24,
When the gate electrode 25 is formed, the shape of the element isolation region is shown in FIG.
The shape is as shown in (b). In this shape, the corners of the groove opening are covered with the silicon oxide film 21, and no electric field concentration occurs in the element region. Therefore, no kink is generated in the subthreshold characteristics of the transistor, the leak current is significantly reduced, and good element characteristics can be obtained (3 (c)).

As a polishing barrier layer having a large selection ratio with respect to a silicon oxide film, a film containing a metal such as titanium nitride or a tungsten silicide film as a component can be mentioned. A film containing such a metal as a component. When adopting as a flattening step of the buried element isolation method, there are the following problems. That is, since the buried element isolation region is manufactured before the element manufacturing process of the semiconductor device, it is necessary to suppress metal contamination and the like during the manufacturing of the buried element isolation region, and the film containing the above metal as a component is polished. It is difficult to use as a barrier layer.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor element isolation method of the present invention will be described below with reference to FIG. A silicon thermal oxide film 2 having a film thickness of 20 nm is formed on a silicon substrate 1. Next, the carbon film 10 is sputtered to form a silicon nitride film 11 by LPCVD at a film thickness of 100 nm under a pressure of 10 ⁻⁴ Torr and a substrate temperature of 350 ° C. in an argon atmosphere.
At a pressure of 0.5 to 1.0 Torr and a temperature of 750 to 850
A film having a thickness of 20 nm is formed under the condition of ° C, and a silicon oxide film 4 having a thickness of 400 nm is formed by a normal atmospheric pressure CVD method.
To form a film. However, when forming the silicon nitride film 11, the flow rate ratio of dichlorosilane and ammonia, which is the material gas of the silicon nitride film LPCVD, is 0.1, and the composition ratio of nitrogen to silicon is about 1.3.

Next, a positive resist 12 having a thickness of 1 μm is applied on the silicon oxide film 4. Next, the positive resist 12 is patterned by a well-known lithographic technique to leave the positive resist 12 only above the portion of the silicon substrate 1 which will be the element region (FIG. 1).
(A)).

Next, using the positive resist 12 as a mask, the silicon oxide film 4, the silicon nitride film 11, and the carbon film 10 are anisotropically etched in this order by reactive ion etching. For example, the silicon oxide film 4 and the carbon film 10 may be etched with a mixed gas of CF ₄ and O ₂ , and the silicon nitride film 11 may be etched with a mixed gas of CF ₄ gas or CHF ₃ and CO. Particularly, in the etching of the carbon film 10, the etching is stopped under the condition that the over-etching is not performed so that the underlying silicon thermal oxide film 2 is not exposed (FIG. 1B). This Figure 1
In (b), a part of the carbon film 10 is thinly left on the silicon oxide film 2 and is shown.

Next, the positive resist 12 is removed, for example, in a mixed solution of hot concentrated sulfuric acid and hydrogen peroxide solution. In addition,
In this embodiment, the positive resist 12 is removed with acid or the like, but this removing step can be performed by chemical dry etching using oxygen and carbon tetrafluoride. In this step, it is possible to remove the above-mentioned remaining carbon film 10 at the same time.

Next, using the silicon oxide film 4 as a mask, the remaining film of the carbon film 10 is etched in, for example, an oxygen plasma atmosphere. Thus, the carbon film 10
By anisotropically etching most of the above with the positive resist 12 as a mask, and by etching the residual carbon film 10 with the silicon oxide film 4 as a mask in the subsequent overetching. The amount of etching of the silicon thermal oxide film 2 can be suppressed, and the silicon thermal oxide film 2 can be made thinner than before. When the carbon film 10 is etched in an oxygen plasma atmosphere or the like, the carbon film 10 can be etched at once.

Next, a silicon nitride film 13 is formed on the entire surface by the LPCVD method at a pressure of 0.5 to 1.0 Torr and a temperature of 750.
A film having a film thickness of 25 nm is formed under the condition of ˜850 ° C. However, in forming the silicon nitride film 11, the flow rate ratio of dichlorosilane and ammonia, which is the material gas of the silicon nitride film LPCVD, is 0.1, and the composition ratio of nitrogen to silicon is about 1.3. Next, the entire surface of the silicon nitride film 13 is anisotropically etched so that only the side surfaces of the silicon oxide film 4, the silicon nitride film 11 and the carbon film 10 are left (FIG. 1C). In this embodiment, the carbon film 1
By forming the silicon nitride film 11 having oxidation resistance on the exposed surface of 0, the carbon film 10 is suppressed from being oxidized. The formation of the silicon nitride film 11 on the surface of the carbon film 10 as described above has the advantage that, in addition to preventing the oxidation of the carbon film 10, a good element isolation shape is realized and the element characteristics are improved. As stated.

Next, the silicon thermal oxide film 2 and the silicon substrate 1 are etched by reactive ion etching using the silicon oxide film 4 and the silicon nitride film 13 as masks, and an element isolation region having a depth of 500 nm is formed in the silicon substrate 1. A groove to be 5 is formed. Further, a silicon thermal oxide film 6 having a film thickness of 20 nm is formed on the inner surface of this groove (FIG. 1).
(D)).

In the step of forming the silicon thermal oxide film 6, since the side surface of the carbon film 10 is covered with the silicon nitride film 11, the carbon film 10 is protected without being oxidized. Next, the silicon nitride film 13 is removed in hot phosphoric acid, and then the silicon oxide film 7 is formed on the entire surface by LPCVD.
It is deposited to a film thickness of 0 nm (FIG. 1 (e)).

Next, the carbon film 1 is formed on the silicon oxide film 7.
4 with a film thickness of 100 nm is formed by the sputtering method. After applying a positive resist of 1 μm on the carbon film 14, the positive resist is formed only on the silicon oxide film 7 formed in the groove 9 having a groove width of 3 μm or more among the grooves to be the element isolation regions 5. Are patterned by a well-known lithographic technique to remain. Next, the carbon film 14 is etched by reactive ion etching using the positive resist as a mask. The positive resist on the carbon film 14 is removed in a mixed solution of hot concentrated sulfuric acid and hydrogen peroxide solution (FIG. 1).
(F)).

Next, the silicon oxide films 4 and 7 and the silicon nitride film 11 are polished by using the carbon films 10 and 14 as a polishing barrier layer for etching and using, for example, cerium oxide as a polishing agent (FIG. 1 (g)). The remaining polishing agent is removed with concentrated sulfuric acid or the like. The carbon film used as the stopper in the present embodiment can have a polishing rate ratio with the silicon oxide film of 20 or more, and etching by polishing can be stopped at a desired position.

Next, heat treatment is performed at 650 ° C. for 30 minutes in an atmosphere containing water vapor and oxygen, and then 1050
Heat treatment is performed for 30 minutes in a nitrogen atmosphere at ℃. By this heat treatment, the silicon oxide film 7 can be densified, and at the same time, the carbon films 10 and 14 can be burned and removed, and the number of steps can be reduced. Further, the silicon thermal oxide film 2 is removed in an ammonium fluoride aqueous solution,
The device isolation region 5 is formed by leaving the silicon oxide film 7 only in the device isolation region 5 (FIG. 1H).

According to the present embodiment described above, as described in the operation, it is possible to form the element isolation region having a good shape. Another embodiment of the semiconductor element isolation method of the present invention will be described below with reference to FIG.

A silicon thermal oxide film 2 having a thickness of 35 nm is formed on the silicon substrate 1. Next, the carbon film 3 is formed by the sputtering method.
With a film thickness of 200 nm, and the silicon nitride film 11 is further deposited by LPCVD under a pressure of 0.5 to 1.0 Torr and a temperature of 75.
A film having a thickness of 400 nm is formed under the condition of 0 to 850 ° C.
However, when forming the silicon nitride film 11, a silicon nitride film having a low film formation stress is used with a flow rate ratio of dichlorosilane, which is a material gas of the silicon nitride film LPCVD, to ammonia. The composition ratio of nitrogen to silicon is about 0.9 (FIG. 2A).

Next, a positive resist of 1 μm is applied on the silicon nitride film 11. Next, the positive resist is patterned by a well-known lithographic technique, so that the positive resist remains only above the portion of the silicon substrate 1 which will be the element region.

Then, using the positive resist as a mask, the silicon nitride film 11 and the carbon film 10 are anisotropically etched in this order by reactive ion etching.
Next, the positive resist is removed in a hot concentrated sulfuric acid / hydrogen peroxide mixture solution. Although the positive resist is selectively removed from the carbon film 10 with acid or the like in this embodiment, this removing step can be performed by chemical dry etching using oxygen and carbon tetrafluoride. Further, as shown in Example 1, the carbon film may be removed by etching in two steps.

Next, a silicon nitride film 13 having a film thickness of 25 nm is formed on the entire surface by LPCVD, and the entire surface of the silicon nitride film 13 is anisotropically etched to form side surfaces of the silicon nitride film 11 and the carbon film 10. Only the nitride film 13 is left (FIG. 2B).

After that, the silicon nitride films 11 and 13 are formed.
Using the as a mask, the silicon thermal oxide film 2 and the silicon substrate 1 are etched by reactive ion etching to form a groove to be the element isolation region 5 having a depth of 500 nm in the silicon substrate 1. Further, a silicon thermal oxide film 6 is formed on the inner surface of the groove with a film thickness of 35 nm (FIG. 2C).

Next, the silicon nitride film 13 is formed in hot phosphoric acid.
Then, the silicon oxide film 7 is deposited on the entire surface by LPCVD to a thickness of 550 nm. Further, a carbon film 14 is formed on the silicon oxide film 7 by a sputtering method so as to have a film thickness of 170 nm. Next, a positive resist of 1 μm is coated on the carbon film 14, and the positive resist is applied only on the silicon oxide film 7 formed in the groove 9 having a groove width of 3 μm or more among the grooves to be the element isolation regions. The resist is patterned by a well-known lithography technique to be left. Further, the carbon film 14 is etched by reactive ion etching using the positive resist as a mask. The positive resist on the carbon film 14 is removed in a mixed liquid of hot concentrated sulfuric acid and hydrogen peroxide solution (FIG. 2 (d)).

Next, as in the case of the first embodiment described above, for example, cerium oxide was used as an abrasive, and the carbon film 1 was used.
The silicon oxide film 7 and the silicon nitride film 11 are polished using 0 and 14 as a polishing barrier layer for etching (FIG. 2).
(E)). The remaining polishing agent is removed with a strong acid or the like.

Next, heat treatment is performed for 30 minutes in an atmosphere containing water vapor and oxygen at 650 ° C., and then 1050
Heat treatment is performed for 30 minutes in a nitrogen atmosphere at ℃. By this heat treatment, the silicon oxide film 7 is densified as in the first embodiment, and the carbon films 10 and 14 are formed.
Is burnt to remove. Further, the silicon thermal oxide film 2 is removed in an ammonium fluoride aqueous solution to remove the element isolation region 5
The element isolation region 5 is formed by leaving the silicon oxide film 7 only in the area (FIG. 2F).

In this embodiment, the same effect as in the first embodiment can be obtained, and since the silicon nitride film 11 is formed thick, the carbon film 10 can be protected more reliably and the silicon oxide film 4 can be omitted. This can reduce the number of steps.

In the first and second embodiments, the silicon thermal oxide film 6 formed in the element isolation region has a film thickness of 1
The range of 0 to 40 nm is most desirable for removing damage due to etching and protecting the interface of the embedded film.

Further, the silicon oxide film 7 as the burying film may be left in the groove, so that the film thickness may be in the range of 500 to 800 nm, for example. Further, as the oxidation resistant film, a film containing Si, O and N such as a silicon nitride oxide film may be used in addition to the silicon nitride film.

Furthermore, in the carbon film of the present invention,
A carbon film containing impurities such as H, N, and Si is also included. In addition, various modifications can be made without departing from the scope of the present invention.

[0045]

As described above, according to the present invention, by using a carbon film as a polishing barrier layer for polishing in the step of flattening a buried insulating film for element isolation, good controllability of polishing can be obtained. It is possible to realize the element isolation shape that can secure good characteristics and obtain good element characteristics.

[Brief description of drawings]

FIG. 1 is a process cross-sectional view showing a first embodiment of a semiconductor element isolation method according to the present invention.

FIG. 2 is a process sectional view showing a second embodiment of the element isolation method for a semiconductor element according to the present invention.

FIG. 3 is a cross-sectional view of a buried element isolation region in an element isolation method of a semiconductor device according to the present invention.

FIG. 4 is a process cross-sectional view of a conventional buried element isolation method in which a polishing etchback method is performed using a polycrystalline silicon film as a polishing barrier layer in a planarization step.

FIG. 5 is a cross-sectional view of a buried element isolation region according to a conventional method.

[Explanation of symbols]

 1 Silicon Substrate 2 Silicon Thermal Oxide Film 3 Polycrystalline Silicon Film 4 Silicon Oxide Film 5 Element Isolation Area 6 Silicon Thermal Oxide Film 7 Silicon Oxide Film 8 Polycrystalline Silicon Film 9 Grooves of 3 μm or More 10 Carbon Film 11 Silicon Nitride Film 12 Positive Resist 13 silicon nitride film 14 carbon film 21 insulating film 22 polishing barrier layer 23 silicon thermal oxide film 24 gate oxide film 25 gate electrode

Claims (6)

[Claims] 1. A step of selectively forming a carbon film on an element region forming portion on a semiconductor substrate and coating an exposed surface of the carbon film with an oxidation resistant film, and an element isolation region on the semiconductor substrate. Forming a groove, a step of forming a thermal oxide film on the inner surface of the groove, a step of removing the oxidation resistant film on the side wall of the carbon film, and a buried film formed on the entire surface so as to fill the groove. Element, a step of leaving the buried film in the groove of the element isolation region by polishing, using the carbon film as a polishing barrier layer, and a step of removing the carbon film. Method. 2. The step of selectively forming a carbon film on the element region forming portion and covering the exposed surface of the carbon film with an oxidation resistant film forms the carbon film on the entire surface of the semiconductor substrate. Steps, a step of forming an oxidation resistant film on the entire surface of this carbon film, a step of selectively leaving the carbon film and the oxidation resistant film on the element region forming portion, and forming an oxidation resistant film on the entire surface And a step of etching the oxidation resistant film by anisotropic etching so that the oxidation resistant film remains on the side wall of the carbon film. Method. 3. The element isolation method for a semiconductor device according to claim 1, wherein a film containing at least silicon and nitrogen is used as the oxidation resistant film that covers the exposed surface of the carbon film. 4. The groove formed in the element isolation region has a groove width of 3 μm or more, and a carbon film is further selectively formed as a polishing barrier layer on the groove.
An element isolation method for a semiconductor element as described above. 5. The element isolation method for a semiconductor element according to claim 1, wherein the step of removing the carbon film is performed in an atmosphere containing oxygen. 6. The element isolation method for a semiconductor element according to claim 5, wherein the atmosphere containing oxygen contains water vapor.