JP2000012491A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To flatten the surface of a polished film body without depending on the roughness/denseness of a pattern and without over-polishing and under- polishing by pouring abrasive accelerator into the surface part of the polished film body and chemically/mechanically polishing it with a polishing pad having a specified compression elastic modulus. SOLUTION: A stretch embedded silicon oxide film 5 whose thickness is 1-10 times as much as trench depth, 1000 nm, for example, is deposited by a bias application CVD method. A large quantity of boron 6 is doped so that it is poured into the surface part of the trench embedded silicon oxide film 5, especially, the tip part 7 of a surface projecting part by 80 deg. rotation oblique ion injection, for example. Then, polishing is conducted until a polishing protection film 3 at a base is exposed by using a polishing pad whose compression elastic modulus is 80% and above, 92%, for example, from such state. At that time, slurry where neutral colloidal silica and alkali colloidal silica are dispersed is used as an abrasive material.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for polishing a surface of a film-to-be-polished having a concave and convex surface formed on a semiconductor substrate.
Chemical mechanical polishing (Chemical Mechani)
The present invention relates to a method for manufacturing a semiconductor device that can be almost completely planarized by cal polishing (abbreviated to CMP).

[0002]

2. Description of the Related Art With the miniaturization and ultra-high integration of semiconductor devices, planarization technology by CMP has come to be used. This technique is conventionally used, for example, when flattening the surface of an insulating film formed between wirings of each layer or between layers in a single-layer wiring or a multi-layer wiring, and is becoming quite successful. In recent years, it has become necessary to apply this planarization technique by CMP to so-called trench element isolation.

In the case of the conventional flattening of an insulating film formed between wirings or between layers, the pitch (rule) of the underlying wiring pattern is relatively slow, about 0.8 to 1.0 μm, and is rough. Since the difference between the density of the simple pattern and the density of the dense pattern is small, the entire semiconductor substrate can be easily flattened.

However, in the case of the trench element isolation, for example, an insulating film is deposited inside a trench (trench) provided in a silicon semiconductor substrate for the purpose of electrically insulating element regions such as MOS transistors from each other. Then, for example, the element isolation region is formed by polishing and flattening the upper surface of the insulating film so that the upper surface of the insulating film forms one plane with the surface of the silicon semiconductor substrate. An extremely fine pattern of 6 μm or less and an element isolation region of 0.4 μm or less is formed. An isolated element region of several μm order and a pattern of several tens of μm are further assembled to form several hundred μm order. In such a situation, it is extremely difficult to uniformly flatten the entire area of the semiconductor substrate because the pattern density is intense, for example, the pseudo large area element regions are adjacent to each other. However, in the case of flattening the element isolation region, complete flattening is required because the effect on element characteristics is greater than in the case of flattening an insulating film formed between wirings or between layers. .

What has been considered in order to realize the complete flattening of the insulating film in the trench is disclosed in, for example, Japanese Patent Laid-Open No. 7-28.
As described in Japanese Patent No. 8253, a protective film made of a material having a lower polishing rate than the film to be polished is formed on the surface of the underlying substrate. As a result, when the polishing pad reaches the polishing protective film in a certain pattern, the polishing rate is reduced, so that the polishing delay in other pattern portions can be recovered, and thus the polishing rate varies depending on the pattern density. However, it was thought that complete planarization would be possible. However, in a pattern having a very large difference in density, such as a recent logic device, the polishing rate differs between a pattern having a coarse element region and a pattern having a high density by about 1000 times at the maximum. Have difficulty.

As a method of planarizing a trench element isolation insulating film using CMP, for example, a method described in the EE International Electron Devices Meeting, paragraphs 61 to 64 in 1989, or The method disclosed in JP-A-7-147278 is schematically shown in FIG. First, as shown in FIG. 3A, for example, a silicon oxide film 22 and a silicon nitride film 2 are sequentially formed on a p-type silicon semiconductor substrate 21.
3 by photolithography and reactive ion etching, and then the patterned silicon oxide film 22 and silicon nitride film 23
As a mask by reactive ion etching to form a number of different trench A ₃ spaced and width. next,
Silicon oxide film 2 the inside of the trench A ₃ is thermally oxidized
4 is formed, and a trench buried insulating film 25 is further deposited by using the CVD method. Next, as shown in FIG. 3 (b), by using the inverted mask photolithographic mask used in patterning the trench A _3, perform a photolithography process, embedding the trench on the trench A ₃ A resist mask 25 is formed in the concave portion of the insulating film 25. Next, as shown in FIG. 3 (c), the surface of the trench buried insulating film 25 on the element region is substantially equal to the surface of the trench buried insulating film 25 on the element isolation region by using the reactive ion etching method. So that it is tall,
The insulating film 25 is selectively etched. Next, FIG.
As shown in (d), the remaining corner portions and the trench buried insulating film 25 on the element region and the element isolation region are flattened by CMP to form the trench buried insulating film 25 separated from each other. I do.

However, this method enables flattening independent of pattern density, but requires a photolithography step and an etching step, which necessitates mask design and increases the number of steps, resulting in an increase in manufacturing cost. Problem. Therefore, as a method of forming a trench element isolation insulating film that realizes planarization independent of pattern density without using an inversion mask, Japanese Patent Publication No.
FIG. 4 schematically shows a flattening technique disclosed in Japanese Patent Publication No. 11962.

First, for example, as shown in FIG.
The silicon oxide film 32 and the silicon nitride film 33 sequentially formed on the silicon semiconductor substrate 31 are patterned by photolithography and reactive ion etching, and then the patterned silicon oxide film 32 and silicon nitride the film 33 as a mask by reactive ion etching to form a trench a ₄ having different intervals and widths. Then, the inside of the trench A ₄ to form a silicon oxide film 34 by thermal oxidation, further,
A trench buried insulating film 35 is deposited by using a thermal CVD method. Next, a silicon nitride film 36 having a lower polishing rate than the trench buried insulating film 35 is deposited. Next, when initial polishing is performed, as shown in FIG. 4B, a region where element regions and element isolation regions are alternately formed (hereinafter referred to as L / S).
In the case of an L / S pattern having an interval of several μm to several tens of μm, since the area of each convex portion in contact with the polishing pad during polishing is small, the polishing speed is high, and the step is immediately reduced. Since the L / S pattern of several hundred μm having a relatively large convex area in contact with the pad has a lower polishing rate than the L / S pattern of several μm to several tens μm,
The step is difficult to reduce. However, since the polishing rate of the several hundred μmL / S pattern portion is low, only the silicon nitride film 36 in the convex portion is selectively polished and the silicon nitride film 36 in the concave portion is selectively polished.
Can be selectively left. If the polishing is subsequently performed, several μm to several tens μm are obtained as shown in FIG.
The L / S pattern completely flattens the step and lowers the polishing rate, while the L / S pattern of several hundred μm has the silicon nitride film 36 serving as a polishing protective film remaining in the concave portion, and thus the convex portion. Only the trench buried insulating film 35 can be selectively polished. Therefore, the polishing can be performed without depending on the density of the pattern.
As shown in (d), the trench-buried insulating films 35 separated from each other are formed.

[0009] However, the Japanese Patent Publication No. 7-111962
In practice, even when the method for planarizing a trench element isolation insulating film disclosed in
It is difficult to completely planarize a semiconductor device in which both the L / S pattern and the L / S pattern of several hundred μm are mixed without depending on the density of the pattern. If the silicon nitride film 32 is polished, Over-polishing (dishing) of a wide trench element isolation insulating film can be suppressed,
For example, as shown in FIG. 5D showing a process similar to that of FIG. 4, the polishing rate is low on the element region having a wide width, so that the polishing is not sufficiently polished, resulting in an under-polishing state.

Japanese Patent Application Laid-Open No. 9-162144 discloses that
When planarizing an interlayer insulating film by CMP, As ions or the like are implanted into a convex portion of the interlayer insulating film to soften the film, thereby increasing a polishing selectivity with respect to a portion other than the convex portion, thereby reducing dishing in a portion other than the convex portion. Although it is disclosed to prevent the occurrence, as in the present invention, when a high-hardness polishing pad having a compression elastic modulus of 80% or more is used, a polishing accelerator is injected into a film body to be polished, There is no disclosure of a technique that exerts an unexpected effect of expressing these synergistic effects and obtaining a flatness with a step of the polished surface of 100 ° or less and a dishing amount of 100 ° or less. .

[0011]

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to improve the above-mentioned disadvantages of the prior art, and to mix L / S patterns of several μm to several tens μm and L / S patterns of several hundred μm. In such a case, the surface of the polished film body having irregularities on the surface formed on the semiconductor substrate may be subjected to overpolishing (dishing) or underpolishing without depending on the density of the pattern. It is another object of the present invention to provide a method for manufacturing a semiconductor device which can be almost completely planarized by CMP.

[0012]

SUMMARY OF THE INVENTION The present invention basically employs the following technical configuration to achieve the above object.

That is, as a first aspect according to the present invention,
A polishing accelerator is injected into the surface layer portion of the film body having irregularities on the surface formed on the semiconductor substrate, and then the film body is polished with a polishing pad having a compression modulus of 80% or more. This is a method for manufacturing a semiconductor device to be polished by a chemical mechanical polishing (CMP) method to be used.

According to a second aspect of the present invention, a polishing accelerator is injected into a surface layer portion of a polished film formed on a semiconductor substrate and having irregularities on its surface. A protective film made of a material having a lower polishing rate than the film to be polished is formed thereon, and then the protective film and the film to be polished are polished with a compression modulus of 80% or more. This is a method for manufacturing a semiconductor device which is polished by a CMP method using a pad.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The method of manufacturing a semiconductor device according to the present invention employs the above-described configuration. The feature of the method is that a polishing accelerator is injected into a film to be polished, and thereafter, the polishing accelerator is applied. The polishing target is polished by a CMP method using a polishing pad having a compression elastic modulus of 80% or more, so that the polishing target is substantially completely flat without causing overpolishing (dishing) or underpolishing. It becomes possible to be.

Here, as described with reference to FIG. 6, the compression elastic modulus means that when the polishing pad starts polishing operation,
Separated from the film body to be polished, the thickness in an unloaded state is T
1. During the polishing operation, the thickness in the state of being compressed and deformed in contact with the film body to be polished is T2, and the polishing operation is completed, separated from the film body to be polished again, and the compression deformation is recovered. When the thickness of the state is T3, the degree of the amount of the deformation recovery with respect to the amount of the compression deformation is expressed as a percentage, and is usually measured when the polishing pad is used for the first time, and the compression elasticity is usually measured. Determine the rate. The detailed measurement principle is
"Science in CMP", Chapter 4, published by Science Forum (1997). Therefore, the fact that the compression elastic modulus is as high as 80% or more means that the polishing pad hardly undergoes compression deformation and is highly rigid.
In addition, as such a polishing pad, a pad having a two-layer structure of an elastic foam and a polishing cloth known in the art can be used.

According to the present inventor's opinion, the use of such a high-hardness polishing pad may facilitate the equalization of polishing. However, mechanical stress is applied to the underlying semiconductor substrate. For example, it is unlikely to be a candidate for a polishing pad to be used because a rule may cause mechanical damage to a fine element region such as 0.5 μm and greatly deteriorate characteristics and reliability of an element such as a MOS transistor. Met.

However, the present inventor has intensively studied measures to alleviate the mechanical stress on the underlying semiconductor substrate, and as a result of repeated experiments, as a precondition for using such a high-hardness polishing pad, it has been found that By injecting a polishing accelerator into the entire surface layer portion of the film body to be polished formed on the substrate, or into a specific portion such as a convex portion, the polishing amount when using the high-hard polishing pad is dramatically increased. To improve,
In other words, when the conventional hard polishing pad having a low compression elastic modulus is used, the polishing amount is significantly increased so as not to be seen, and moreover, unexpectedly, when the pattern density varies unevenly. In addition, the injection of these polishing accelerators and the use of a high-hardness polishing pad can provide a surface with very few steps even in a rough pattern or a dense pattern, and significantly reduce overpolishing (dishing) and underpolishing. The inventor has found that the present invention is completed.

That is, FIG. 7 shows a silicon oxide film (undoped SiO ₂ ) in which a polishing accelerator has not been injected by using a high-hard polishing pad having a compression modulus of 92% according to the present invention. , And the polishing amount when the TEOS / BPSG film was polished are shown in comparison. As is clear from the figure, in the case of the TEOS / BPSG film containing boron (B) and phosphorus (P) as the polishing accelerator, the polishing amount is about three times faster than the polishing target body containing no impurities. I understood that.

As shown in FIG. 8, a 10 μm L / S pattern and a high-hardness polishing pad according to the present invention and a conventional ordinary hard polishing pad are used as described in the following Examples. 3 mm square surface level difference after polishing each trench element isolation insulating film of the pseudo large area pattern is shown for comparison, and the compression modulus is 80% or more.
For example, when a high-hardness polishing pad of 92% according to the present invention is used, the step is remarkably reduced to 100 ° or less in about 4 minutes without depending on the density of the pattern, and the conventional method shown in FIGS. It has been found that there is no disadvantage that underpolishing occurs in a pseudo large area pattern as in the method. By utilizing this phenomenon, it is possible to selectively polish the convex portion of the film body to be polished even in a wide element region. On the other hand, the compression modulus is less than 80%, for example, 7%.
With a 0% hard polishing pad, even if polishing is performed for 4 minutes, there is a step difference of 1000 ° especially in a pseudo large area pattern.
Even if the polishing is performed for a longer time than this, the step is not reduced.

The polishing accelerator used in the present invention has the ability to increase the polishing rate of the film to be polished by, for example, changing the structure, crystal structure, hardness, etc. of the film to be polished. Any material may be used. For example, an organic solvent such as alcohol or aldehyde may be applied and penetrated. However, the film-to-be-polished is formed on the semiconductor substrate by silicon, silicon oxide, silicon nitride, or the like. In the case of a film made of a silicon compound, the impurity for silicon, that is, the hardness of the film made of silicon or silicon compound penetrates into the crystal structure of the film made of silicon or silicon compound. Is preferably one or more impurities selected from, for example, boron, phosphorus, arsenic and the like.

In order to flatten the film to be polished, which is intended by the present invention, it is preferable to selectively inject the polishing accelerator into the convex portion of the film to be polished. As a specific method, for example, it is preferable to use a rotating oblique ion implantation method.

Further, in the present invention, the film body to be polished may be any film body having the unevenness formed on the surface of the semiconductor substrate formed as described above. As described above, it is more effective when the insulating film is a trench-buried insulating film.
This is particularly effective when the film is formed by a bias application film forming method such as a CVD method for applying a bias such as an F bias, and has a mountain-shaped convex portion unique to the surface, such as a silicon oxide film. is there. However, the present invention can be applied to other film bodies such as an insulating film formed between wirings of each layer in a single-layer wiring or a multi-layer wiring or between layers as the film body to be polished.

Alternatively, the film body to be polished may be formed by implanting the impurity during the formation of the film body to be polished, for example, by the above-described TE.
It may be a film such as an OS / BPSG film. The TEO
The S-BPSG film is obtained by reacting, for example, tetraethoxyorthosilicate (TEOS), diborane, phosphine and, if necessary, ozone by a CVD method. In the case of a film to be polished into which the impurity has been implanted during the film formation, the same or different polishing accelerator may or may not be injected after the film formation.

According to the present invention, the surface of the film to be polished can be substantially completely flattened, for example, over the entire area of the semiconductor substrate by polishing the film to be polished. The upper surface of the polished film body is polished and flattened so that the upper surface of the polished film body forms one plane with the surface of the silicon semiconductor substrate to form an element isolation region. In some cases, for example, a flatness with a surface step of 100 ° or less and a dishing amount of 100 ° or less can be finally obtained.

[0026]

Next, a specific example of a method of manufacturing a semiconductor device according to the present invention will be described in more detail with reference to the drawings.

FIGS. 1 and 2 are cross-sectional views for explaining the steps of one specific example of the method for manufacturing a semiconductor device according to the present invention. The cross-sectional views shown in FIG. 1 and FIG.
L / S pattern part of order and L / S of several hundred μm order
A mask layout in which S pattern portions are mixed is shown.

First, as shown in FIG.
The thickness is, for example, 50
A silicon oxide film 2 having a thickness of nanometer and a polishing protection film 3 having a thickness of, for example, 100 nanometer and made of, for example, a silicon nitride film are formed as required. Then, the the silicon oxide film 2 and the polishing protective film 3 as a mask, by photolithography and reactive ion etching to form a trench A ₁ having a depth of, for example, 300 nm, further, by thermal oxidation or CVD A silicon oxide film 4 having a thickness of, for example, 10 nanometers is formed in the trench. The silicon oxide film 4 is intended to modify the shape of the inner wall of the trench A _1, it is not necessarily required.

Next, a silicon oxide film 5 with a thickness of, for example, 1 to 10 times the trench depth, specifically, for example, 1000 nanometers is deposited by, for example, a bias application CVD method. Next, the dose is set to, for example, 5E15 cm ^{− so} that, for example, boron 6 is implanted in a large amount into the surface layer portion of the trench-embedded silicon oxide film 5, in particular, the tip portion 7 of the surface convex portion, particularly by the 80 ° rotation oblique ion implantation. FIG. 1 (b) with doping as ²
State. From this state, polishing is performed using a polishing pad having a compression elastic modulus of 80% or more, specifically, for example, 92% until the underlying polishing protective film 3 is exposed. At this time, for example, a slurry in which neutral colloidal silica or alkaline colloidal silica is dispersed is used as an abrasive. In the initial stage of polishing shown in FIG.
/ S pattern part is on the order of tens of μm L
Although the polishing rate is lower than that of the / S pattern portion, polishing is performed using a polishing pad having boron 6 doped into the surface layer portion of the trench-embedded silicon oxide film 5 and having a compression elastic modulus of 80% or more. With this, the trench-filled insulating film 5 in the concave portion is hardly polished,
The convex silicon oxide film 5 can be selectively polished.

When the polishing is subsequently performed, as shown in FIG. 1C, the L / S pattern portion of the order of several tens of μm has almost no step, so that the polishing speed is reduced.
On the other hand, the L / S pattern portion of the order of several hundred μm is also polished by using a polishing pad having a compression elastic modulus of 80% or more, so that the silicon oxide film 5 with the trenches embedded in the convex portions can be efficiently formed. In addition, it can be selectively polished and has a substantially flat shape. Further, when polishing is performed, FIG.
As shown in (d), the trench-embedded silicon oxide film 5 is formed only in the element isolation region, and is further polished.
Eventually, a trench element isolation silicon oxide film 5 in which the surface of the silicon oxide film forms the same plane as the surface of the semiconductor substrate 1 is completed. At this time, the step of the substrate 1 is set at 100 ° or less, and the dishing amount is set at 100 °.
Almost completely flattening or less was achieved.

Next, the specific example shown in FIG. 2 will be described. First, as shown in FIG. 2A, a p-type silicon semiconductor substrate 11 is formed on the p-type silicon semiconductor substrate 11 in the same manner as in the example of FIG. Then, a silicon oxide film 12 having a thickness of, for example, 10 nm and a silicon nitride film 13 having a thickness of, for example, 200 nm are formed. Next, using the silicon oxide film 12 and the silicon nitride film 13 as a mask, a trench A ₂ having a depth of, for example, 500 nm is formed by photolithography and reactive ion etching, and the inside of the trench A ₂ is thermally oxidized. Then, a silicon oxide film 14 having a thickness of, for example, 20 nanometers is formed. Next, for example, thermal CVD
A silicon oxide film 15 with a trench of 1000 nm is buried by the method. Then, the dose is set to, for example, 1E so that boron 16 is contained in the tip 17 of the convex portion of the oxide film 15 by oblique ion implantation at, for example, 70 °.
Doping as 16 cm ^-2 .

Next, a polishing protective film 18 made of a silicon nitride film having a thickness of, for example, 10 nm is formed on the trench-embedded silicon oxide film 15. Next, as shown in FIG. 2B, initial polishing is performed using a polishing pad having a compression modulus of 80% or more. At this time, a slurry in which neutral colloidal silica or alkaline colloidal silica is dispersed is used as an abrasive. The L / S pattern portion of the order of several tens of μm has a high polishing rate, so that the step is reduced immediately. However, the L / S pattern portion of the order of several hundred μm has a lower polishing rate, so the step is reduced. Hard to do.

When the polishing is subsequently performed, as shown in FIG. 2C, the pattern portion of the order of several tens of μmL / S has almost no level difference, so that the polishing rate decreases. On the other hand, the L / S pattern portion of the order of several hundred μm is formed by doping a large amount of boron 16 on the surface of the convex portion and performing polishing using a polishing pad having a compression elastic modulus of 80% or more. The silicon oxide film 18 in the trench can be efficiently and selectively polished without substantially polishing the silicon nitride film 18 in the recess.

When further polishing is performed, as shown in FIG. 2D, a trench-buried silicon oxide film 15 is formed only in the element isolation region.

In the above example, a silicon nitride film is used as a protective film made of a material having a lower polishing rate than the film to be polished. However, the protective film used in the present invention is a silicon nitride film. However, the present invention is not limited to this. For example, it is possible to use a silicon oxide film having a polishing rate lower than that of the silicon oxide film to be polished, for example, a silicon oxide film based on another manufacturing method as the protective film. Further, in the above embodiments, the semiconductor substrate used is a silicon semiconductor substrate, but the same effect can be obtained in the case of another type of semiconductor substrate.

[0036]

According to the method of manufacturing a semiconductor device according to the present invention,
Since the technical configuration as described above is employed, a polishing accelerator is injected into the film body to be polished, and then the film body is polished using a polishing pad having a compression elastic modulus of 80% or more.
By polishing by the MP method, the film body to be polished can be almost completely flattened without causing overpolishing (dishing) or underpolishing.

[Brief description of the drawings]

1 and 2 are cross-sectional views for explaining the steps of the method of the present invention, and FIGS. 3, 4, and 5 are cross-sectional views for explaining a conventional example. FIG. 6 is a diagram showing the relationship between the impurity concentration and the polishing rate, and FIG. 7 is a diagram showing the relationship between the polishing pad and the step reduction.

FIG. 1 is a cross-sectional view for explaining a step in a specific example of a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a cross-sectional view for explaining steps of another specific example of the method for manufacturing a semiconductor device of the present invention.

FIG. 3 is a cross-sectional view for describing steps of a conventional semiconductor device manufacturing method.

FIG. 4 is a cross-sectional view for explaining steps of a conventional semiconductor device manufacturing method.

FIG. 5 is a cross-sectional view for explaining steps of a conventional semiconductor device manufacturing method.

FIG. 6 is a schematic diagram for explaining a method of calculating a compression modulus of a high-hardness polishing pad used in the present invention.

FIG. 7 is a graph showing a polishing rate of a film body to be polished in the present invention.

FIG. 8 is a graph showing the rate of disappearance of a step due to polishing in the present invention in comparison with a conventional example.

[Explanation of symbols]

1, 11, 21 semiconductor substrate 2,12,22 silicon oxide film 3,13,23 polishing protective film _{A 1, A 2, A 3} , A 4, A 5 trench 4,14,24 silicon oxide film 5 and 15, 25 Trench groove buried insulating film 6, 16, 26 Rotating oblique ion implantation 7, 17, 27 Impurity doped portion 18 Protective film

Claims (12)

[Claims] 1. A polishing accelerator is injected into a surface layer portion of a film body having irregularities on a surface formed on a semiconductor substrate,
A method of manufacturing a semiconductor device, comprising: thereafter, polishing the film to be polished by a chemical mechanical polishing method using a polishing pad having a compression elastic modulus of 80% or more. 2. A polishing accelerator is injected into a surface layer portion of a film-to-be-polished body formed on a semiconductor substrate and having irregularities on its surface,
Thereafter, a protective film made of a material having a lower polishing rate than that of the film to be polished is formed on the film to be polished, and then the protective film and the film to be polished have a compression elastic modulus of 80.
%. A method for manufacturing a semiconductor device, wherein the polishing is performed by a chemical mechanical polishing method using a polishing pad of% or more. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the film body to be polished is made of silicon or a silicon compound, and the polishing accelerator is an impurity for silicon. 4. The method according to claim 3, wherein the impurities are one or more impurities selected from boron, phosphorus and arsenic. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the polishing accelerator is selectively injected into a convex portion of the surface of the film body to be polished. 6. The method for manufacturing a semiconductor device according to claim 3, wherein the doping of the surface layer portion of the film body to be polished is performed by a rotating oblique ion implantation method. 7. The semiconductor device according to claim 1, wherein the film body to be polished is a trench-buried insulating film formed in a trench formed in a surface portion of the semiconductor substrate. A method for manufacturing a semiconductor device. 8. The method of manufacturing a semiconductor device according to claim 1, wherein said film body to be polished is a film body formed by a bias applying film forming method. 9. The method for manufacturing a semiconductor device according to claim 8, wherein said film body to be polished is a silicon oxide film formed by a bias application film forming method. 10. The method of manufacturing a semiconductor device according to claim 3, wherein the impurity is doped during the formation of the film body to be polished. 11. The film object to be polished is TEOS / BPSG.
The method according to claim 10, wherein the semiconductor device is a film. 12. The step of polishing the surface of the film body to be polished is 100 ° or less, and the dishing amount is 10 or less.
2. The method according to claim 1, wherein the angle is 0 ° or less.
2. The method for manufacturing a semiconductor device according to item 1.